KR20000009987A - Addressing method of plasma display panel - Google Patents

Abstract

PURPOSE: A method of addressing a plasma display panel is provided to prevent deterioration of image quality by reducing a cross-talk phenomenon in high speed scan. CONSTITUTION: Scan electrode lines are arranged in a line and address electrode lines are arranged to be perpendicular with the scan electrode lines, so that pixels corresponding to respective cross points are provided in the plasma display panel. The scan electrode lines are divided into a plurality of blocks. The blocks are sequentially scanned and a scan pulse is applied to the scan electrode lines in non-adjacent order. Image data corresponding to a scan order of the scan electrode lines is applied to the address electrode lines.

Description

Addressing method of plasma display panel

The present invention relates to an addressing method of a plasma display panel, and more particularly, to a method in which the reset, address and sustain discharge steps are applied to an address step in a driving scheme performed in a unit subfield.

1 illustrates an electrode line pattern of a typical plasma display panel. FIG. 2 schematically shows a cross section for one pixel of the pattern of FIG. 1. Referring to the drawings, a typical surface discharge plasma display panel includes address electrode lines A1, A2, A3, ..., Am, a first dielectric 21, a phosphor 22, and scan electrode lines Y1, Y2. ,..., Yn ₋₁ , Yn, 231, 232, common electrode lines X, 241, and 242, a second dielectric 25, and a protective film 26 are provided. Each scan electrode line Y1, Y2,..., Yn ₋₁ , Yn includes an indium tin oxide (ITO) electrode line 231 for scanning and a bus electrode line 232 for scanning. Similarly, the common electrode lines X, 241 and 242 are also composed of the common ITO electrode line 241 and the common bus electrode line 242. The plasma forming gas is sealed in the space between the protective film 26 and the first dielectric 21.

The address electrode lines A1, A2, A3, ..., Am are applied in a constant pattern to a lower substrate (not shown) as the first substrate. The first dielectric 21 is applied over the address electrode lines A1, A2, A3,..., Am. The phosphor 22 is applied on the first dielectric 21 in a predetermined pattern. In some cases, formation of the first dielectric 21 is omitted, and the phosphor 22 is applied in a predetermined pattern on the address electrode lines A1, A2, A3,..., Am. The scan electrode lines Y1, Y2, ..., Yn- ₁ , Yn, 231, 242 and the common electrode lines X, 241, 242 are the address electrode lines A1, A2, A3, ... Is formed in a constant pattern on the upper substrate (not shown) as the second substrate so as to be orthogonal to Am). Each intersection point defines a corresponding pixel. The second dielectric 25 is applied to the scan electrode lines Y1, Y2,..., Yn ₋₁ , Yn, 231, and 232 and the common electrode lines X, 241, and 242. The protective film 26 for protecting the panel from the strong electric field is entirely coated on the second dielectric 25.

A driving scheme generally applied to such a plasma display panel is an address / display separation driving scheme in which reset, address and sustain discharge steps are performed in a unit subfield. In the application of this address / display separation driving method, conventionally, scan pulses are sequentially applied to scan electrode lines adjacent to each other in an address step. When such a conventional addressing method is applied to a high definition plasma display panel that must be addressed at a high scanning speed, cross-talk in which wall charges generated after address discharge interfere with adjacent pixels is generated. Are more likely to happen. As a result, there is a high possibility that the image quality is degraded due to mis-discharge.

SUMMARY OF THE INVENTION An object of the present invention is to provide an addressing method which can reduce the occurrence of cross-talk even at a high scanning speed when driving a plasma display panel.

1 is an electrode line pattern diagram of a typical plasma display panel.

FIG. 2 is a schematic cross-sectional view of one pixel of the pattern of FIG. 1.

3 is a waveform diagram of voltages applied to electrode lines according to an addressing method of a plasma display panel according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

21, 25 dielectric, 22 phosphor,

Y1, Y2, ..., Yn- ₁ , Yn, 231, 232 ... scanning electrode lines,

X, 241, 242, common electrode line, 26, protective film,

A1, A2, A3, ..., Am ... address electrode line,

B0 ... 0th block, B1 ... 1st block.

In the addressing method of the present invention for achieving the above object, a plasma display panel in which scan electrode lines are aligned with each other, address electrode lines are orthogonally aligned with respect to the scan electrode lines, and pixels corresponding to each intersection are defined. Applies to The method includes dividing the scan electrode lines into a plurality of blocks. Each block is sequentially scanned, and scanning pulses are applied to the scan electrode lines in the order in which they are not adjacent to each other in the block being scanned. Further, image data corresponding to the driving order of the scan electrode lines is applied to the address electrode lines.

Accordingly, since the scan electrode lines are scanned in an order not adjacent to each other, it is possible to reduce the occurrence of cross-talk even at a high scanning speed.

Hereinafter, preferred embodiments of the present invention will be described in detail.

3 illustrates waveforms of voltages applied to electrode lines according to an addressing method of a plasma display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 3, each of the divided blocks B0, B1, ... is formed of five scan electrode lines Y1, Y2, ..., Yn. In the address period dw in the unit sub-field, each of the divided blocks B0, B1, ... is sequentially scanned while not being adjacent to each other within the blocks B0, B1, ... that are scanned. Negative polarity in the scan electrode lines in the order (Y2-> Y4-> Y1-> Y3-> Y5-> Y7-> Y9-> Y6-> Y8-> Y10-> ......-> Yn) A scan pulse of negative voltage -Vy is applied. Also, the driving sequence of the scan electrode lines (Y2-> Y4-> Y1-> Y3-> Y5-> Y7-> Y9-> Y6-> Y8-> Y10-> ......-> Yn) Corresponding image data is applied to the address electrode lines Am.

Thus, they are not adjacent to each other (Y2-> Y4-> Y1-> Y3-> Y5-> Y7-> Y9-> Y6-> Y8-> Y10-> ......-> Yn). Since the scan electrode lines are scanned, the occurrence of cross-talk can be reduced even at high scanning speeds.

In the first reset period bc, a pulse of voltage Vaw is applied to the address electrode lines Am, a pulse of voltage Vs + Vw is applied to the common electrode lines X, and scan electrode lines Y1, Y2, ... , Yn) is applied to 0 [V]. The voltage Vs + Vw is a voltage obtained by adding the voltage Vw to the sustain discharge voltage Vs, which is higher than the voltage Vaw. Accordingly, since a pulse having a relatively high voltage Vs + Vw is applied between the common electrode lines X and the scan electrode lines Y1, Y2,..., And Yn, the common electrode lines X and the scan electrode are scanned. Primary surface discharge occurs between the electrode lines Y1, Y2, ..., Yn (time b of FIG. 3). Positive wall charges are accumulated in the passivation layer 26 under the scan electrode lines 231 and 232 of FIG. 2, and the passivation layer under the common electrode lines 241 and 242. At (26) negative wall charges are accumulated.

The voltage of the wall charges accumulated in the first reset period b-c is a voltage capable of initiating re-discharge. In the second reset period c-d, 0 [V] is applied to the address electrode lines Am, the common electrode lines X, and the scan electrode lines Y1, Y2, ..., Yn. Accordingly, secondary surface discharge occurs between the common electrode lines X and the scan electrode lines Y1, Y2,..., And Yn by the wall charges accumulated in the first reset period b-c. And the wall charges of all the pixels are erased.

In the address period dw, in a state where a pulse of voltage Vax is applied to the common electrode lines X, each of the blocks B0, B1, ... is sequentially scanned, and the scanned blocks B0, B1, Within ...), non-adjacent sequence (Y2-> Y4-> Y1-> Y3-> Y5-> Y7-> Y9-> Y6-> Y8-> Y10-> ......- > Yn), a scan pulse of negative voltage -Vy is applied to the scan electrode lines. While the scan pulse of the negative voltage -Vy is applied to one scan electrode line Y1, Y2, ..., or Yn (in the case of the first scan electrode line Y1, fg section), the selected address electrode line ( When a pulse of the address voltage Va is applied to Am), the counter discharge is performed in the corresponding pixel. This is because a pulse of the counter discharge voltage Va + Vy is applied between the corresponding scan electrode line Y1, Y2, ..., or Yn and the selected address electrode lines Am. While the counter discharge is performed in this way, the counter discharge is stopped when the voltage of the corresponding scan electrode line Y1, Y2, ..., or Yn is switched to 0 [V]. Positive wall charges are accumulated below the scan electrode lines 231 and 232 of the selected pixels.

Next, in the first sustain discharge period x-y1, a pulse having a voltage of Vs / 2 which is 1/2 of the scan voltage Vs is applied to the address electrode lines Am, and 0 [V] is applied to the common electrode lines X. The pulse of the sustain discharge voltage Vs is applied to the scan electrode lines Y1, Y2, ..., Yn. That is, in the state where positive wall charges are accumulated below the scan electrode lines Y1, Y2, ..., or Yn of the selected pixels, the scan electrode lines Y1, Y2, ..., Yn ) And a relatively high reverse voltage pulse is applied between the common electrode lines X, and the surface discharge is performed in the selected pixel. When surface discharge is performed in the selected pixel as described above, plasma is formed in the gas layer of the corresponding region, and the phosphor (22 in FIG. 2) is excited by the ultraviolet radiation to generate light. Negative wall charges are accumulated below the scan electrode lines 231 and 232 of the selected pixels, and positive wall charges are accumulated below the common electrode lines 241 and 242.

In the subsequent sustain discharge period y2-y3, the pulse of the voltage Vs / 2 which is 1/2 of the scan voltage Vs is applied to the address electrode lines Am, and the sustain discharge voltage is applied to the common electrode lines X. A pulse of Vs is applied 0 [V] to the scan electrode lines Y1, Y2, ..., Yn. That is, when a pulse having a relatively high reverse voltage is applied between the scan electrode lines Y1, Y2,..., Yn and the common electrode lines X while the wall charges are accumulated, the surface discharge is performed in the selected pixel. This is done. Positive wall charges are accumulated below the scan electrode lines 231 and 232 of the selected pixel, and negative wall charges are accumulated below the common electrode lines 241 and 242. When surface discharge is performed in the selected pixel as described above, plasma is formed in the gas layer of the corresponding region, and the phosphor 22 is excited by the ultraviolet radiation to generate light. The first and second sustain discharge steps are repeatedly performed during a set sustain discharge cycle, so that generation of light in the selected pixel is maintained.

As described above, the order of the scan electrode lines scanned in the address period dw is Y2-> Y4-> Y1-> Y3-> Y5-> Y7-> Y9-> Y6-when five lines are blocked. > Y8-> Y10-> Y12-> Y14-> Y11-> Y13-> Y15-> ......-> Yn. Therefore, the number x of the scan electrode line corresponding to the scanning order in each block B0, B1, ... is obtained by the following equation (1).

x = j⋅k + m

In Equation 1, j is the number of scan electrode lines allocated to the unit block, k is the corresponding block number allocated in the order of '0' to a positive integer, and m is the scan corresponding to the scanning order of the 0th block. The number of electrode lines.

When 5 lines are blocked as shown in FIG. 3, j is 5, k is 0, 1, 2, ..., and m is 2, 4, 1, 3, 5. Therefore, j corresponding to the first electrode line to be scanned in the 0th block is 5, k is 0, and m is 2, so when it is substituted into Equation 1 above, the electrode to be first scanned in the 0th block B0 is The number x of the line is two. That is, the secondly arranged scan electrode line Y2 is the electrode line to be scanned first. According to this algorithm, j corresponding to the second electrode line to be scanned in the first block (B1) is 5, k is 1, and m is 4, so substituting this in Equation 1 above, The number x of the electrode lines is nine. That is, the ninth arranged scan electrode line Y9 is the electrode line to be scanned second in the first block B1.

As described above, according to the addressing method of the plasma display panel according to the present invention, it is possible to reduce the occurrence of cross-talk at high scanning speed during driving of the plasma display panel, thereby reducing the probability of image quality deterioration due to mis-discharge. have.

The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art.

Claims (2)

In the addressing method of a plasma display panel in which scan electrode lines are aligned with each other, address electrode lines are orthogonal to the scan electrode lines, and pixels corresponding to each intersection point are defined. Dividing the scan electrode lines into a plurality of blocks; Scanning the blocks sequentially and applying scan pulses to the scan electrode lines in a non-adjacent order within the blocks being scanned; And And applying image data corresponding to the scanning order of the scan electrode lines to the address electrode lines. The method of claim 1, wherein the number of the scan electrode line corresponding to the scanning order in each block, If the number of scan electrode lines allocated to the unit block is j, the corresponding block number assigned from '0' to a positive integer is k, and the number of scan electrode lines corresponding to the scan order of the 0th block is m, j⋅k + m An addressing method of a plasma display panel, characterized by the following equation.