KR100310687B1 - Method for driving plasma display panel - Google Patents

Abstract

According to the driving method of the present invention, an interlaced image signal having a resolution corresponding to the number of Y electrode lines to which a scan driving signal is applied in a plasma display panel, or a sequential image signal having a resolution corresponding to half of the number of Y electrode lines is processed. The plasma display panel is driven in the set subfield units. The method includes applying a display data signal and forming wall charges. In the step of applying the display data signal, the display data signal corresponding to the interlaced video signal or the sequential video signal is applied to the address electrode lines arranged in the direction orthogonal to the Y electrode lines. In the forming of the wall charges, a scan pulse corresponding to the Y electrode lines is applied simultaneously with the application of the display data signal, and the scan pulses are sequentially applied in units of two adjacent Y electrode lines, thereby forming Wall charges are formed.

Description

Driving method for plasma display panel {Method for driving plasma display panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel of a three-electrode surface discharge method.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 illustrates an electrode line pattern of the plasma display panel of FIG. 1. FIG. 3 shows an example of one pixel of the panel of FIG. 1. Referring to the drawings, between the front and rear glass substrates 10 and 13 of the general surface discharge plasma display panel 1, address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am Dielectric layers 11 and 15, Y electrode lines Y ₁ , Yn, X electrode lines X ₁ , Xn, phosphor 16, barrier 17, and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am are formed in a predetermined pattern on the front surface of the rear glass substrate 13. The lower dielectric layer 15 is entirely coated on the front surface of the address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am. The barrier ribs 17 are formed on the front surface of the lower dielectric layer 15 in a direction parallel to the address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am. These partitions 17 function to partition the discharge area of each pixel and to prevent optical cross talk between each pixel. The phosphor 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., Xn) and the Y electrode lines (Y ₁ , ..., Yn) are the address electrode lines (A ₁ , A ₂ , ..., Am- ₁ , Am). It is formed in a predetermined pattern on the back of the front glass substrate 10 so as to be orthogonal. Each intersection point defines a corresponding pixel. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Yn) is an indium tin oxide (ITO) electrode line (Xna, Yna of FIG. 3) of a transparent conductive material. And a bus electrode line (Xnb, Ynb of FIG. 3) made of metal are combined. The upper dielectric layer 11 is formed by coating the entire surface on the rear surfaces of the X electrode lines X ₁ ,..., Xn and the Y electrode lines Y ₁ ,..., Yn. A magnesium monoxide (MgO) layer 12 for protecting the panel 1 from a strong electric field is formed by applying the entire surface to the back surface of the upper dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

The driving method basically applied to the plasma display panel is a method in which reset, address, and sustain discharge steps are sequentially performed in a unit subfield. In the reset step, the remaining wall charges in the previous subfield are erased and driven so that the space charges are generated evenly. In the addressing step, the wall charges are formed in the selected pixels. In the sustain discharge step, light is driven to generate light in the pixels in which wall charges are formed in the addressing discharge step. That is, when alternatingly applying a pulse of a relatively high voltage to all the X electrode lines (X ₁ , ..., Xn) and all the Y electrode lines (Y ₁ , ..., Yn), wall charges are formed. It causes surface discharge in the pixels. At this time, a plasma is formed in the gas layer, and the phosphor 16 is excited by the ultraviolet radiation to generate light.

4 illustrates a unit frame for displaying gray scales on the plasma display panel of FIG. 1 according to a general sequential driving method. Referring to FIG. 4, a unit frame is divided into six subfields SF1, SF6 to realize time division gray scale display. In addition, each subfield SF1, ..., SF6 is divided into address periods A1, ..., A6 and sustain discharge periods S1, ..., S6.

Each of the address periods (A1, ..., A6) in, the address electrode lines _{(A 1, A 2, ...} , Am -1, Am) is a display data signal in the same time as soon each Y electrode lines (Y ₁ , ..., Y ₄₈₀ ) are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding pixel, and wall charges are not formed in the other pixel.

In each sustain discharge period S1, ..., S6, a common pulse is applied to all the Y electrode lines Y ₁ , ..., Y ₄₈₀ and the X electrode lines X ₁ , ..., Xn. Alternatingly applied, it causes display discharge in pixels in which wall charges are formed in corresponding address periods A1, ..., A6. Therefore, the luminance of the plasma display panel is proportional to the length of the sustain discharge cycles S1, ..., S6 occupied in the unit frame. In the case of Fig. 4, the lengths of the sustain discharge cycles S1, ..., S6 occupy a unit frame are 63T (T is the unit time). Therefore, it can be displayed in 64 gray levels including the case where it is not displayed once in the unit frame.

FIG. 5 illustrates driving signals applied to the plasma display panel of FIG. 1 in the unit subfield SF1 of the unit frame of FIG. 4. Reference numerals in FIG. 5 Denotes a drive signal applied to each of the address electrode lines A ₁ , A ₂ , ..., Am- ₁ , Am, Denotes a drive signal applied to the X electrode lines X ₁ , ..., Xn, and , ..., Indicates a drive signal applied to each of the Y electrode lines Y ₁ , ..., Y ₄₈₀ . Referring to FIG. 5, an address period A1 in the unit subfield SF1 is divided into reset periods A11, A12, and A13 and a main address period A14.

In the sustain discharge period S1, the positive voltages are applied to all the Y electrode lines Y ₁ , ..., Y ₄₈₀ and the X electrode lines X ₁ , ..., Xn. Higher voltage The common pulses of are alternately applied, causing display discharge in the pixels in which wall charges are formed in the corresponding address period A1. In the sustain discharge period S1, when the final pulse is applied to the X electrode lines X ₁ , ..., Xn, electrons are formed around the X electrode of the selected and displayed pixels, and positive charges are formed around the Y electrode. do. Accordingly, in the first reset period A11, the positive voltage is applied to the X electrode lines X ₁ ,..., Xn. Lower voltage Is applied, a discharge is performed to first erase the wall charges. Further, in the second reset period A12, voltages are applied to all of the Y electrode lines Y ₁ ,..., Y ₄₈₀ . A narrow pulse of is applied to perform a discharge that secondly erases the remaining wall charges. In the third reset period A13, voltages are applied to the X electrode lines X ₁ ,..., Xn. Is applied again, and discharge which finally erases the wall charges is performed. Accordingly, all the wall charges can be erased and the space charges can be uniformly distributed in the discharge space.

In the main address period A14, a display data signal is applied to the address electrode lines A ₁ , A ₂ ,..., Am- ₁ , Am, and at the same time, each Y electrode line Y ₁ ,..., Y ₄₈₀ are sequentially applied. The display data signal applied to each of the address electrode lines A ₁ , A ₂ , ..., Am- ₁ , Am is 0 [V], which is the positive voltage Va when the pixel is selected, and the ground voltage otherwise. Is applied. Each Y electrode line (Y ₁ , ..., Y ₄₈₀ ) has a bias voltage at a time that is not scanned. Is applied and 0 [V] is applied at the time of scanning. Accordingly, when the display data signal of voltage Va is applied while the scan pulse of 0 [V] is applied, wall charges are formed by the address discharge in the corresponding pixel, and wall charges are not formed in the other pixel. Where the voltage on the X electrode lines (X ₁ , ..., Xn) Lower than Higher voltage Is applied, a more accurate and efficient address discharge can be performed.

According to the conventional interlaced driving method of the plasma display panel, the scan pulse is applied only to the corresponding odd-numbered Y electrode lines (Y ₁ , Y ₃ , ..., Y ₄₇₉ ) in the odd-numbered subfield. In the even subfield, a scan pulse is applied only to corresponding even Y electrode lines (Y ₂ , Y ₄ ,..., Y ₄₈₀ ).

6 illustrates an addressing operation according to a conventional interlace driving method. FIG. 7 shows a screen of each subfield corresponding to the addressing operation of FIG. 6. In FIG. 7, reference numeral 71 denotes a screen of an odd subfield, and 72 denotes a screen of an even subfield. 6 and 7, in the odd subfield, the display data signal is applied to the address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am in FIG. Scan pulses corresponding to electrode lines Y ₁ , Y ₃ , ..., Y ₄₇₉ are sequentially applied. Similarly, in the even-numbered subfield, the display data signal is applied to the address electrode lines A ₁ , A ₂ ,..., Am- ₁ , Am and at the same time, each even-numbered Y electrode line Y ₂ , Y _4. , ..., Y ₄₈₀ ) are sequentially applied.

According to the conventional driving method as described above, there are the following problems.

1. Between the Y electrode lines being scanned, the voltage of the scan pulse (0 [V] in FIG. 5) and the bias voltage (in the case of FIG. 5) Since there are Y electrode lines to which the) is applied, there is a high possibility that flicker, which is a kind of noise display, is generated due to the interference discharge.

2. In the odd subfield, display discharge (corresponding to the period S1 in FIG. 5) occurs only in pixels selected in relation to the odd-numbered Y electrode lines Y ₁ , Y ₃ ,..., Y ₄₇₉ . Similarly, in the even-numbered subfield, display discharge occurs only in pixels selected with respect to the even-numbered Y electrode lines Y ₂ , Y ₄ ,..., Y ₄₈₀ . As a result, the display discharge efficiency is lowered and the display brightness is lowered.

An object of the present invention is to provide a driving method capable of suppressing the generation of flicker and increasing the display brightness in the driving method of a plasma display panel.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is an electrode line pattern diagram of the plasma display panel of FIG. 1.

3 is a cross-sectional view illustrating an example of one pixel of the panel of FIG. 1.

4 is a block diagram illustrating a unit frame for displaying gray scales on the plasma display panel of FIG. 1 according to a general sequential driving method.

FIG. 5 is a timing diagram illustrating driving signals applied to the plasma display panel of FIG. 1 in a unit subfield of the unit frame of FIG. 4.

6 is a schematic diagram illustrating an addressing operation according to a conventional interlaced driving method.

FIG. 7 is a schematic diagram illustrating a screen of each subfield corresponding to the addressing operation of FIG. 6.

8 is a block diagram illustrating a plasma display device to which a driving method according to the present invention is applied.

9 is a timing diagram illustrating driving signals applied to the plasma display panel of the apparatus of FIG. 8 in an address period of an odd-numbered subfield according to an embodiment of the present invention.

FIG. 10 is a timing diagram illustrating driving signals applied to the plasma display panel of the apparatus of FIG. 8 in an address period of an even-numbered subfield alternated with the odd-numbered subfield of FIG. 9.

11 is a schematic diagram illustrating an addressing operation according to a driving method of an embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

1, 88 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 magnesium monoxide layer,

13 back glass substrate, 14 discharge space,

16 phosphors, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line,

Y ₁ , ..., Yn ... Y electrode line,

A ₁ , A ₂ , ..., Am _-1 , Am ... address electrode line,

Xna, Yna ... ITO electrode line,

Xnb, Ynb ... bus electrode line,

SF1, ..., SF6 ... subfield, A1, ..., A6 ... address cycle,

S1, ..., S6 ... sustain discharge cycle, A11 ... first reset cycle,

A12 ... second reset cycle, A13 ... third reset cycle,

A14 ... Main address period, 71 ... Odd subfield display,

72 ... even-numbered subfield screen, 81 ... signal format determination unit,

82 ... interlaced video signal processor, 83 ... progressive video signal processor,

84 control unit, 85 address drive unit,

86 ... Y electrode drive, 87 ... X electrode drive.

The driving method of the present invention for achieving the above object, the interlaced image signal of the resolution corresponding to the number of Y electrode lines to which the scan driving signal is applied in the plasma display panel, or the resolution corresponding to half of the number of the Y electrode lines The plasma display panel is driven by sequentially processing image signals, and setting the plasma display panel in units of set subfields. The method includes applying a display data signal and forming wall charges. In the applying of the display data signal, a display data signal corresponding to the interlaced image signal or the sequential image signal is applied to address electrode lines arranged in a direction orthogonal to the Y electrode lines. In the forming of the wall charges, a scan pulse corresponding to the Y electrode lines is applied simultaneously with the application of the display data signal, and the scan pulses are sequentially applied to two adjacent Y electrode lines. Wall charges are formed in the pixels.

According to the driving method of the present invention, since the scan pulse is sequentially applied in units of two adjacent Y electrode lines, there is a high probability that the flicker generated due to the potential difference between adjacent lines is suppressed. Further, since the Y electrode line to be scanned and the adjacent Y electrode line to be scanned are simultaneously scanned in all the subfields, both the selected pixels and the adjacent pixels in relation to the Y electrode line to be scanned perform display discharge. As a result, the display discharge efficiency may be increased, thereby increasing display brightness.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

8 shows a plasma display device to which a driving method according to the present invention is applied. Referring to FIG. 8, the apparatus for driving the plasma display panel 88 by applying the driving method according to the present invention includes a signal format determination unit 81, an interlaced image signal processor 82, a sequential image signal processor 83, The control unit 84, the address driver 85, the Y electrode driver 86 and the X electrode driver 87 are included.

As an image signal input to the signal format determination unit 81, interlaced image signals or Y electrode lines having a resolution corresponding to the number n of Y electrode lines (Y ₁ ,..., Y n in FIG. 1) are provided. A progressive video signal having a resolution corresponding to half (n / 2) of the number of (Y ₁ , ..., Yn) can be input. The signal format determination unit 81 determines whether the input image signal is an interlaced or sequential format and inputs it to the corresponding image signal processing units 82 and 83. The interlaced image signal processor 82 processes the interlaced image signal having a resolution corresponding to the number n of the Y electrode lines Y ₁ ,..., And Y n and inputs the interlaced image signal to the controller 84. The sequential image signal processor 82 processes and inputs a sequential image signal having a resolution corresponding to half (n / 2) of the number of Y electrode lines Y ₁ ,..., And Y n and inputs it to the controller 84. The controller 84 generates timing control signals and driving control signals corresponding to the input image signal and inputs the driving control signals to the driving units 85, 86, and 87. Accordingly, the address driver 85 applies a drive signal to the address electrode lines (A ₁ , A ₂ ,..., Am ₋₁ , Am in FIG. 1), and the Y electrode driver 86 receives the Y electrode line. The driving signals are applied to the fields Y ₁ ,..., And Yn, and the X electrode driver 87 applies a driving signal to the X electrode lines X ₁ ,..., Xn.

9 illustrates driving signals applied to the plasma display panel of the apparatus of FIG. 8 in an address period of an odd-numbered subfield according to an embodiment of the present invention. FIG. 10 illustrates driving signals applied to the plasma display panel of the apparatus of FIG. 8 in an address period of an even-numbered subfield alternated with the odd-numbered subfield of FIG. 9. 11 illustrates an addressing operation according to a driving method of an embodiment of the present invention. Reference numerals in FIGS. 9 and 10 , ..., _Denotes a drive signal applied to each Y electrode line (Y ₁ , ..., Y ₄₈₀ ), and Indicates a driving signal applied to each of the address electrode lines A ₁ , A ₂ ,..., Am- ₁ , Am. 9, 10 and 11 are correlated with the main address period (A14 in FIG. 5), and immediately before this, the space charges are uniformly distributed to all pixels while removing wall charges remaining in the pixels displayed in the previous subfield. There are reset periods (A11, A12 and A13 in FIG. 5) to distribute. In addition, immediately after the main address periods of FIGS. 9, 10, and 11 are terminated, all Y electrode lines Y ₁ ,..., Y ₄₈₀ are fixed to the X electrode lines X ₁ ,..., X ₄₈₀ . Polarity voltage (in case of Figure 5 There is a sustain discharge period S1 that alternately applies a common pulse to cause display discharge in pixels in which wall charges are formed in a corresponding address period (A1 in FIG. 5).

9, 10, and 11, voltages at respective address electrode lines A ₁ , A ₂ ,..., Am ₋₁ , Am Or while the display data signal of the ground voltage (0 [V]) is applied, the corresponding (i) (i is odd) Y electrode line and (i + 1) th Y electrode line adjacent thereto in the odd subfield. Scan pulses of 0 [V] are applied simultaneously. In the even subfield, scan pulses are simultaneously applied to the (i + 1) th Y electrode line and the (i + 2) th Y electrode line. At this time, the bias voltage is applied to the remaining Y electrode lines. Is applied.

Since the scan pulses are sequentially applied in units of two adjacent Y electrode lines as described above, there is a high possibility that flicker generated due to a potential difference between adjacent lines is suppressed. Further, since the Y electrode line to be scanned and the adjacent Y electrode line to be scanned are simultaneously scanned in all the subfields, both the selected pixels and the adjacent pixels in relation to the Y electrode line to be scanned perform display discharge. As a result, the display discharge efficiency may be increased, thereby increasing display brightness.

As described above, according to the driving method of the plasma display panel according to the present invention, since the scanning pulse is sequentially applied in units of two adjacent Y electrode lines, flicker generated due to a potential difference between adjacent lines is suppressed. Is likely to be. Further, since the Y electrode line to be scanned and the adjacent Y electrode line to be scanned are simultaneously scanned in all the subfields, both the selected pixels and the adjacent pixels in relation to the Y electrode line to be scanned perform display discharge. As a result, the display discharge efficiency may be increased, thereby increasing display brightness.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (4)

An interlaced image signal having a resolution corresponding to the number of Y electrode lines to which the scan driving signal is applied or a sequential image signal having a resolution corresponding to half of the number of the Y electrode lines are processed in the plasma display panel, and set in a subfield unit. In the method for driving the plasma display panel, Applying a display data signal according to the interlaced image signal or the sequential image signal to address electrode lines arranged in a direction orthogonal to the Y electrode lines; And A scan pulse corresponding to the Y electrode lines is applied simultaneously with the application of the display data signal, and the wall pulses are formed in the corresponding pixels by sequentially applying the scan pulse in units of two adjacent Y electrode lines. Driving method including steps. The method of claim 1, In the odd subfield, the scan pulse is simultaneously applied to the (i) th (i is odd) Y electrode line and the (i + 1) th Y electrode line. And a scan pulse is simultaneously applied to an (i + 1) th Y electrode line and an (i + 2) th Y electrode line in an even subfield. The method of claim 1, wherein before performing the applying of the display data signal and causing the wall charges to be formed, the space charges are uniformly applied to all the pixels while removing the wall charges remaining in the pixels displayed in the previous subfield. A driving method in which a reset step of automatically distributing is performed. The method of claim 1, wherein after performing the applying of the display data signal and causing the wall charges to be formed, a common pulse is applied to the address electrode lines and the Y electrode lines arranged parallel to the Y electrode lines. And a sustain discharge step of causing display discharge to occur in the pixels on which the wall charges are formed by alternately applying the same.