KR20000007247A - Board interconnection structure of computer - Google Patents

Abstract

PURPOSE: A board interconnection structure of computer is provided to dissolve operational error in computer system using interconnection of signal. CONSTITUTION: The board interconnection structure comprises a master slot, slave slots, an initialization device select(IDSEL) pin, and a selection relay section. In the board interconnection structure, a main circuit board and sub circuit board are set up in the master slot. Slave slots are connected by the master slot and a plurality of signal line. The IDSEL pin set up in each slave slot. The selection relay section selects specific signal line in address signal lines and connects to the IDSEL pin, wherein specific signal line is named AD16 or AD31.

Description

Board connection structure of computer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a board connection structure of a computer, and more particularly, to a board connection structure of a computer relaying an interconnection of a main circuit board and an auxiliary circuit board.

Referring to FIG. 1, a conventional board connection structure 10 is provided with a plurality of slots 12 and 13 spaced apart from each other.

The master slot 12 is connected to a main circuit board 16 on which a central processing unit (CPU) is mounted. The slave slots 13 connected to the master slot 12 and the signal lines, respectively, are mounted with an auxiliary circuit board 17, that is, peripheral devices.

In this board connection method, the PCI (Peripheral Compenent Interconnect) bus standard, which defines the signal line connection between the CPU and peripherals, processes high-speed data such as CPUs and peripherals such as graphics, video processor, SCSI, and LAN. It is a signal line connection method to improve the data transfer speed compared to the existing ISA bus and VESA bus. This PCI bus specification has a bus structure that manufacturers can adopt for other CPUs in common. In addition, it supports a system that can automatically recognize the devices attached to the computer to improve the user's convenience. The automatic recognition support system is simply called PNP by plug and play, and when the power is turned on and played, there is no need for a separate operation method setting process. To this end, a device supporting the PNP function in the PCI bus structure has a configuration resister that indicates its configuration or operation status. In addition, IDSEL (Initialization Device Select) pin is designated for use as chip select when reading the configuration register of the device to be mounted or writing data to the register among the pins allocated to the PCI slot for mounting the peripheral device. have.

Conventionally, as shown in FIG. 2, the IDSEL pin 13a designated for each of the slave slots 13 and each of the address signal lines 14 selected from the address signals lines drawn out from the main slot 12 are different from each other. Each is connected via a limiting resistor element 15. However, in order to improve the focusing efficiency on the main circuit board mounted on the main slot 12, a part of the peripheral device for function expansion is integrated together, and a signal line connected to the IDSEL pin (not shown) of the peripheral device is connected to the slave slot 13. In the case where the signal line 14 overlaps with the signal line 14 used in the system, a failure occurs in recognizing and recognizing each peripheral device.

In general, when assembling a computer, if the same manufacturer's product is selected for each circuit board, the signal lines of different numbers are used so that the recognition failure does not occur, but the main circuit board is upgraded to a third party product for enhancing the function. In the case of adopting the new circuit board, the peripheral device is recognized when the newly adopted main circuit board designates a signal line whose address overlaps with the signal line used in the slave slot 13 when the signal line set for the peripheral device integrated together therein is designated. A failure occurs. These cognitive impairments interfere with the normal operation of the computer.

The present invention was devised to improve the above problems, and the signal line of the address line which does not overlap with the signal line used for IDSEL in the main circuit board to be mounted in the main slot can be connected to the IDSEL pin of the slave slot. The purpose is to provide a board connection structure of a computer.

1 is a perspective view showing a conventional board connection structure,

FIG. 2 is a wiring diagram illustrating a signal line connection relationship for a specific pin between a master slot and a slave slot in the board connection structure of FIG. 1;

3 is a plan view schematically showing a board connection structure according to the present invention.

<Description of Symbols for Major Parts of Drawings>

10, 20: board connection structure 12, 22: master slot

13, 23: slave slot 13a, 23a: IDSEL pin

14, 24: address signal lines 15, 27: resistive elements

16: main circuit board 17: auxiliary circuit board

21: substrate 25: input terminal

26: output terminal 30: signal line select relay

In order to achieve the above object, according to the present invention, the main circuit board equipped with the central processing unit is mounted, and the auxiliary circuit board for the expansion function is mounted to be connected by the master slot and a plurality of signal lines In a board connection structure of a computer having a plurality of slave slots, any one of an IDSEL designation pin set in each of the slave slots and a signal line whose unique number is AD 16 to AD 31 among the address signal lines drawn out from the master slot; And a signal line selection repeater configured to select and connect a signal line of the signal line.

Hereinafter, the board connection structure of the computer according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically showing a board connection structure according to the present invention.

Referring to the drawings, the board connection structure includes a board 21, a master slot 22 for mounting a main circuit board mounted on the board 21, slave slots 23 for mounting an auxiliary circuit board, and a signal line selection connection. The signal line selection relay unit 30 is provided. Each of the slots 22 and 23 has a structure capable of accepting and supporting a mounting target circuit board, that is, a main circuit board (see FIG. 1) and an auxiliary circuit board (see FIG. 1), and the main circuit board and the auxiliary circuit board. The wirings are connected by a signal line of a predetermined pattern on the substrate 21 so that the electrical connections are made together. The wiring method of the signal line between the master slot 22 and the slave slots 23 is made according to the PCI protocol.

According to the PCI protocol, it is recommended that the IDSEL pin 23a of the pins allocated to each slot 23 use any one of the AD 16 to AD 31 signal lines starting from AD0 drawn out from the master slot 22. .

In consideration of this, the signal line selection relay section 30 is connected from the master slot 21 to each of the IDSEL pins 23a of the respective slave slots 23 in the address signal lines, all of the AD 16 to AD 31 signal lines or the substrate 21. A portion selected from the number of the slave slots 23 mounted on the s) is appropriately selected and connected to the IDSEL pin 23a of each slot 23. The signal line select relay 30 has input terminals 25 connected to the address signal lines 24 and output terminals 26 connected to the IDSEL designating pins 23a of the slave slots 23, respectively. Selective connection of terminal 25 and output terminal 26 can be made internally or by a user. As a method for selective connection, the signal line selection relay unit 30 selects a signal to be connected to the signal line of the IDSEL pin 23a of each slot 23 among the AD 16 to AD 31 signal lines according to the instruction of the central processing unit. The internal circuit may be configured, or alternatively, the signal line to be selected by hand and the IDSEL pin 23a may be connected by wire. When the signal line to be manually selected and the IDSEL pin 23a can be connected by wires, the input terminal 25 and the output terminal 26 are formed to be exposed to the outside of the substrate 21.

The resistor elements 27 provided between the IDSEL pin 23a and the output terminal 26 are for current limiting.

First, according to the instruction of the central processing unit, the operation when the internal circuit of the signal line selection connecting section 30 is configured so that the connection target signal line of the IDSEL pin 23a of each slot 23 can be selected among the AD 16 to AD 31 signal lines. In the following description, when the ROM BIOS mounted on the main circuit board operates according to power-on, the auxiliary circuit board integrated in the main circuit board, for example, reads the address of the address signal line which VGA or LAN is using for IDSEL, and The central processing unit outputs information to the signal line selection relay section 30 so that the address signal line of the address other than the address signal line of the previous address is connected to the IDSEL pin 23a of the slave slot 23. The signal line selection relay section 30 connects the IDSEL pin 23a and the designated address signal line in accordance with the inputted information. At this time, the addresses of the address signal lines 24 connected to the IDSEL pins 23a of the slave slots 23 are connected differently.

On the other hand, in the case where the signal line 24 to be manually selected by the signal line selection relay unit 30 and the IDSEL pin 23a can be connected by wires, the signal line selection relay unit 30 is the address signal lines 24. And only the input terminals 25 connected to each other and the output terminals 26 connected to the IDSEL pins 23a of the slave slots 23, respectively. Then, the signal line connection in the signal line select relay 30 is connected between the input terminal 25 of the address line of the address to be designated and the output terminal 25 connected to the IDSEL designating pin 23a of the corresponding slot 23. This can be done with wires.

Although not shown, when a peripheral device such as VGA or LAN is integrated on the main circuit board, a signal line selection relay may be provided on the main circuit board so that the selection of the connection address of the address signal line for the IDSEL of the peripheral device can be changed. . At this time, the IDSEL signal line of the signal line selection relay provided on the main circuit board may be connected so as not to overlap with the address signal lines of the addresses used in the slave slots.

As described so far, according to the board connection structure of the computer according to the present invention, the classification connection of the signal line can be easily changed so that the central processing unit can recognize the mutually connected auxiliary devices, thereby eliminating the operation error. have.

Claims (3)

Board connection structure of a computer having a master slot on which a main circuit board equipped with a central processing unit is mounted, and a plurality of slave slots connected by the master slot and a plurality of signal lines for mounting an auxiliary circuit board for function expansion. To A signal line selection repeater configured to select and connect any one of an IDSEL designation pin set to each of the slave slots and a signal line whose unique number is AD 16 to AD 31 among the address signal lines drawn out from the master slot; Board connection structure of a computer, characterized in that it further comprises. The board connection structure of a computer according to claim 1, wherein said IDSEL designating pin is capable of selectively connecting with said address signal line through a current limiting resistor. The signal line selection relay of claim 1, wherein the signal line selection relay has an input terminal connected to each of the address signal lines, an output terminal spaced a predetermined distance from the input terminals, and an output terminal connected to an IDSEL pin of each of the slave slots. And a wire connection with any one input terminal selected from each of said output terminals.