KR20000004736A - Method for forming a field oxide of semiconductor devices - Google Patents
Method for forming a field oxide of semiconductor devices Download PDFInfo
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- KR20000004736A KR20000004736A KR1019980026232A KR19980026232A KR20000004736A KR 20000004736 A KR20000004736 A KR 20000004736A KR 1019980026232 A KR1019980026232 A KR 1019980026232A KR 19980026232 A KR19980026232 A KR 19980026232A KR 20000004736 A KR20000004736 A KR 20000004736A
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- oxide film
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000002955 isolation Methods 0.000 claims abstract description 34
- 150000004767 nitrides Chemical class 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 13
- 150000002500 ions Chemical class 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract 5
- 239000000126 substance Substances 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- -1 Boron ion Chemical class 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- 240000002836 Ipomoea tricolor Species 0.000 description 1
- 210000003323 beak Anatomy 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체장치의 제조공정에 관한 것으로, 특히, 폭이 좁은 소자분리영역을 형성하기 위하여 반도체기판까지 노출되는 트렌치를 형성하고, 이 트렌치에 화학기계적연마공정으로 산화막을 형성시킨 후에 나이트라이드막을 식각으로 노출시키고 산화막을 성장시켜 소자분리영역의 필드산화막을 형성하므로 버어즈빅을 없애주어 소자의 특성을 향상시키도록 하는 반도체장치의 필드산화막형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device. In particular, a trench exposed to a semiconductor substrate is formed to form a narrow device isolation region. The present invention relates to a method of forming a field oxide film of a semiconductor device in which an oxide film is grown by etching and an oxide film is grown to form a field oxide film in a device isolation region.
일반적으로, 반도체기판 상에 트랜지스터와 커패시터등을 형성하기 위하여 반도체기판에는 전기적으로 통전이 가능한 활성영역(Active Region)과 전기적으로 통전되는 것을 방지하고 소자를 서로 분리하도록 하는 소자분리영역(Isolation region)을 형성하게 되는 것으로서, 상기 소자분리영역은 산화막을 성장시켜 비행접시형상의 필드산화막(Field Oxide)을 형성하므로 활성영역간에 전기적으로 분리된 영역을 형성하게 되는 것이다.In general, in order to form transistors and capacitors on a semiconductor substrate, an isolation region is formed in the semiconductor substrate to prevent electrical conduction with an electrically energized active region and to separate devices from each other. In this case, the device isolation region grows an oxide film to form a field oxide film in the shape of a flying saucer, thereby forming an electrically separated region between the active regions.
이와 같이, 소자를 분리시키기 위하여 산화막을 성장시켜 형성되는 필드산화막을 형성시키기 위한 공정에는 반도체기판에 산화막과 나이트라이드막을 마스킹공정으로 나이트라이드막을 식각하고 그 식각된 콘택부위에 산화막을 성장하여 필드산화막을 형성시키는 LOCOS공정(Local Oxidation of silicon)이 있으며, 그 외에 상기 LOCOS공정의 산화막과 나이트라이드막 사이에 버퍼역할을 하는 폴리실리콘막을 개재하여 완충역할을 하여 필드산화막을 성장시키는 PBL(Poly Buffered LOCOS)공정등이 사용되고 있다.As such, in the process for forming a field oxide film formed by growing an oxide film to separate the device, the nitride film is etched by masking the oxide film and the nitride film on a semiconductor substrate, and the oxide film is grown on the etched contact portion. There is a LOCOS process (Local Oxidation of silicon) to form a, PBL (Poly Buffered LOCOS) to grow a field oxide film through a polysilicon film that acts as a buffer between the oxide film and the nitride film of the LOCOS process Processes are used.
도 1 내지 도 4는 종래의 일반적인 PBL공정으로 필드산화막을 형성하는 공정을 순차적으로 보인 도면으로서, 도 1은 반도체기판(1)에 산화막(3), 폴리실리콘막(4) 및 나이트라이드막(5)을 순차적으로 적층한 상태를 보인 도면이다.1 to 4 are diagrams sequentially illustrating a process of forming a field oxide film by a conventional general PBL process, and FIG. 1 illustrates an oxide film 3, a polysilicon film 4, and a nitride film on a semiconductor substrate 1. 5 is a diagram showing a state in which the stacking sequentially.
그리고, 도 2는 ISO마스크를 적층하여 필드산화막이 형성될 소자분리영역에 식각을 통하여 콘택부위(6)를 형성하고 활성영역에 나이트라이드막을 남겨둔 상태를 도시하고 있다.FIG. 2 illustrates a state in which a contact region 6 is formed by etching an element isolation region where a field oxide film is to be formed by stacking an ISO mask and leaving a nitride layer in an active region.
도 3은 감광막(8)을 이용하여 NMOS영역의 소자분리영역에 반도체기판과 동일한 도전형의 불순물로서 Boron이온은 임플란트(Implant)하여 항복전압을 증가시키므로 절연을 향상시키기 위하여 이온주입(7)을 하는 상태를 보이고 있다.FIG. 3 shows that the boron ion is implanted into the device isolation region of the NMOS region using the photoresist film 8 as the impurity of the same conductivity type as the semiconductor substrate to increase the breakdown voltage. It is showing the state.
그리고, 도 4는 도3의 감광막(8)을 제거시킨 후에 콘택부위(6)를 통하여 산화막(3)을 성장시켜 필드산화막(9)을 형성시키는 상태를 도시하고 있다.FIG. 4 shows a state in which the field oxide film 9 is formed by growing the oxide film 3 through the contact portion 6 after removing the photosensitive film 8 of FIG.
그런데, 상기 한바와 같이, 종래에는 필드산화막(9)을 형성할 때 주변회로 지역에서는 정상적으로 필드산화막이 형성되므로 소자 절연특성에 이상이 없으나 소자분리영역의 간격이 좁은 셀(Cell)영역에서는 좁은 부분에서 발생하는 윈도우 효과에 의하여 정상적으로 산화막이 성장하지 못하고 필드산화막의 양측모서리가 얇아지는 새주둥아리와 같은 형상의 버어즈빅(Bird,s Beak)이 형성되어 활성영역이 감소하므로 소자분리특성이 나빠져서 소자의 전기적인 특성이 저하되는 문제를 지니고 있었다.However, as described above, since the field oxide film is normally formed in the peripheral circuit area when the field oxide film 9 is formed, there is no problem in device insulation characteristics, but a narrow portion in the cell region where the device isolation region is narrow. Due to the window effect that occurs at, the oxide film does not grow normally and the bird's beak has a shape like a bird's nose where both edges of the field oxide film become thinner, thereby reducing the active area. The electrical characteristics of the had a problem of deterioration.
본 발명은 이러한 점을 감안하여 안출한 것으로서, 폭이 좁은 소자분리영역을 형성하기 위하여 반도체기판까지 식각되는 트렌치를 형성하고, 이 트렌치에 화학기계적연마공정으로 산화막을 형성시킨 후에 나이트라이드막을 식각으로 노출시키고 산화막을 성장시켜 소자분리영역의 필드산화막을 형성하므로 버어즈빅을 없애주어 소자의 특성을 향상시키도록 하는 것이 목적이다.The present invention has been devised in view of the above, and in order to form a narrow device isolation region, a trench is etched to a semiconductor substrate, and an oxide film is formed in the trench by chemical mechanical polishing, and then the nitride film is etched. The purpose of the present invention is to improve the characteristics of the device by eliminating burr's beak by exposing and growing an oxide film to form a field oxide film in the device isolation region.
도 1 내지 도 4는 종래의 일반적인 필드산화막을 형성하는 공정을 순차적긍로 보인 도면이고,1 to 4 are sequential views showing a process of forming a conventional general field oxide film,
도 5 내지 도 10은 본 발명에 따른 필드산화막을 형성하는 방법을 순차적으로 보인 도면이다.5 to 10 are views sequentially showing a method of forming a field oxide film according to the present invention.
-도면의 주요부분에 대한 부호의 설명-Explanation of symbols on the main parts of the drawing
10 : 반도체기판 20 : 산화막10 semiconductor substrate 20 oxide film
30 : 나이트라이드막 40 : 감광막30: nitride film 40: photosensitive film
45 : 트렌치 50 : 이온주입부분45 trench 50 ion implantation part
60 : 산화막 70 : 감광막60: oxide film 70: photosensitive film
75 이온주입부분 80 : 필드산화막75 ion implantation part 80: field oxide film
A : 버어즈빅이방지된부분A: Burrs big prevention
이러한 목적은 반도체기판에 산화막 및 나이트라이드막을 순차적으로 적층하는 단계와; 상기 단계 후에 소자분리영역의 폭이 넓은 영역에 감광막을 적층하고 소자분리영역의 폭이 좁은 영역에는 감광막을 적층하지 않도록 하는 단계와; 상기 단계 후에 소자분리영역의 폭이 좁은 영역에 나이트라이드막 및 산화막을 식각하여 제거하고 노출되는 반도체기판을 식각하여 트렌치를 형성하는 단계와; 상기 단계 후에 상기 트렌치내에 이온을 주입하고 소자분리영역의 폭이 넓은 영역에 있는 감광막을 제거한 후에 트렌치 및 그 이외의 전면에 샨화막을 적층하고 트렌치내의 산화막을 제외한 나머지 부분의 산화막을 제거하는 단계와; 상기 단계 후에 소자분리영역의 폭이 좁은 영역의 산화막 상에 감광막을 적층하고, 소자분리영역의 폭이 넓은 영역에 있는 나이트라이드막을 식각하여 콘택부위를 형성하는 단계와; 상기 단계후에 콘택부위에 이온을 주입한 후 콘택부위를 통하여 산화막을 성장시켜 필드산화막을 형성하는 단계로 구성된 반도체장치의 필드산화막형성방법을 제공함으로써 달성된다.The object is to sequentially deposit an oxide film and a nitride film on a semiconductor substrate; Stacking the photoresist film in a wide area of the device isolation region after the step and not stacking the photoresist film in the narrow area of the device isolation region; Etching the nitride film and the oxide film in a narrow region of the device isolation region after the step and etching the exposed semiconductor substrate to form a trench; After the step of implanting ions into the trench, removing the photoresist film in the wide region of the device isolation region, laminating a sulphation film on the trench and other front surfaces, and removing the oxide film of the remaining portions except the oxide film in the trench; Stacking a photoresist on an oxide film in a narrow region of the device isolation region after the step, and etching a nitride film in a wide region of the device isolation region to form a contact region; It is achieved by providing a field oxide film forming method for a semiconductor device, comprising the step of implanting ions into a contact portion after the step and growing an oxide film through the contact portion to form a field oxide film.
이하, 첨부한 도면에 의거하여 본 발명에 따른 필드산화막 형성방법 대하여 상세히 설명하도록 한다.Hereinafter, a method of forming a field oxide film according to the present invention will be described in detail with reference to the accompanying drawings.
먼저, 도 5은 반도체기판(10)에 산화막(20) 및 나이트라이드막(30)을 순차적으로 적층하는 상태를 도시하고 있다.First, FIG. 5 illustrates a state in which the oxide film 20 and the nitride film 30 are sequentially stacked on the semiconductor substrate 10.
그리고, 도 6은 상기 단계 후에 소자분리영역의 폭이 넓은 영역에 감광막(40)을 적층하고 소자분리영역의 폭이 좁은 영역에는 감광막(40)을 적층하지 않도록 한 후에 소자분리영역의 폭이 좁은 영역에 나이트라이드막(30) 및 산화막(20)을 식각하여 제거하고 노출되는 반도체기판(10)을 식각하여 트렌치(45)를 형성하는 계속하여 상기 트렌치(45)내에 도전형불순물 역할을 하는 Boron이온을 주입하는 상태를 도시하고 있다.6 shows that after the above step, the photoresist film 40 is stacked in a wide region of the device isolation region, and the photoresist film 40 is not laminated in the narrow region of the device isolation region, and then the width of the device isolation region is narrow. The nitride film 30 and the oxide film 20 are etched and removed in the region, and the exposed semiconductor substrate 10 is etched to form the trench 45. The boron serving as a conductive impurity in the trench 45 is formed. The state which implants an ion is shown.
그리고, 도 7 및 도8은 소자분리영역의 폭이 넓은 영역에 있는 감광막(40)을 제거한 후에 트렌치(45) 및 그 이외의 전면에 화학기상증착(CVD; Chemical Vapor Deposition)에 의하여 산화막(60)을 적층하고 트렌치(45)내의 산화막(60)을 제외한 나머지 부분의 산화막(60)을 화학기계적연마로 제거하여 나이트라이드막(30)을 노출시키는 상태를 도시하고 있다.7 and 8 show that the oxide film 60 is removed by the chemical vapor deposition (CVD) on the trench 45 and other surfaces after removing the photosensitive film 40 in the wide region of the device isolation region. ), The oxide film 60 in the remaining portions except the oxide film 60 in the trench 45 is removed by chemical mechanical polishing to expose the nitride film 30.
도 9는 상기 단계 후에 트렌치(45)의 산화막(60) 상의 소자분리영역의 폭이 좁은 영역에 감광막(70)을 적층하고, 소자분리영역의 폭이 넓은 영역에 있는 나이트라이드막(30)을 식각하여 콘택부위(35)를 형성하고 콘택부위(35)에 이온을 주입하는 상태를 도시하고 있다.FIG. 9 shows that the photoresist film 70 is stacked in a narrow region of the device isolation region on the oxide film 60 of the trench 45 after the step, and the nitride film 30 in the wide region of the device isolation region is formed. The state of etching to form the contact portion 35 and implanting ions into the contact portion 35 is illustrated.
도 10은 상기 콘택부위(35)를 통하여 나이트라이드막(30)을 성장시켜 필드산화막(80)을 형성하는 상태를 도시하고 있고, 산화막(60)을 갖는 부위와 필드산화막(80)이 성장되는 부위가 서로 만나는 부분은 버어즈빅이 방지된부위(A)로 표시되어지며, 단차없이 정확하게 필드산화막(80)이 형성되어진다.FIG. 10 shows a state in which the nitride film 30 is grown through the contact portion 35 to form the field oxide film 80. The site having the oxide film 60 and the field oxide film 80 are grown. The portions where the portions meet each other are marked as the portions A where the burj's big is prevented, and the field oxide film 80 is accurately formed without a step.
따라서, 상기한 바와 같이 본 발명에 따른 반도체소자의 필드산화막형성방법을 이용하게 되면, 폭이 좁은 소자분리영역을 형성하기 위하여 반도체기판까지 식각되는 트렌치를 형성하고, 이 트렌치에 화학기계적연마공정으로 산화막을 형성시킨 후에 나이트라이드막을 식각으로 노출시키고 산화막을 성장시켜 소자분리영역의 필드산화막을 형성하므로 버어즈빅을 없애주어 소자분리영역의 면적을 작게하여 활성영역의 면적을 크게하므로 반도체소자의 전기적 특성을 향상시키도록 하는 매우 유용하고 효과적인 발명이다.Therefore, as described above, when the field oxide film forming method of the semiconductor device according to the present invention is used, a trench is etched to the semiconductor substrate to form a narrow device isolation region, and the trench is subjected to a chemical mechanical polishing process. After the oxide film is formed, the nitride film is exposed by etching and the oxide film is grown to form a field oxide film of the device isolation region. Thus, the burrs big is eliminated and the area of the device isolation region is reduced to increase the area of the active region. It is a very useful and effective invention for improving the properties.
Claims (4)
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| KR1019980026232A KR20000004736A (en) | 1998-06-30 | 1998-06-30 | Method for forming a field oxide of semiconductor devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6992742B2 (en) | 1999-03-09 | 2006-01-31 | Lg.Philips Lcd Co., Ltd. | Multi-domain liquid crystal display device having pixel electrodes with electric field inducing windows |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6992742B2 (en) | 1999-03-09 | 2006-01-31 | Lg.Philips Lcd Co., Ltd. | Multi-domain liquid crystal display device having pixel electrodes with electric field inducing windows |
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