KR20000004576A - Communication line duplexing device in serial data communication system and method thereof - Google Patents

Abstract

PURPOSE: A communication line duplexing device in a serial data communication system and method thereof detect a signal transition of the first and second communication lines, detect a data transmission error on the basis of the generation number of the signal transitions, and determine a failure of the communication line. CONSTITUTION: A communication line duplexing device includes a first transition detector for detecting a digital signal transition from the first communication line; a second transition detector for detecting a digital signal transition from the second communication line; an error detector which receives output signals of the first and second transition detectors and determines an error by comparing generation numbers of signal transitions between two communication lines; and a line switching part which receives an error detection signal from the error detector, determines a failure line, and performs a line switching between a normal line and the failure line. Thereby, the communication line duplexing device minimizes a data loss in receiving the data, and has a high reliability and a rapid response characteristic.

Description

Device and method for redundancy of communication line in serial data communication system

The present invention relates to a redundancy apparatus and method of a communication line in a serial data communication system, and more particularly, detects a signal transition of each of the first communication line and the second communication line (rising edge: rising edge and / or falling edge). : Falling Edge) The present invention relates to a communication line redundancy device and a communication line redundancy method for detecting a data transmission error from a frequency at which this signal transition occurs and determining whether a line is faulty.

As is known, in a serial data communication system in which two or more processors perform serial data communication through a common communication line, the influence of communication failures between processors on the entire system and the spread of the influences of the entire system rather than a local failure in any one processor The effect is even greater.

In particular, if an automatic control system is networked to a plurality of processors in a common communication network to perform distributed control, the communication failure may be a very fatal failure because it may lead to a service malfunction of the entire system.

Therefore, in such a communication system, communication lines are duplicated. In general, if two communication lines have the same data and transmit the same data simultaneously, if one communication line fails, another communication line is used to solve the communication failure. Overcoming and securing the stability of the system.

Fig. 1 is a block diagram showing the concept of a duplication apparatus for a communication line in a conventional serial data communication system, and shows an example of the case where software for controlling the determination of communication failure is performed in the main controller.

First, look at the configuration; Detects abnormality of each line from the line matching and transmitting / receiving unit 101 and 102 for performing line matching and data transmission / reception of each of the first line and the second line, and the data string inputted through the line matching and transmitting / receiving unit. An error detection unit 103 for inputting an error detection signal from the error detection unit 103, a main control unit 104 for determining a line in which an abnormality occurs, and performing line switching control to a normal communication line; And a buffer 105, 106 for selecting a normal line of either the first communication line or the second communication line under control to perform data reception.

The operation of the conventional communication line redundancy device configured as described above is performed as follows.

The first line matching and transmitting / receiving unit 101 is responsible for line matching between the first line and the processor and data transmission and reception, and the second line matching and transmitting / receiving unit 102 is responsible for line matching between the second line and the processor. It is in charge of data transmission and reception.

Line matching and transmission / reception include matching of physical layers between the communication line and the processor, filtering of noise, and the like.

The error detection unit 103 receives the input data received from the line matching and transmitting / receiving unit 101 or 102 and uses the conditions to be determined as regularity or other line failure in the protocol of communication of the data string. The presence / absence is detected and an error detection signal is input to the main control unit 104.

The main control unit 104 receives the error detection signal of the line from the error detection unit 103, determines whether there is a failure, and outputs a line selection control signal for selecting a normal line according to the determination result.

For example, if a failure of the first line occurs, a line selection control signal for disabling the first buffer 105 and enabling the second buffer 106 is output, and the failure of the second line occurs. If so, the first buffer 105 is enabled, and the second buffer 106 outputs a line selection control signal for disabling.

Data reception is performed by a buffer enabled by such a line selection control signal. At this time, data transmission is transmitted regardless of a failed line.

This is because the counterpart processor also performs the line redundancy of the concept as shown in FIG. 1, so that buffering control for the transmitted data is not necessary.

Meanwhile, in FIG. 1, when both lines are normal, only one buffer for one communication line is enabled and the other buffer is disabled according to a predetermined priority.

However, as shown in FIG. 1, when the main control unit 104 directly manages the determination of the presence or absence of a failure from the result of the error detection and the transfer of the line to the failure line and the normal line, the software burden on the main control unit's processor is large and the line failure occurs. The response to the occurrence (automatic transfer to the normal line) is delayed by the time required from the error detection recognition to the determination of the failure, which causes a problem that the duplication response speed is lowered.

FIG. 2 shows a configuration of a conventional line redundancy apparatus for performing error detection and line selection separately from the main control unit in hardware, and has a similar circuit configuration with the same concept as that of FIG.

First, look at the configuration; Detects abnormality of each line from the line matching and transmitting / receiving unit 201, 202 for performing line matching and data transmission / reception of each of the first line and the second line, and the data string inputted through the line matching and transmitting / receiving unit. An error detection unit 203 for receiving the error detection signal from the error detection unit 203, a line selection unit 204 for determining a line in which an abnormality occurs, and performing line switching control to a normal communication line; Buffers 205 and 206 which are each enabled or disabled by the selection unit 204 to perform respective data reception on the normal line, and a main control unit which transmits and receives data through the communication line ( 207).

The conventional communication line redundancy apparatus configured as described above can reduce the burden on the main control part and speed up the response speed by performing the determination of the fault line and the line transfer according to the error detection separately from the main control part 207, as compared to the above-described FIG. In this circuit, the operation of the circuit is as follows.

The first line matching and transmitting / receiving unit 201 is responsible for line matching between the first line and the processor, data transmission, reception, and noise cancellation, and the second line matching and transmitting / receiving unit 202 is connected to the second line and the processor. It is responsible for line matching, data transmission, reception and noise cancellation.

Line matching and transmission and reception include physical layer matching between communication lines and processors, data transmission and reception, filtering of noise, and the like.

The error detection unit 203 receives the input data received from the line matching and transmission / reception unit 201 and 202 and uses the condition to be determined as regularity or other line failure in the protocol of communication of the data string to determine the data error. The presence / absence is detected and an error detection signal is input to the line selection unit 204.

The line selection unit 204 receives the error detection signal of the line from the error detection unit 203 and outputs a line selection control signal for selecting a normal line.

For example, if a failure occurs in the first line, a line selection control signal for disabling the first buffer 205 and enabling the second buffer 206 is output, and the failure of the second line occurs. If so, the first buffer 205 is enabled, and the second buffer 206 outputs a line selection control signal for disabling.

Data reception is performed by a buffer enabled by such a line selection control signal. At this time, data transmission is transmitted regardless of a failed line.

This is because the counterpart processor also performs the line redundancy of the concept as shown in FIG. 2, so that the buffering control for the transmitted data is not necessary.

Meanwhile, in FIG. 2, when both lines are normal, only one buffer for one communication line is enabled and the other buffer is disabled according to a predetermined priority.

Then, the main controller 207 processes only the original operations such as data transmission / reception, decryption, processing, etc. in the state where the determination of the fault line and the control fault of the line transfer are excluded.

As described above, the concept of data communication system line redundancy is the same as that of Fig. 1 or Fig. 2, but the most important point in the practical implementation of the technology is precisely from how quickly and accurately the error of the communication line is detected and the error detection result. It depends on the determination of the presence of the obstacle line and the possibility of instantaneous line changeover.

In the redundant control technology of the communication line as shown in Figs. 1 and 2, the detection of an error is detected from a data bit stream of the received data to determine whether there is an error. Such real-time error detection is substantially very difficult. For this reason, most communication line duplication technologies are limited to systems using specific communication protocols and propose suitable duplexing techniques.

For example, there is a duplication technology of a communication system using a packet communication protocol called High-level Data Link Control (HDLC) or Synchronous Data Link Control (SDLC).

As shown in Fig. 3, the structure of the data packet of this communication method is an opening flag (Opening Flag: 7Eh) 301 which means the beginning of the data string and a closing flag (7Eh) 302 which means the end of the data string. ) Has a packet structure for transmitting and receiving via an information data field (303).

Here, the opening flag or the closing flag has a specific bit pattern promised. For example, the '7Eh' value is intervened one or more times.

This characteristic of HDLC or SDLC protocol is used to detect transmission error, which means that the data transmitted by the protocol cannot have more than 6 consecutive bits of logical value '1' (up to 5 '1' is continuous).

That is, in the case of a bit stream in which six or more bits having a data value of '1' are continuous, one '0' bit must be inserted after the five '1' bit streams and then again. Is to send a '1' bit string, and on the receiving side, if more than six bits with a data value of '1' continue, it intervenes between the five '1' bit strings and the '1' bit following it. Zero deletion of the '0' bit causes the original data to be received.

However, in the case of the opening flag or the closing flag, '7Eh' is '01111110', which distinguishes the characteristic that the logical value '1' is repeated in six consecutive bit patterns to distinguish it from the general data 303. Had.

Based on the characteristics of the HDLC / SDLC communication protocol described above (data is limited to five '1' bit sequences, and flags are allowed up to '1' bit sequences, '6'). If more than seven bits of the data bit string having logical value '1' are consecutively inputted, an error is determined.

For this purpose, the error detection (and determination) circuit uses a retriggerable monostable multivibrator to detect line faults and failures by monitoring whether more than seven '1' bits of the string continue (with consideration to the flag field). However, since the time constant value of the monostable multivibrator is difficult to set and the time constant value is changed by the operating environment of the system, in particular, the temperature, the accurate error detection and determination is practically impossible, which results in a low reliability.

In view of these shortcomings, the technique disclosed in Korean Laid-Open Patent Publication (Publication No. 96-3182) (using a data communication clock and a counter) monitors whether 8 or more logical values of '1' or '0' are continued. Technology).

However, the above-mentioned communication line duplication technology is limited to be applicable only to a specific communication protocol because it is a technology that uses the characteristics of the data transmission in a specific communication protocol promised, and a hardware (or software) burden related to monitoring data bit strings. This is large, because the main control unit does not know the failure of the communication line has a disadvantage that can not report the failure to the operator for the line maintenance.

The present invention provides an apparatus and method for redundancy of a communication line in a serial data communication system, which solves the problems of the conventional communication line redundancy described above.

In particular, the present invention detects signal transitions of each of the first communication line and the second communication line (rising edge: rising edge and / or falling edge: falling edge), and the signal transitions generated in each of the two communication lines. By providing communication line redundancy device and communication line redundancy method which detects data transmission error from frequency and judges line failure, general and common characteristics of digital data communication system (signal transition and data Based on thermal information transmission, error detection, fault determination and line transfer of communication lines can be performed.

In the present invention, in view of the fact that the phase of the data received through the two communication lines are always in phase when the phase of the normal line, the first flag means that the signal transition of the first communication line occurs Is set every time a signal transition of the first communication line occurs, and a second flag, which means that a signal transition of the second communication line occurs, is set every time the signal transition of the second communication line occurs, and the two communication lines are set. In case of signal transition in all phases of the furnace, the operation of resetting the two flags is performed for each signal transition of each communication line so that error detection and line transfer can be performed. It provides a redundancy device and a method thereof.

1 is a block diagram showing the concept of a communication line redundancy control device using conventional software;

2 is a block diagram of a communication line redundancy control device using conventional hardware.

3 is a diagram illustrating the structure of a message packet in HDLC / SDLC communication used in a conventional communication line duplication technology.

Figure 4 is a block diagram showing the configuration of the communication line redundancy device of the present invention

5 is a circuit diagram illustrating an embodiment of an error detection and line selection controller in a communication line redundancy device of the present invention;

6 is a signal waveform diagram of each circuit part for explaining the operation of FIG.

In the serial data communication system of the present invention, a redundancy apparatus of a communication line is provided; A serial data communication system having at least two communication lines and transmitting the same digital signal to the plurality of communication lines between at least two processors to perform mutual data communication.

First transition detecting means for detecting a transition of a digital signal input through a first communication line, second transition detecting means for detecting a transition of a digital signal input through a second communication line, and the first transition Error detection means for detecting the presence of an error by receiving the detection signal of the detection means and the second transition detection means by comparing the frequency of signal transitions occurring in the two communication lines with each other, and receiving the error detection signal of the error detection means And a line transfer means for performing a line transfer between a normal line and a fault line using the determined result and determining the line.

In the serial data communication system of the present invention configured as described above, in the redundancy apparatus of the communication line, the frequency of signal transitions occurring in each of the two communication lines is detected using the hardware signal transition flag for each communication line. It is to perform the line transfer and the presence or absence of failure from the set / reset state of.

The signal transition detecting means detects a signal transition (rising edge or falling edge) of each communication line, and the detected edge detection signal is input to the error detection means.

The error detection means detects the presence or absence of a data error by comparing the edge detection signals detected from the data input through the two lines, which means that one of the two communication lines is disconnected, shorted, line matched / transmitted or received. If a failure occurs due to a failure, the data on the failed track side is based on the fact that no transition of data bits is detected while the data on the normal track side is received.

When the error detection signal is input as described above, the line switching means determines the fault line and blocks the data receiving system of the fault line and maintains the data receiving system of the normal line so as to control data reception through the normal line.

4 is a block diagram showing a circuit configuration of a duplication apparatus of a communication line in the serial data communication system of the present invention. The line matching and transmitting / receiving unit 401 for the first communication line and the line for the second communication line are shown in FIG. A first edge detector 403 for detecting an edge (signal transition) of a digital signal input through the matching and transmitting / receiving unit 402, the first line matching and transmitting / receiving unit 401, and the second line matching. And a second edge detector 404 for detecting an edge (signal transition) of the digital signal inputted through the transceiver 402, and an occurrence frequency of the edge detector signal detected by the edge detectors 403 and 404. The error detection and line selection control unit 405 and the line matching and transmitting / receiving unit which detects the presence or absence of an error and determine a fault line from error detection to perform line selection control, and output line error information. 401, 402 input from The line detection unit 406 which selects a normal line by the error detection and line selection control unit 405 and the line error information among the ground signals, and the line selection unit 406 of the communication line selected by the line selection unit 406 And a main controller 407 for receiving and processing data.

As an example, the edge detectors 403 and 404 of FIG. 4 detect rising edges or falling edges of digital signals (data) or both rising and falling edges.

As an example, the line selector 406 of FIG. 4 may be a 2: 1 multiplexer.

In FIG. 4, the first line matching and transmitting / receiving unit 401 is responsible for line matching between the first line and the processor, data transmission, reception, and noise cancellation, and the second line matching and transmitting / receiving unit 402 is a second line. It is responsible for line matching with the processor and data transmission, reception and noise cancellation.

The first edge detector 403 detects a rising edge or a falling edge of the digital signal (data) input from the first line.

The second edge detector 404 detects the rising edge or the falling edge of the digital signal (data) input from the second line.

Edge detection selects the type of edge to which data transitions more effectively according to the characteristics of the physical layer of the communication method and the communication protocol, the matching of the line and the characteristics of the transceiver.

In addition, the edge detection may be performed by detecting a rising edge or a falling edge, or both a rising edge and a falling edge, and may be performed by a circuit which generates an edge detection pulse at the signal transition timing at the signal transition, or the system. Depending on the characteristics, the rising or falling edge of the data may be used as it is.

The error detection and line selection control unit 405 receives the edge detection signals detected by the edge detection units 403 and 404 and compares the two signals to detect an error, and determines a fault line from the line selection control signal. Outputs

At this time, the error detection can detect the edge occurrence frequency by comparing the case of the first data and the second data with each other, and determines the communication line of which the edge occurrence frequency is relatively low as the faulted line.

Specific embodiments thereof will be described later with reference to FIGS. 5 and 6.

The line error information output from the error detection and line selection control unit 405 is input to the main control unit 407, and the line selection signal output from the error detection and line selection control unit 405 is transferred to the line selection unit 406. It is input as a signal.

By this control signal, the line selecting section 406 selects a normal communication line, that is, selects a line matching and transmitting / receiving section on the normal side, and inputs the received data to the main control section 407.

For example, if a failure of the first line occurs, the first line matching and reception data of the transceiver 401 are selected, and if a failure of the second line occurs, the second line matching and reception data of the transceiver 402 is selected. do.

The data is received by this line selection. At this time, data transmission is transmitted regardless of the faulted line, and error information of the line is read by the main control unit 407 to report the fault content for system maintenance. do.

On the other hand, if both lines are normal in FIG. 4, one communication line is selected according to a predetermined priority.

Then, the main control unit 407 processes only the original operations such as reporting of error information on the obstacle line, transmission and reception of data after line transfer, decryption, and processing.

Fig. 5 is an embodiment in which a falling edge is detected (edge detection pulse output) in the present invention, an error is detected by comparing the falling edge detection pulses with each other, and a line selection control signal is output by a flip-flop using an error detection signal. An example circuit configuration is shown, and FIG. 6 shows an operation signal waveform diagram (timing diagram) of each circuit portion of FIG.

That is, the first flip-flop 403a is set as a hardware flag that receives the falling edge detection pulse for the digital signal of the first line and is set when the edge of the first line is generated and is reset when the edge is generated together with the second line. The second flip-flop 404a is set as a hardware flag that receives a falling edge detection pulse for the digital signal of the second line and is set when an edge of the second line is generated and reset when an edge is generated together with the first line. A NAND gate 405a for applying a reset signal to each flip-flop with the output Q1 (Q2) values of the flip-flops 403a and 404a, and the output Q1 (Q2) values of the flip-flop Signal output Q3 for selecting a normal line by latching the output Q1 of the first flip-flop 403a with the EX-OR gate 405b and the output of the EX-OR gate 405b as a clock. ) Was configured as a third flip-flop 405c.

The reason for detecting the falling edge in this embodiment is in particular taking into account that the logical level of the data is recognized as the logical value '1' in the event of a failure of the communication line, in view of the statistical experience of the field.

In other words, most communication line failures have the highest frequency in the case of disconnection, and when the communication line is disconnected, the signal transition of data is stopped and the logic level of the disconnected side maintains the value '1' ( The reliability of the transition (rising edge) from the logic value '0' to the logic value '1' among the level transitions of the data is relatively low compared to the reliability of the transition (falling edge) from the logic value '1' to the logic value '0'. Based).

Hereinafter, the error detection and the output operation of the line selection control signal according to the embodiment of FIG. 5 will be described with reference to the waveform diagram (timing diagram) of FIG.

A logic value '1' (= Vcc) is maintained at the data input terminal D1 of the first flip-flop 403a, and the first edge detector 403 from the first edge detector 403 for the first communication line data is provided at the clock terminal CP1. Whenever one edge detection pulse is input and the first edge detection pulse is input, the data '1' of the input terminal D1 is latched and output (Q1), and the data input terminal D2 of the second flip-flop 404a is provided. The logic value is maintained at '1' (= Vcc), and the second edge detection pulse from the second edge detection unit 404 for the second communication line data is input to the clock terminal CP2 to input the second edge detection pulse. Each time the data '1' of the input terminal D2 is latched and output Q2.

If both communication lines are normal, the outputs of the first flip-flop 403a and the second flip-flop 404a have the same value '1', so the output of the NAND gate 405a is '0'. '0' is inputted to the clear stages CD1 and CD2 of the flip-flops 403a and 404a so that the flip-flops are reset, so that the edge detection pulses as shown in the waveform diagram of FIG. Each time it is entered, the set / reset is repeated.

At this time, since the EX-OR gate 405b has the same input value from two flip-flops 403a and 404a as '1' or '0', the output is (when both lines are normal). ) Always keep '0'.

However, if any one of the two communication lines has a failure, a failure is detected and a selection control signal of a normal communication line is output. First, when a failure occurs at any time ts on the second communication line, Take a look.

The output Q1 of the first flip-flop 403a for the first communication line will be output as '1' at the timing at which the first falling edge after the time ts is detected, but for the second communication line having a failure The output Q2 of the double flip-flop 404a is still output as reset '0' since no falling edge is detected after the time ts.

At this timing, the output of the NAND gate 405a becomes '1' because the output Q1 of the flip-flop 403a is '1' and the output Q2 of the flip-flop 404a is '0'. Flip-flops 403a and 404a are not reset.

Therefore, at the falling edge detection timing after the fault occurrence time ts, the output of the first flip-flop 403a will continue to remain '1', and the output of the second flip-flop 404a will continue to '0'. maintain.

Therefore, at this timing, the output of the EX-OR gate 405b transitions from '0' to '1', and this signal transition is input to the third flip-flop 405c as the rising edge (clock) as the clock CP3. do.

The third flip-flop 405c latches the output Q1 = '1' of the first flip-flop 403a, which is the data of the input terminal D3, at the timing when the clock CP3 is applied to set the line selection signal to '1'. Will output

When the line selection signal is output as '1', the line selecting unit 406 is switched to the first line matching and transmitting / receiving unit 401 (1 = A, 0 = B) in FIG. 4 to receive a normal first communication line. Data is input to the main control unit 407.

Meanwhile, the output Q1 and Q2 values of the flip-flops 403a and 404a are all input to the main controller 407, so that the main controller 407 has input values of '1' and '0' at the same timing. By recognizing the difference, the first line can be read normally and the second line can read the line error information due to a failure.

As another case, the case where a failure occurs at any time ts on the first communication line will be described.

The output Q2 of the second flip-flop 404a for the second communication line will be output as '1' at the timing at which the first falling edge after the time ts is detected, but the first for the failed first communication line. The output Q1 of one flip-flop 403a is still output as reset '0' since no falling edge is detected after time ts.

At this timing, the output of the NAND gate 405a becomes '1' because the output Q1 of the flip-flop 403a is '0' and the output Q2 of the flip-flop 404a is '1'. Flip-flops 403a and 404a are not reset.

Therefore, at the falling edge detection timing after the fault occurrence time ts, the output of the second flip-flop 404a will continue to be maintained at '1', and the output of the first flip-flop 403a will continue to be '0'. maintain.

Therefore, at this timing, the output of the EX-OR gate 405b transitions from '0' to '1', and this signal transition is input to the clock CP3 of the third flip-flop 405c as a rising edge (clock). do.

The third flip-flop 405c latches the output Q1 = '0' of the first flip-flop 403a, which is the data of the input terminal D3, at a timing at which the clock CP3 is input to set the line selection signal to '0'. Will output

When the line selection signal is output as '0', the line selecting unit 406 is switched to the second line matching and transmitting / receiving unit 402 in FIG. 4 (1 = A, 0 = B) to receive a normal second communication line. Data is input to the main control unit 407.

In this case, the output Q1 and Q2 values of the flip-flops 403a and 404a are all input to the main control unit 407, so that the main control unit 407 has the input values' 0 'and' By recognizing the difference at 1 ', the second line is normal and the first line can read line error information due to a failure.

In the serial data communication system of the present invention, the redundancy apparatus and method of the communication line can be applied universally regardless of the specific communication protocol because it detects an error from the frequency at which the signal transition occurs and determines and switches the fault line. It works.

In addition, since the line transfer is made from the fault line to the normal line by using the edge detection signal, it is possible not only to minimize the amount of defects upon data reception, but also to have high reliability and fast response time.

In addition, in the serial data communication system, it is possible to control the redundancy of the communication line with a high speed response time without any burden on the main controller.

In addition, it is easy to apply and detect the rising edge or the falling edge, the rising edge and the falling edge according to the characteristics of the communication system, and to easily implement the application circuit which generates the edge detection pulse or uses the rising or falling edge as it is. Do.

In addition, according to the present invention, the error detection and line selection control unit performs hardware redundancy, while outputting error information of the line to the main control unit so that the main control unit can read the fault contents of the line. Increased conservatism.

Claims (5)

A serial data communication system having at least two communication lines and transmitting the same digital signal to the plurality of communication lines between at least two processors to perform mutual data communication. First transition detecting means for detecting a transition of a digital signal input through a first communication line, second transition detecting means for detecting a transition of a digital signal input through a second communication line, and the first transition Error detection means for detecting the presence of an error by receiving the detection signal of the detection means and the second transition detection means to compare the signal transition frequency occurring in the two communication lines with each other, and the error line receiving the error detection signal of the error detection means And a line transfer means for performing line transfer between the normal line and the fault line using the determined result. The method of claim 1, wherein the signal transition detecting means detects a rising edge or a falling edge of a digital signal or a rising and falling edge, and the error detecting means compares the occurrence frequency of the edge detection pulse of the signal with each other, Line switching means determines the frequency of the edge detection signal of the signal as a result of the different signal transition occurs as a failure to perform the automatic line transfer to the normal line, characterized in that the redundant communication line in the serial data communication system . The method according to claim 1 or 2, wherein the respective latches of the signal transition detection signals are latched, and the latched two signal transition detection signals are compared with each other using a gate to detect a case having different signal values as an error, A redundancy apparatus for a communication line in a serial data communication system, characterized by outputting any one of the two latched signals as a normal line selection signal using the error detection signal as a clock. A serial data communication system having at least two communication lines and transmitting the same digital signal to the plurality of communication lines between at least two processors to perform mutual data communication. Detects signal transitions of each of the first communication line and the second communication line (rising edge: rising edge and / or falling edge: falling edge), and errors in data transmission from the frequency of signal transitions occurring in each of the two communication lines. 12. A method for redundancy of a communication line in a serial data communication system, comprising detecting a failure of the line. A serial data communication system having at least two communication lines and transmitting the same digital signal to the plurality of communication lines between at least two processors to perform mutual data communication. Detecting a rising or falling edge of the first digital signal input through the first communication line and detecting a rising or falling edge of the second digital signal input through the second communication line; And comparing the occurrence frequency of the detected signal transitions with each other to determine if different signal transitions are detected as an error, distinguishing the normal line from the fault line according to the error determination result, and receiving data through the normal line. 12. A method for redundancy of a communication line in a serial data communication system, characterized by controlling to perform line switching to achieve this.