KR20000004340A - Method for forming an interlayer dielectric of semiconductor devices - Google Patents

Method for forming an interlayer dielectric of semiconductor devices Download PDF

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Publication number
KR20000004340A
KR20000004340A KR1019980025772A KR19980025772A KR20000004340A KR 20000004340 A KR20000004340 A KR 20000004340A KR 1019980025772 A KR1019980025772 A KR 1019980025772A KR 19980025772 A KR19980025772 A KR 19980025772A KR 20000004340 A KR20000004340 A KR 20000004340A
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South Korea
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interlayer insulating
insulating film
forming
gas
interlayer dielectric
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KR1019980025772A
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Korean (ko)
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KR100293816B1 (en
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차용원
김대현
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching

Abstract

PURPOSE: An interlayer dielectric formation method of semiconductor devices is provided to simplify manufacturing process and reduce manufacturing cost without additional flattening process by using HDP-CVD(high density plasma CVD). CONSTITUTION: The interlayer dielectric forming method using the HDP-CVD comprises the steps of: depositing an interlayer dielectric layer(23) on a semiconductor substrate(21) having fine interconnections(22) by using HDP-CVD; and etching the interlayer dielectric layer(23) by controlling a reactive gas and a bias power used at the HDP-CVD process, thereby flattening the surface of the interlayer dielectric layer(23) in-situ.

Description

반도체 소자의 층간 절연막 형성방법Method of forming interlayer insulating film of semiconductor device

본 발명은 반도체 소자의 제조방법에 관한 것으로, 보다 상세하게는, 고밀도 플라즈마 화학기상증착법을 이용한 반도체 소자의 층간 절연막 형성방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming an interlayer insulating film of a semiconductor device using a high density plasma chemical vapor deposition method.

반도체 소자가 고집적화됨에 따라, 다층 금속 배선 및 고밀도의 상호연결(interconnection)구조가 이용되고 있다. 이러한, 다층 금속 배선 기술에서는 하층 배선과 상층 배선 사이에 층간 절연막을 개재시켜 상·하층 배선간을 전기적으로 절연시키고 있다.As semiconductor devices become more integrated, multilayer metallization and high density interconnect structures are used. In such a multilayer metal wiring technology, the upper and lower wirings are electrically insulated through an interlayer insulating film between the lower wiring and the upper wiring.

도 1은 종래 기술에 따른 다층 배선 형성방법을 설명하기 위한 도면으로서, 도시된 바와 같이, 트랜지스터(도시않됨)가 구비된 반도체 기판(1) 상에 공지의 방법으로 하층 배선들(2)을 형성하고, 이러한 하층 배선들(2)을 덮도록 전체 상부에 층간 절연막(3)을 형성한다.FIG. 1 is a view for explaining a method for forming a multilayer wiring according to the prior art. As shown in the drawing, the lower wirings 2 are formed by a known method on a semiconductor substrate 1 having a transistor (not shown). Then, the interlayer insulating film 3 is formed on the entire upper portion so as to cover the lower wirings 2.

그런 다음, 층간 절연막(3)의 소정 부분들을 식각하여 하층 배선들(2)을 노출시키고, 이어서, 전체 상부에 배선용 금속막을 증착시킨 상태에서, 상기 금속막을 패터닝하여 상층 배선(4)을 형성한다.Subsequently, predetermined portions of the interlayer insulating film 3 are etched to expose the lower wiring lines 2, and then the metal film is patterned to form the upper wiring 4 while the wiring metal film is deposited on the entire upper portion. .

그러나, 반도체 소자의 고집적화가 이루어짐에 따라 배선들간의 간격이 감소되고 있기 때문에, 통상의 증착 공정으로는 미세 간격으로 하층 배선들이 형성된 반도체 기판 상에 층간 절연막을 제대로 증착시킬 수 없는 문제점이 있다.However, since the spacing between wirings is reduced as the semiconductor devices are highly integrated, there is a problem in that a normal deposition process cannot properly deposit an interlayer insulating film on a semiconductor substrate on which lower wirings are formed at minute intervals.

따라서, 최근에는 미세 간격으로 배선들이 형성된 반도체 기판 상에 증착 공정과 식각 공정이 동시에 이루어지는 특성을 갖는 고밀도 플라즈마 화학기상증착법(High Density Plasma Chemical Vapor Deposition : 이하, HDP-CVD라 칭함)을 이용하여 층간 절연막을 형성하는 기술이 실시되고 있다.Therefore, in recent years, a high-density plasma chemical vapor deposition method (HDP-CVD), which has a property that a deposition process and an etching process are simultaneously performed on a semiconductor substrate on which wiring lines are formed at minute intervals, is used. The technique of forming an insulating film is implemented.

도 2a 및 도 2b는 종래 HDP-CVD법을 이용한 반도체 소자의 층간 절연막 형성방법을 설명하기 위한 도면으로서, 우선, 도 2a에 도시된 바와 같이, 미세 간격으로 배선들(12)이 형성된 반도체 기판(11) 상에 HDP-CVD법으로 층간 절연막(13)을 증착하고, 이어서, 도 2b에 도시된 바와 같이, 통상 이용되고 있는 화학적기계적연마법(Chemical Mechanical Polishing : 이하, CMP라 칭함)으로 층간 절연막(13)의 표면을 전면 식각하여 상기 층간 절연막(13)의 평탄화를 달성한다.2A and 2B illustrate a method of forming an interlayer insulating film of a semiconductor device using a conventional HDP-CVD method. First, as illustrated in FIG. 2A, a semiconductor substrate having wirings 12 formed at minute intervals ( 11) depositing the interlayer insulating film 13 on the HDP-CVD method, and then, as shown in Figure 2b, the interlayer insulating film by chemical mechanical polishing (CMP), which is commonly used as shown in Figure 2b The entire surface of (13) is etched to achieve planarization of the interlayer insulating film 13.

상기에서, 층간 절연막(13)의 두께는 상·하층 배선 사이에 개재되는 실재 층간 절연막의 두께 보다 더 두껍게 형성하며, 여분의 두께는 평탄화를 위한 식각시에 제거한다.In the above, the thickness of the interlayer insulating film 13 is formed to be thicker than the thickness of the real interlayer insulating film interposed between the upper and lower layer wirings, and the extra thickness is removed during etching for planarization.

그러나, 상기와 같은 HDP-CVD 기술을 이용한 종래 기술에 따른 층간 절연막의 형성방법은 증착 공정과 식각 공정이 동시에 진행되는 HDP-CVD의 고유 특성으로 인하여, 도 3에 도시된 바와 같이, 층간 절연막(13)의 표면에 피크(peak : P)가 발생하게 됨으로써 오히려 후속 공정에 악영향을 미치게 되는 문제점이 있었다.However, the method of forming the interlayer insulating film according to the related art using the HDP-CVD technique as described above is due to the inherent characteristics of the HDP-CVD in which the deposition process and the etching process are simultaneously performed, as shown in FIG. A peak (P) was generated on the surface of 13), which rather adversely affected the subsequent process.

또한, 층간 절연막의 표면에 발생된 피크를 제거하기 위해서 종래에는 반도체 기판 상에 필요 이상의 두께로 층간 절연막을 증착한 후에 CMP 공정을 진행하여 상기 층간 절연막의 표면을 평탄화시키기 때문에, 층간 절연막의 증착 시간이 증가하게 됨은 물론 CMP 공정의 추가로 인하여 제조 비용이 증가하게 되고, 아울러, CMP 공정에 의해 층간 절연막의 표면이 거칠어지거나 또는 표면에 균열이 발생되어 양질의 층간 절연막을 형성할 수 없는 문제점이 있었다.In addition, in order to remove the peaks generated on the surface of the interlayer insulating film, the deposition time of the interlayer insulating film is conventionally deposited by depositing the interlayer insulating film with a thickness greater than necessary on the semiconductor substrate and then planarizing the surface of the interlayer insulating film. In addition, the manufacturing cost increases due to the addition of the CMP process, and the surface of the interlayer insulating film becomes rough or cracks are generated by the CMP process, thereby making it impossible to form a high quality interlayer insulating film. .

따라서, 상기와 같은 문제점을 해결하기 위하여 안출된 본 발명은, CMP 공정 없이도 층간 절연막의 평탄화를 얻을 수 있는 HDP-CVD를 이용한 반도체 소자의 층간 절연막 형성방법을 제공하는데, 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device using HDP-CVD, which can obtain planarization of an interlayer insulating film without a CMP process.

도 1은 종래 기술에 따른 다층 금속 배선 형성방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for forming a multilayer metal wiring according to the prior art.

도 2a 및 도 2b는 종래 고밀도 플라즈마 화학기상증착법을 이용한 층간 절연막 형성방법을 설명하기 위한 단면도.2A and 2B are cross-sectional views for explaining a method of forming an interlayer insulating film using a conventional high density plasma chemical vapor deposition method.

도 3은 종래 고밀도 플라즈마 화학기상증착법을 이용한 층간 절연막 형성방법의 문제점을 설명하기 위한 사진.Figure 3 is a photograph for explaining the problem of the method of forming an interlayer insulating film using a conventional high density plasma chemical vapor deposition method.

도 4a 및 도 4b는 본 발명의 실시예에 따른 고밀도 플라즈마 화학기상증착법을 이용한 층간 절연막 형성방법을 설명하기 위한 공정 단면도.4A and 4B are cross-sectional views illustrating a method of forming an interlayer insulating film using a high density plasma chemical vapor deposition method according to an embodiment of the present invention.

도 5는 본 발명의 실시예에 따라 고밀도 플라즈마 화학기상증착법을 이용하여 층간 절연막을 형성한 상태를 보여주는 사진.5 is a photograph showing a state in which an interlayer insulating film is formed using a high density plasma chemical vapor deposition method according to an embodiment of the present invention.

(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

21 : 반도체 기판 22 : 배선21: semiconductor substrate 22: wiring

23 : 층간 절연막23: interlayer insulation film

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 층간 절연막 형성방법, 고밀도 플라즈마 화학기상증착법을 이용한 반도체 소자의 층간 절연막 형성방법으로서, 미세 간격으로 배선들이 형성된 반도체 기판 상에 고밀도 플라즈마 화학기상증착 공정으로 소정 두께의 층간 절연막을 형성하는 단계; 및 상기 층간 절연막의 표면이 평탄화되도록 상기 고밀도 플라즈마 화학기상증착 공정시에 사용되는 반응 가스 및 바이어스 파워를 변화시켜 상기 층간 절연막을 식각하는 단계를 포함하는 것을 특징으로 한다.A method of forming an interlayer insulating film of a semiconductor device and a method of forming an interlayer insulating film of a semiconductor device using a high density plasma chemical vapor deposition method according to the present invention for achieving the above object, a high density plasma chemical vapor phase on a semiconductor substrate formed with fine intervals Forming an interlayer insulating film having a predetermined thickness by a deposition process; And etching the interlayer insulating film by changing a reaction gas and a bias power used in the high density plasma chemical vapor deposition process so that the surface of the interlayer insulating film is flattened.

본 발명에 따르면, 층간 절연막을 형성한 후에 반응 가스량과 바이어스 파워를 적절하게 조절함으로써, 표면 평탄화가 달성된 양질의 층간 절연막을 형성할 수 있다.According to the present invention, after forming the interlayer insulating film, by adjusting the amount of reaction gas and the bias power appropriately, it is possible to form a good quality interlayer insulating film in which surface planarization is achieved.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 보다 상세하게 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 4a 및 도 4b는 본 발명의 실시예에 따른 층간 절연막 형성방법을 설명하기 위한 공정 단면도로서, 우선, 도 4a에 도시된 바와 같이, 반도체 기판(21) 상에 공지의 방법으로 미세 간격을 갖는 다수개의 배선들(22)을 형성한 상태에서, HDP-CVD법으로 상기 배선들(22)이 덮혀지도록 반도체 기판(21)의 전면 상에 층간 절연막(23)을 증착한다.4A and 4B are cross-sectional views illustrating a method of forming an interlayer insulating film according to an exemplary embodiment of the present invention. First, as shown in FIG. 4A, fine gaps are formed on a semiconductor substrate 21 by a known method. In the state where a plurality of wirings 22 are formed, an interlayer insulating film 23 is deposited on the entire surface of the semiconductor substrate 21 so that the wirings 22 are covered by HDP-CVD.

이때, 층간 절연막(23)은 실제 상·하층 배선들 사이에 개재되는 두께로 증착하며, 증착 챔버내에 주입되는 사일렌(SiH4)가스는 50 내지 150sccm, 산소(O2) 가스는 150 내지 200sccm, 아르곤(Ar) 가스는 50 내지 500sccm으로 하고, 바이어스 파워는 1,500 내지 3,500W로 하여 형성한다.At this time, the interlayer insulating film 23 is actually deposited to have a thickness interposed between the upper and lower layer wirings, and 50 to 150 sccm of the silicon (SiH 4 ) gas injected into the deposition chamber and 150 to 200 sccm of the oxygen (O 2 ) gas. And argon (Ar) gas is 50 to 500 sccm, the bias power is formed to 1,500 to 3,500W.

이어서, 도 4b에 도시된 바와 같이, 상기 HDP-CVD법에 의한 층간 절연막의 형성시에 사용되는 반응 가스들 중에서 증착에 기여하는 가스인 사일렌(SiH4)가스는 0 내지 150sccm, 산소(O2) 가스는 0 내지 200sccm으로 감소시키고, 식각에 기여하는 아르곤(Ar) 가스량과 바이어스 파워(Biad Power)는 각각 100 내지 700sccm, 1,000 내지 4,000W로 증가시켜 층간 절연막(23)에 대한 표면 평탄화를 실시한다.Subsequently, as shown in FIG. 4B, among the reaction gases used in the formation of the interlayer insulating film by the HDP-CVD method, a siren (SiH 4 ) gas, which contributes to deposition, is 0 to 150 sccm and oxygen (O). 2 ) The gas is reduced from 0 to 200 sccm, and the amount of argon (Ar) gas and the bias power, which contribute to etching, are increased to 100 to 700 sccm and 1,000 to 4,000 W, respectively, thereby improving the surface planarization of the interlayer insulating film 23. Conduct.

이 결과, 미세 간격으로 배선들(22)이 형성된 반도체 기판(21) 상에는 피크의 발생없이 표면 평탄화가 달성된 층간 절연막(23)이 형성된다.As a result, on the semiconductor substrate 21 on which the wirings 22 are formed at fine intervals, an interlayer insulating film 23 in which surface planarization is achieved without generating peaks is formed.

도 5는 상기와 같은 공정을 통해 배선들 및 층간 절연막이 형성된 반도체 기판을 보여주는 사진이다. 도시된 바와 같이, 배선들(22)을 피복하는 층간 절연막(23)이 반도체 기판(21)의 전면 상에 도포되어 있으며, 특히, 층간 절연막의 표면은 피크의 발생없이 평탄화가 이루어져 있다.5 is a photograph showing a semiconductor substrate on which wirings and an interlayer insulating layer are formed through the above process. As shown, an interlayer insulating film 23 covering the wirings 22 is applied on the entire surface of the semiconductor substrate 21. In particular, the surface of the interlayer insulating film is planarized without generation of peaks.

따라서, 상기와 같이 반응 가스의 양과 바이어스 파워만을 조절하여 층간 절연막의 표면 평탄화를 달성할 수 있기 때문에 CMP와 같은 식각 공정을 추가로 실시할 필요가 없으며, 이에 따라, CMP 공정으로 인한 층간 절연막의 표면이 거칠게 되거나, 또는 균열이 발생되는 것을 방지할 수 있게 된다.Therefore, since the planarization of the surface of the interlayer insulating film can be achieved by adjusting only the amount of reaction gas and the bias power as described above, it is not necessary to perform an etching process such as CMP, and thus, the surface of the interlayer insulating film due to the CMP process. This roughness or cracking can be prevented from occurring.

이상에서와 같이, 본 발명은 미세 간격으로 배선들이 형성된 반도체 기판 상에 증착 공정과 식각 공정을 동시에 수행하게 되는 HDP-CVD법을 이용하여 층간 절연막을 형성한 후에, 반응 가스량과 바이어스 파워를 조절하여 표면 평탄화가 달성된 층간 절연막을 형성할 수 있으며, 이에 따라, 추가적인 평탄화 공정을 필요로 하지 않기 때문에 공정의 단순화 및 비용 절감의 효과를 얻을 수 있다.As described above, according to the present invention, after the interlayer insulating film is formed by using the HDP-CVD method which simultaneously performs the deposition process and the etching process on the semiconductor substrate on which wiring lines are formed at minute intervals, It is possible to form an interlayer insulating film in which surface planarization has been achieved, and thus, an additional planarization process is not required, thereby simplifying the process and reducing costs.

또한, CMP 공정의 삭제로 인하여 층간 절연막 표면이 거칠어지거나, 또는 표면 균열이 발생되는 것을 방지할 수 있기 때문에 양질의 층간 절연막을 얻을 수 있다.In addition, since the surface of the interlayer insulating film is roughened or surface cracks can be prevented due to the deletion of the CMP process, a high quality interlayer insulating film can be obtained.

한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.

Claims (3)

고밀도 플라즈마 화학기상증착법을 이용한 반도체 소자의 층간 절연막 형성방법으로서,A method of forming an interlayer insulating film of a semiconductor device using a high density plasma chemical vapor deposition method, 미세 간격으로 배선들이 형성된 반도체 기판 상에 고밀도 플라즈마 화학기상증착 공정으로 소정 두께의 층간 절연막을 형성하는 단계; 및Forming an interlayer insulating film of a predetermined thickness on a semiconductor substrate on which wiring lines are formed at minute intervals by a high density plasma chemical vapor deposition process; And 상기 층간 절연막의 표면이 평탄화되도록 상기 고밀도 플라즈마 화학기상증착 공정시에 사용되는 반응 가스 및 바이어스 파워를 변화시켜 상기 층간 절연막을 식각하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.And etching the interlayer insulating film by changing a reaction gas and a bias power used in the high density plasma chemical vapor deposition process so that the surface of the interlayer insulating film is flattened. 제 1 항에 있어서, 상기 고밀도 플라즈마 화학기상증착 공정은, 반응 가스인 SiH4가스는 50 내지 150sccm, O2가스는 50 내지 200sccm, Ar 가스는 50 내지 500sccm으로 하고, 바이어스 파워는 1,500 내지 3,500W로 하는 조건으로 실시하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.The method of claim 1, wherein the high-density plasma chemical vapor deposition process is a reaction gas of SiH 4 gas is 50 to 150sccm, O 2 gas is 50 to 200sccm, Ar gas is 50 to 500sccm, the bias power is 1,500 to 3,500W The interlayer insulation film forming method of a semiconductor element characterized by the above-mentioned. 제 1 항에 있어서, 상기 층간 절연막의 상부 표면을 평탄화시키는 단계는, 반응 가스인 SiH4가스는 0 내지 150sccm, O2가스는 0 내지 200sccm, Ar 가스는 100 내지 700sccm으로 하고, 바이어스 파워는 1,000 내지 4,000W로 하는 조건으로 실시하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성방법.The planarization method of claim 1, wherein the planarization of the upper surface of the interlayer insulating layer comprises: 0 to 150 sccm of SiH 4 gas, 0 to 200 sccm of O 2 gas, and 100 to 700 sccm of Ar gas, and a bias power of 1,000. A method for forming an interlayer insulating film of a semiconductor device, characterized in that it is carried out under the condition of 4,000W to 4,000W.
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