KR20000003624A - Device separation insulation film forming method of semiconductor device - Google Patents
Device separation insulation film forming method of semiconductor device Download PDFInfo
- Publication number
- KR20000003624A KR20000003624A KR1019980024884A KR19980024884A KR20000003624A KR 20000003624 A KR20000003624 A KR 20000003624A KR 1019980024884 A KR1019980024884 A KR 1019980024884A KR 19980024884 A KR19980024884 A KR 19980024884A KR 20000003624 A KR20000003624 A KR 20000003624A
- Authority
- KR
- South Korea
- Prior art keywords
- film
- forming
- insulating film
- aluminum thin
- oxide film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000034 method Methods 0.000 title claims abstract description 24
- 238000000926 separation method Methods 0.000 title abstract description 6
- 238000009413 insulation Methods 0.000 title abstract 4
- 239000010408 film Substances 0.000 claims abstract description 65
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 17
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000010409 thin film Substances 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 11
- 238000002955 isolation Methods 0.000 claims description 26
- 230000000694 effects Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Element Separation (AREA)
Abstract
Description
본 발명은 반도체소자의 소자분리절연막 형성방법에 관한 것으로, 특히 버즈빅이 없는 평탄화된 소자분리절연막을 형성하여 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 기술에 관한 것이다.The present invention relates to a method for forming a device isolation insulating film of a semiconductor device, and more particularly, to a technology capable of improving the characteristics and reliability of a semiconductor device by forming a flattened device isolation insulating film without buzzvik.
종래의 반도체 소자 제조방법에서는, 소자분리 산화막의 형성시 실리콘 질화막을 얇게 증착하고 소자간의 분리를 쉽게 해주기 위해서 실리콘 기판을 식각해준 뒤 소자분리 산화막을 성장시키는 방법을 사용해 왔는데 상기와 같은 종래의 방법에서는 소자 분리 산화막의 측면 부분에서 새부리 모양의 산화막이 활성영역 쪽으로 많이 치고 들어감과 동시에 수직단차가 생기는 등의 비정상적인 성장이 이루어졌다.In the conventional method of manufacturing a semiconductor device, a method of forming a device isolation oxide film by thinly depositing a silicon nitride film and etching the silicon substrate and then growing the device isolation oxide film to facilitate separation between devices has been used. Abnormal growth occurred such that the beak-shaped oxide film squeezed toward the active region in the side portion of the device isolation oxide film and a vertical step occurred at the same time.
반도체 디바이스가 소형화되고 집적화되면서 소자분리 산화막 영역의 면적을 줄여주면서도 소자의 분리를 원활하게 해 줄수 있는 방법이 요구되고 있는데 측면 부분의 새부리 모양 산화막의 액티브 영역으로의 증가는 소자분리 산화막 영역의 면적을 실제 디자인상의 면적보다 증가시키는 효과를 일으키므로 디자인상의 제약을 받게하는 문제점이 있다.As semiconductor devices become smaller and more integrated, there is a need for a method that can reduce the area of the device isolation oxide region and facilitate device separation. An increase in the beak-shaped oxide layer on the side portion to the active region increases the area of the device isolation oxide region. Since there is an effect to increase than the actual design area there is a problem to be subject to design restrictions.
도 1 은 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.1 is a cross-sectional view illustrating a method of forming a device isolation insulating film of a semiconductor device according to the prior art.
먼저, 반도체기판(31) 상부에 패드절연막(도시안됨)을 형성하고 소자분리마스크(도시안됨)를 이용한 식각공정으로 이를 식각한다. 이때, 상기 패드절연막은 산화막과 질화막의 적층구조로 형성된다.First, a pad insulating layer (not shown) is formed on the semiconductor substrate 31 and etched by an etching process using a device isolation mask (not shown). In this case, the pad insulating film is formed in a stacked structure of an oxide film and a nitride film.
그리고, 상기 반도체기판(31)을 산화시켜 소자분리산화막(33)을 형성하고, 상기 패드절연막을 제거한 다음, 후속공정으로 세정 및 게이트산화막(35) 형성공정을 실시한다.In addition, the semiconductor substrate 31 is oxidized to form an isolation oxide layer 33, the pad insulating layer is removed, and a subsequent step of cleaning and forming the gate oxide layer 35 is performed.
여기서, 상기 소자분리산화막(33)은 산화공정이 측면산화공정이 병행되어 상기 패드절연막을 구성하는 패드산화막으로 확산됨으로써 버즈빅이 형성된다.Here, in the device isolation oxide film 33, a oxidization process is performed in parallel with a side oxidation process, and the bird oxide is diffused into the pad oxide film constituting the pad insulating film.
그 다음에, 후속공정으로 트랜지스터 및 캐패시터를 형성하여 반도체 메모리 소자를 형성한다. (도 1)Subsequently, transistors and capacitors are formed in subsequent steps to form semiconductor memory devices. (Figure 1)
따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 버즈빅의 발생을 방지하는 평탄화된 소자분리절연막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 반도체소자의 소자분리절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art, the method of forming a device isolation insulating film of a semiconductor device capable of improving the characteristics and reliability of the semiconductor device by forming a planarized device isolation insulating film that prevents the occurrence of buzz big. The purpose is to provide.
도 1 은 종래기술에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.1 is a cross-sectional view showing a method of forming an isolation film in a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
11,31 : 반도체기판 13 : 패드산화막11,31: semiconductor substrate 13: pad oxide film
15 : 알루미늄박막 17 : PECVD 산화막15 aluminum thin film 17 PECVD oxide film
19 : CVD 산화막 21 : 감광막19: CVD oxide film 21: photosensitive film
23,33 : 소자분리산화막 35 : 게이트산화막23,33: device isolation oxide film 35: gate oxide film
100 : 트렌치100: trench
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은,In order to achieve the above object, a device isolation insulating film forming method of a semiconductor device according to the present invention,
패드산화막이 형성된 반도체기판 상부에 알루미늄박막을 형성하는 공정과,Forming an aluminum thin film on the semiconductor substrate on which the pad oxide film is formed;
소자분리마스크를 이용한 식각공정으로 알루미늄박막, 패드산화막 및 일정두께의 반도체기판을 식각하여 트렌치를 형성하는 공정과,Forming a trench by etching an aluminum thin film, a pad oxide film, and a semiconductor substrate having a predetermined thickness by an etching process using an element isolation mask;
상기 트렌치를 매립하는 PECVD 절연막을 형성하는 공정과,Forming a PECVD insulating film filling the trench;
상기 PECVD 절연막을 버퍼드 HF 식각공정으로 일정두께 식각하여 상기 알루미늄박막을 노출시키는 공정과,Etching the PECVD insulating film to a predetermined thickness by using a buffered HF etching process to expose the aluminum thin film;
상기 알루미늄박막을 리프트-오프시키는 공정과,Lift-off the aluminum thin film;
전체표면상부에 CVD 절연막을 형성하는 공정과,Forming a CVD insulating film over the entire surface;
상기 CVD 절연막 상부를 평탄화시키는 감광막을 형성하는 공정과,Forming a photosensitive film for planarizing an upper portion of the CVD insulating film;
상기 감광막, CVD 절연막, PECVD 절연막을 마스크없이 에치백하여 평탄화된 소자분리절연막을 형성하는 공정을 포함하는 것을 특징으로한다.And etching back the photosensitive film, the CVD insulating film, and the PECVD insulating film without a mask to form a planarized device isolation insulating film.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 제1실시예에 따른 반도체소자의 소자분리절연막 형성방법을 도시한 단면도이다.2A through 2F are cross-sectional views illustrating a method of forming a device isolation insulating film of a semiconductor device according to a first embodiment of the present invention.
먼저, 반도체 기판(11) 상부에 패드 산화막(13)을 형성하고 그 상부에 알루미늄박막(15)을 일정두께 형성한다. (도 2a)First, the pad oxide film 13 is formed on the semiconductor substrate 11, and the aluminum thin film 15 is formed to have a predetermined thickness thereon. (FIG. 2A)
그 다음에, 소자분리마스크(도시안됨)를 이용한 식각공정으로 상기 알루미늄박막(15), 패드산화막(13) 및 일정두께의 반도체기판(11)을 식각하여 트렌치(100)를 형성한다.Next, the trench 100 is formed by etching the aluminum thin film 15, the pad oxide film 13, and the semiconductor substrate 11 having a predetermined thickness by an etching process using a device isolation mask (not shown).
그리고, 상기 트렌치(100)를 매립하는 PECVD 산화막(17)을 전체표면상부에 형성한다. (도 2b)A PECVD oxide film 17 filling the trench 100 is formed on the entire surface. (FIG. 2B)
그 다음에, 버퍼드 ( buffered ) HF 식각공정으로 상기 PECVD 산화막(17)을 식각하여 상기 알루미늄박막(15)을 노출시킨다.Next, the PECVD oxide film 17 is etched by a buffered HF etching process to expose the aluminum thin film 15.
그리고, 상기 알루미늄박막(15)을 리프트-오프 ( lift-off ) 시킨다. (도 2c, 도 2d)Then, the aluminum thin film 15 is lifted off. (FIG. 2C, FIG. 2D)
그 다음에, 전체표면상부에 CVD 산화막(19)을 일정두께 형성한다. 그리고, 상기 CVD 산화막(19) 상부를 평탄화시키는 감광막(21)을 형성한다. (도 2e)Then, a CVD oxide film 19 is formed on the entire surface at a constant thickness. A photosensitive film 21 is formed to planarize the upper portion of the CVD oxide film 19. (FIG. 2E)
그리고, 마스크없이 에치백 ( etch back ) 공정으로 평탄화시켜 그로벌 ( grobal ) 평탄화된 소자분리산화막(23)을 형성한다. (도 2f)In addition, a planarized device isolation oxide film 23 is formed by planarization using an etch back process without a mask. (FIG. 2F)
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 소자분리절연막 형성방법은, 알루미늄박막을 이용한 리프트-오프 공정을 이용하여 그로벌 평탄화된 소자분리절연막을 형성함으로써 반도체소자의 특성 및 신뢰성을 향상시키는 효과가 있다.As described above, the device isolation insulating film forming method of the semiconductor device according to the present invention has the effect of improving the characteristics and reliability of the semiconductor device by forming a global planarized device isolation insulating film using a lift-off process using an aluminum thin film. There is.
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024884A KR20000003624A (en) | 1998-06-29 | 1998-06-29 | Device separation insulation film forming method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980024884A KR20000003624A (en) | 1998-06-29 | 1998-06-29 | Device separation insulation film forming method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20000003624A true KR20000003624A (en) | 2000-01-15 |
Family
ID=19541404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980024884A KR20000003624A (en) | 1998-06-29 | 1998-06-29 | Device separation insulation film forming method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20000003624A (en) |
-
1998
- 1998-06-29 KR KR1019980024884A patent/KR20000003624A/en not_active Application Discontinuation
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5308784A (en) | Semiconductor device and method for making the same | |
| US4713356A (en) | Manufacturing MOS semiconductor device with planarized conductive layer | |
| JPH0449777B2 (en) | ||
| KR100538810B1 (en) | Method of isolation in semiconductor device | |
| US6395598B1 (en) | Semiconductor device and method for fabricating the same | |
| KR950012918B1 (en) | Contact filling method using secondary deposition of selective tungsten thin film | |
| US6682986B2 (en) | Method of forming shallow trench isolation and method of manufacturing a semiconductor device using the same | |
| KR20030000134A (en) | Forming method for field oxide of semiconductor device | |
| US5851901A (en) | Method of manufacturing an isolation region of a semiconductor device with advanced planarization | |
| KR100204023B1 (en) | Method for forming an element isolation region in a semiconductor device | |
| KR20000003624A (en) | Device separation insulation film forming method of semiconductor device | |
| KR100214530B1 (en) | Method for forming trench element isolation structure | |
| KR100345067B1 (en) | Manufacturing method of semiconductor device | |
| JPH05226466A (en) | Manufacture of semiconductor device | |
| KR100195206B1 (en) | Semiconductor isolation method using trench | |
| KR100338938B1 (en) | Manufacturing method for isolation in semiconductor device | |
| KR100271660B1 (en) | Method of fabricating inter isolation film of semiconductor device | |
| KR980012255A (en) | Device isolation method of semiconductor device | |
| KR0139267B1 (en) | Forming method of field oxide in a semicondcutor device | |
| KR100361763B1 (en) | Method for manufacturing isolation layer of semiconductor device | |
| KR100363076B1 (en) | Trench and locos-type associated isolation method | |
| KR20030000129A (en) | Forming method for field oxide of semiconductor device | |
| JPS60206150A (en) | Manufacture of semiconductor device | |
| KR100485158B1 (en) | Method of manufacturing trench and trench in semiconductor | |
| KR950002032B1 (en) | Method of fabricating a trench type capacitor and structure thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |