KR20000003460A - Semiconductor device production method - Google Patents

Semiconductor device production method Download PDF

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Publication number
KR20000003460A
KR20000003460A KR1019980024702A KR19980024702A KR20000003460A KR 20000003460 A KR20000003460 A KR 20000003460A KR 1019980024702 A KR1019980024702 A KR 1019980024702A KR 19980024702 A KR19980024702 A KR 19980024702A KR 20000003460 A KR20000003460 A KR 20000003460A
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oxide film
silicon oxide
forming
wet etching
semiconductor device
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KR1019980024702A
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Korean (ko)
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KR100318470B1 (en
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김한민
김수찬
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김영환
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

Abstract

PURPOSE: A semiconductor element production method is provided to prevent excessive etching of the insulation layer between metal layers and prevent occurrence of fail and void in the forming of bear holes. CONSTITUTION: The semiconductor element is produced in the process of; forming a silicon oxide film(13) on the substrate(11) by means of a high density chemical vapor evaporation; forming a capping layer with less wet etching rate than the silicon oxide film on the silicon oxide film; forming a mask to form a bear hole on the silicon oxide film and wet etching the silicon rich oxide film.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 발명은 고집적도를 요하는 반도체소자를 제조하는 방법에 관한 것으로, 특히 고밀도플라즈마 화학기상증착(이하 HDP CVD : High Density Plasma Chemical Vapor Deposition)으로 형성된 산화막을 금속층간절연막으로 적용하는 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device requiring high integration, and more particularly, to a method for manufacturing a semiconductor device in which an oxide film formed by HDP CVD (High Density Plasma Chemical Vapor Deposition) is applied as an interlayer insulating film. It is about.

반도체메모리소자가 점차 더 고집적화 되어감에 따라 금속배선은 다층화되어 가고 있으며, 또한 하부금속배선과 상부금속배선 간에 형성되는 금속층간절연막은 서로 인접한 하부금속배선 간의 공간을 충분히 매립하면서 평탄화가 가능하여야 한다.As semiconductor memory devices are becoming more and more integrated, metal interconnections are becoming multilayered, and the interlayer dielectric layer formed between the lower metal interconnection and the upper metal interconnection should be flattened while sufficiently filling the space between adjacent lower metal interconnections. .

따라서, 그 특성상 갭-필링(gap filling)이 아주 우수하고 평탄화가 가능한 HDP CVD에 의한 실리콘산화막을 금속층간절연막으로 적용하고 있으며, 또한 공정속도 개선을 위하여 캡핑레이어(capping layer)로서 플라즈마 화학기상증착(이하 PECVD : Plasma Enhanced Chemical Vapor Deposition)에 의해 실리콘산화막을 적용하고 있다.Therefore, the silicon oxide film by HDP CVD, which has excellent gap filling and planarization, is applied as the interlayer dielectric film, and also plasma chemical vapor deposition as a capping layer to improve process speed. The silicon oxide film is applied by PECVD: Plasma Enhanced Chemical Vapor Deposition.

그런데, PECVD에 의한 실리콘산화막은 습식식각율이 크기 때문에 여러 가지 문제점을 일으키게 된다. 도1에는 하부금속배선(12a, 12b, 12c)이 완료된 기판(11) 상에 HDP CVD에 의한 실리콘산화막(13)과 PECVD에 의한 실리콘산화막(14) 적층하여 금속층간절연막(13, 14)을 형성하고, 상기 하부금속배선(12a, 12b, 12c)을 각각 노출시키기 위한 다수의 비아홀을 형성하기 위하여 포토레지스트패턴(15)을 형성한 상태가 도시되어 있다. 도1에서, 금속층 12a와 금속층 12b 간의 간격은 매우 좁기 때문에 금속층 12a 및 12b를 각각 노출시키기 위한 비아홀 간의 간격 역시 매우 좁은 상태이다. 이러한 상태에서 비아홀 형성을 위하여 습식식각 및 건식식각을 차례로 실시하게 되는데, PECVD에 의한 실리콘산화막(14)은 그 습식식각율이 매우 크기 때문에 도1에 도시된 바와 같이 습식식각 완료시(도면의 점선) 포토레지스트패턴 15가 들뜨게 된다. 이에 의해 포토레지스트 패턴 15a가 무너짐으로써 심할 경우 공정 페일(fail)이 발생하게 된다. 또한, 도2에 도시된 바와 같이, 설령 하부금속배선의 금속층(12)간 간격이 충분히 넓어 페일없이 비아홀이 형성되었다 하더라도, 습식식각된 부분이 너무 넓어 이후의 상부금속배선(16)으로 알루미늄막을 증착하고 플로우(flow)시킬 때, 이 알루미늄이 플로우되지 않아 홀 내부에 보이드(void)(17)가 발생하는 문제점도 발생하게 된다.However, the silicon oxide film by PECVD causes various problems because the wet etching rate is large. In Fig. 1, a silicon oxide film 13 by HDP CVD and a silicon oxide film 14 by PECVD are stacked on a substrate 11 on which lower metal wirings 12a, 12b, and 12c are completed, thereby forming intermetallic insulating films 13 and 14. The photoresist pattern 15 is formed to form and to form a plurality of via holes for exposing the lower metal wirings 12a, 12b, and 12c, respectively. In Fig. 1, since the gap between the metal layer 12a and the metal layer 12b is very narrow, the gap between the via holes for exposing the metal layers 12a and 12b, respectively, is also very narrow. In this state, wet etching and dry etching are sequentially performed to form the via holes. Since the wet etching rate of the silicon oxide film 14 by PECVD is very large, as shown in FIG. 1, the wet etching is completed (dotted lines in the drawing). The photoresist pattern 15 is excited. As a result, when the photoresist pattern 15a collapses, a process failure occurs when the photoresist pattern 15a is severe. In addition, as shown in FIG. 2, even if the gap between the metal layers 12 of the lower metal wiring is sufficiently wide so that the via hole is formed without fail, the wet-etched portion is too wide so that the aluminum film is formed by the upper metal wiring 16. When depositing and flowing, this aluminum does not flow, which results in a void 17 occurring inside the hole.

본 발명은 상기 문제점을 해결하기 위하여 안출된 것으로써, 금속층간절연막으로서 HDP CVD 실리콘산화막을 적용할 때 금속층간절연막의 과도한 습식식각을 방지하여 비아홀 형성의 페일 및 보이드 발생을 방지하는 반도체소자 제조방법을 제공함을 그 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and when the HDP CVD silicon oxide film is applied as the interlayer insulating film, a method of manufacturing a semiconductor device which prevents excessive wet etching of the interlayer insulating film and prevents generation of via holes and voids. To provide that purpose.

도1 및 도2는 종래기술의 문제점을 나타내는 단면도.1 and 2 are cross-sectional views showing problems of the prior art.

도3은 사일렌가스(SiH4)를 베이스(base)로 한 실리콘산화막 종류별 습식식각률을 나타내는 도표.FIG. 3 is a graph showing wet etch rate for each type of silicon oxide film based on xylene gas (SiH 4 ); FIG.

도4 및 도5는 본 발명의 작용효과를 설명하기 위한 단면도.4 and 5 are cross-sectional views for explaining the effect of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

11 : 기판11: substrate

12, 12a, 12b, 12c : 금속층12, 12a, 12b, 12c: metal layer

13 : HDP CVD에 의한 실리콘산화막13: silicon oxide film by HDP CVD

24 : HDP CVD에 의한 실리콘리치산화막24 silicon rich oxide film by HDP CVD

15, 15a : 포토레지스트 패턴15, 15a: photoresist pattern

16 : 상부금속층16: upper metal layer

17 : 보이드17: void

상기 목적을 달성하기 위한 본 발명은, 반도체소자 제조방법에 있어서, 하부금속배선이 완료된 기판을 준비하는 단계; 상기 기판 전체구조 상부에 고밀도 플라즈마 화학기상증착에 의해 실리콘산화막을 형성하는 단계; 상기 실리콘산화막 상에 상기 실리콘산화막 보다 습식식각률이 적은 박막으로 공정속도 향상을 위한 캡핑레이어를 형성하는 단계; 및 상기 실리콘리치산화막 상에 비아홀 형성을 위한 마스크를 형성하고 상기 실리콘리치산화막을 습식식각하는 단계를 포함하여 이루어진다.In accordance with another aspect of the present invention, a method of manufacturing a semiconductor device includes: preparing a substrate on which lower metal wiring is completed; Forming a silicon oxide film on the entire substrate structure by high density plasma chemical vapor deposition; Forming a capping layer for improving process speed on the silicon oxide layer using a thin film having a lower wet etching rate than the silicon oxide layer; And forming a mask for forming a via hole on the silicon rich oxide film and wet etching the silicon rich oxide film.

바람직하게, 상기 캡핑레이어는 고밀도 플라즈마 화학기상증착에 의한 실리콘리치산화막을 적용한다.Preferably, the capping layer is applied to the silicon rich oxide film by high-density plasma chemical vapor deposition.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다. 종래기술과 동일한 구성요소(박막)에 대해서는 동일한 도면부호를 인용하였다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. The same reference numerals are used for the same components (thin films) as in the prior art.

도3은 사일렌가스(SiH4)를 베이스(base)로 한 실리콘산화막 종류별 습식식각률을 나타내는 도표로서, 습식식각제는 BOE(buffered oxide etchant) 용액이다. 도3에 나타난 바와 같이, HDP CVD에 의해 증착된 실리콘리치산화막(silicon rich oxide)은 그 습식식각률이 매우 적음을 알 수 있다.FIG. 3 is a diagram illustrating wet etching rates of silicon oxide films based on xylene gas (SiH 4 ), and a wet etching agent is a buffered oxide etchant (BOE) solution. As shown in FIG. 3, it can be seen that the silicon rich oxide deposited by HDP CVD has a very small wet etch rate.

따라서, 본 발명의 일실시예는 금속층간절연막으로서, HDP CVD에 의한 실리콘산화막을 하부에 그리고 캡핑레이어로서 HDP CVD에 의한 실리콘리치산화막을 상부에 형성하는 것이다.Therefore, one embodiment of the present invention is to form a silicon oxide film by HDP CVD as a metal interlayer insulating film, and a silicon rich oxide film by HDP CVD as a capping layer.

도3에는 하부금속배선(12a, 12b, 12c)이 완료된 기판(11) 상에 HDP CVD에 의한 실리콘산화막(13)과 캡핑레이어로서 HDP CVD에 의한 실리콘리치산화막(24)을 적층하여 금속층간절연막(13, 24)을 형성하고, 상기 하부금속배선(12a, 12b, 12c)을 각각 노출시키기 위한 다수의 비아홀을 형성하기 위하여 포토레지스트패턴(15)을 형성한 상태가 도시되어 있다. 도1에서, 금속층 12a 및 12b를 각각 노출시키기 위한 비아홀 간의 간격이 좁은 상태이지만, 종래와는 달리 캡핑레이어인 HDP CVD에 의한 실리콘리치산화막(24)이 습식식각률이 적기 때문에 습식식각후에도 심한 언더컷(under cut)이 발생하지 않는다. 따라서, 포토레지스트 패턴 15a가 무너지는 문제점을 발생치 않는다.3, a silicon oxide film 13 by HDP CVD and a silicon rich oxide film 24 by HDP CVD as a capping layer are laminated on the substrate 11 on which the lower metal wirings 12a, 12b, and 12c are completed. A state in which the photoresist pattern 15 is formed to form (13, 24) and to form a plurality of via holes for exposing the lower metal wirings 12a, 12b, and 12c, respectively, is shown. In Fig. 1, although the gap between via holes for exposing the metal layers 12a and 12b is narrow, the silicon rich oxide film 24 by the HDP CVD, which is a capping layer, has a low wet etching rate, unlike the conventional art, so that a severe undercut even after wet etching is performed. under cut) does not occur. Therefore, the problem that the photoresist pattern 15a collapses does not occur.

도5와 같이, 비아홀 형성후 상부금속배선(16)으로 알루미늄막 증착하고 플로우(flow)시킬 때, 습식식각된 폭이 좁기 때문에 알루미늄이 충분히 플로우되어 비아홀 내부에 보이드(void) 없이 알루미늄을 매립할 수 있다.As shown in FIG. 5, when the aluminum film is deposited and flowed into the upper metal wiring 16 after the via hole is formed, aluminum is sufficiently flowed to fill the aluminum without voids in the via hole because the wet-etched width is narrow. Can be.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명은 금속층간절연막으로 HDP CVD 실리콘산화막을 적용할 경우 캡핑레이어로 습식식각률(wet etch rate)이 작은 박막을 사용함으로써, 비아홀이 밀집되어 있는 곳에서의 습식식각시 과도한 언더컷(under-cut)을 방지하여 포토레지스트패턴의 무너짐을 방지하고, 또한 상부 금속의 매립을 용이하게 할 수 있다는 효과가 있다.As described above, the present invention uses a thin wet etch rate as a capping layer when the HDP CVD silicon oxide film is used as the interlayer dielectric film, and thus, excessive wet etching in the place where via holes are concentrated. There is an effect that it is possible to prevent the under-cut to prevent the photoresist pattern from falling, and also to facilitate the filling of the upper metal.

Claims (2)

반도체소자 제조방법에 있어서,In the semiconductor device manufacturing method, 하부금속배선이 완료된 기판을 준비하는 단계;Preparing a substrate on which lower metal wiring is completed; 상기 기판 전체구조 상부에 고밀도 플라즈마 화학기상증착에 의해 실리콘산화막을 형성하는 단계;Forming a silicon oxide film on the entire substrate structure by high density plasma chemical vapor deposition; 상기 실리콘산화막 상에 상기 실리콘산화막 보다 습식식각률이 적은 박막으로 공정속도 향상을 위한 캡핑레이어를 형성하는 단계; 및Forming a capping layer for improving process speed on the silicon oxide layer using a thin film having a lower wet etching rate than the silicon oxide layer; And 상기 캡핑레이어 상에 비아홀 형성을 위한 마스크를 형성하고 상기 캡핑레이어를 습식식각하는 단계Forming a mask for via hole formation on the capping layer and wet etching the capping layer; 를 포함하여 이루어진 반도체소자 제조방법.Semiconductor device manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 캡핑레이어는 고밀도 플라즈마 화학기상증착에 의한 실리콘리치산화막인 반도체소자 제조방법.The capping layer is a silicon rich oxide film by a high density plasma chemical vapor deposition method of manufacturing a semiconductor device.
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