KR20000001571A - Flash memory cell control circuit of repair fuse control device - Google Patents

Abstract

PURPOSE: Since a programmed memory cell included in the repair fuse control device is not erased when an electrical repair is performed, a split gate type flash memory device is uncorrectable to a prior state of the repair. Thus, it is required to check a repair characteristic at a first stage of design. In addition, if the repair is performed faultily or if a redundancy cell has a problem, the repaired redundancy line is uncorrectable to a prior state of the repair. CONSTITUTION: A flash memory cell control circuit of a repair fuse control device according to the present invention composes a circuitry for outputting a positive high voltage(13V), a regulated power supply voltage and a negative high voltage(-12V), selectively, and uses the output signal from the circuitry as a gate control signal of the flash memory cell of the repair fuse control device.

Description

Flash memory cell control circuit of repair fuse control circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a repair fuse control circuit of a flash memory device, and in particular, a flash memory cell control circuit of a repair fuse control circuit capable of erasing a flash memory cell of a repair fuse control circuit. It is about.

The repair fuse control circuit of the flash memory device is used to electrically repair a bad address in a nonvolatile memory cell such as a flash memory cell.

In the repair fuse control circuit of the flash memory device illustrated in FIG. 1, the voltage S3 applied to the select gates of the first and second flash memory cells 2 and 3 is inverted through the fourth inverter I4. First and second PMOS transistors P1 and P2 and third and fourth PMOS transistors P3 and P4 for applying the power supply voltage V _CC to the first and second nodes K1 and K2. First and second flash memory cells that receive a voltage S3 applied to the select gate through and a first signal S1 that is a control gate control signal of the first and second flash memory cells 2 and 3, respectively. 2 and 3) connected in series between the latch circuit 1 forming a cross latch structure, the second node K2 and the ground terminal V _ss of the latch circuit 1, and a first inverter. External address signal inverted through the second signal S2 and the second inverter I2 which are the drain enable signals inverted through (I1). Claim that is driven according to (A) 3 and claim 4 NMOS transistor is connected between the (N3 and N4), and a latch first node (K1) and the ground terminal (V _ss) of the circuit (1) in series, a first inverter ( First and second NMOS transistors N1 and N2 driven in response to the input of the second signal S2 and the external address signal A inverted through I1, and a second node that is an output of the latch circuit 1. A NOR gate for outputting a voltage control signal in response to the voltage of K2 and the input of the second signal S2 inverted through the first inverter I1, and an external address signal A and inversion in accordance with the output of the NOR gate And first and second transfer gates M1 and M2 for selectively outputting and repairing the external address signal A. FIG.

The driving method of the repair fuse control circuit of the flash memory device configured as described above is as follows.

The first and second flash memory cells 2 and 3 of the latch circuit 1 are composed of electrically programmable flash memory elements. Each flash memory cell 2 and 3 is a cell initially erased by ultraviolet (UV Erase), and maintains the initial state of each node K1 and K2 of the latch circuit 1.

In the initial state, when the first signal S1 in the low state, the second signal S2 in the high state, and the external address signal A in the low state are input, the first signal of the latch circuit 1 is input. Since one flash memory cell 2 is one and the second flash memory cell 3 is two, the current flowing through the second flash memory cell 3 is equal to two of the current flowing through the first flash memory cell 2. It is doubled. Therefore, the potential of the first node K1 of the latch circuit 1 through which a large amount of current flows is in a low state (0V), and the potential of the second node K2 is in a high state (V _CC ). At this time, the output of the NOR gate in which the signal of which the second signal S2 is inverted through the first inverter I1 and the voltage of the second node K2 are input, respectively, becomes low. Therefore, the first transfer gate M1 which takes the output of the NOR gate as input is turned off, and the second transfer gate M2 is turned on. At this time, the external address signal A in the low state is inverted to the high state through the second inverter I2 and output to the output terminal V _out through the second transfer gate M2. Therefore, it is repaired by the external address signal A to the redundancy cell (not shown).

On the other hand, the first flash memory cell 2 of the latch circuit 1 is programmed, the second flash memory cell 3 maintains an initial UV erase state, and the external address signal A in the high state. When is input, when a read operation is performed according to the first signal S1, the second node K2, which is an output of the latch circuit 1, is latched in a low state and the first node K1 is latched in a high state. At this time, the output of the NOR gate which inputs the voltage of the 2nd signal S2 and the 1st node K1 via the 1st inverter I1, respectively becomes a high state. Therefore, the first transfer gate M1 which takes the output of the NOR gate as input is turned on, and the second transfer gate M2 is turned off. At this time, the external address signal A in the high state is output to the output terminal V _out through the first transfer gate M1. Therefore, it is repaired by the external address signal A to the redundancy cell (not shown). That is, when the voltage output to the output terminal V _out is high, the corresponding address is repaired.

However, in the split gate type flash memory device, if the repair is performed electrically, the programmed flash memory cell in the repair fuse control circuit is not erased and cannot be restored to the pre-repair state. Therefore, the repair characteristics should be checked at the beginning of development, and if the repair is wrong or there is a problem with the replaced redundancy cell, the repaired redundancy line cannot be returned to the state before the repair.

Accordingly, the present invention provides a flash memory cell control circuit of a repair fuse control circuit that can erase a flash memory cell of a programmed repair fuse control circuit after electrically repairing the flash memory device and returning it to a state before repair. The purpose.

To achieve the above object, the present invention provides a positive bias circuit for selectively outputting a positive high voltage and a regulated power supply voltage according to a program and a read signal, an inversion means for inverting the output voltage of the positive bias circuit according to an erase signal; A first switching means for delivering the output voltage of the inverting means to an output terminal, a negative charge pump circuit for outputting a negative high voltage, a negative voltage transfer circuit for delivering an output voltage of the negative charge pump circuit in accordance with an erase signal; And second switching means for transferring the output voltage of the negative charge pump circuit to the output terminal according to the output signal of the negative voltage transfer circuit.

1 is a repair fuse control circuit diagram of a flash memory device.

2 is a flash memory cell control circuit diagram of a repair fuse control circuit according to the present invention;

3 is a detailed circuit diagram of the positive bias circuit of FIG.

<Description of the symbols for the main parts of the drawings>

1: latch circuit 2 and 3: flash memory cell

P1 to P4: first to fourth PMOS transistors

N1 to N4: first to fourth NMOS transistors

I1 to I4: first to fourth inverters

K1 and K2: first and second node

M1 and M2: first and second transfer gates

11: positive bias circuit 12: negative charge pump circuit

13: negative voltage transfer circuit 14: inverting means

P11 to P13: first to third PMOS transistors

N11: NMOS transistor

P21 to P23: first to third PMOS transistors

N21: NMOS transistor I11: Inverter

K21 and K22: first and second nodes

The present invention will be described in detail with reference to the accompanying drawings.

2 is a flash memory cell control circuit diagram of a repair fuse circuit according to the present invention, and is driven according to a program and a read signal PGM_RD and an erase signal RWLER.

The flash memory cell control circuit of the repair fuse control circuit according to the present invention includes a positive bias circuit 11 for selectively outputting a positive high voltage of about 13V and a regulated power supply voltage VCCR according to a program and a read signal PGM_RD; Inverting means 14 for outputting or inverting and outputting the positive high voltage output from the positive bias circuit 11 according to the erase signal, and the gate is in a ground state so that it is always turned on and the output of the inverting means 14 A second PMOS transistor P12 for transmitting a signal to an output terminal, a negative charge pump circuit 12 for outputting a negative high voltage of about -12V, and an output signal for the erase signal and the negative charge pump circuit 12 are input as inputs. According to the negative voltage transfer circuit 13 for delivering the negative high voltage and the output signal of the negative voltage transfer circuit 13 And a third PMOS transistor P13 for delivering the output signal of the negative charge pump circuit 12 to the output terminal without a voltage drop.

The driving method of the flash memory cell control circuit of the repair fuse control circuit according to the present invention configured as described above is as follows.

First, a positive bias circuit 11 for selectively outputting a high voltage of about 13V and a regulated power supply voltage VCCR according to a program and read (PGM_RD) signal will be described with reference to FIG. 3.

The program and read signals PGM_RD are input with a high state signal when programming a flash memory cell of a repair fuse control circuit, and with a low state signal when erasing or reading a flash memory cell.

The circuit driving when the high state program and read (PGM_RD) signals are input to program the repair cell will be described as follows.

The program and read signals in the high state are input to the inverter I21 through the NMOS transistor N21 which is always turned on by applying the power supply voltage V _CC to the gate. Since the signal of the high state is inverted to the low state through the inverter I21, the second node K22 maintains the potential of the low state, thereby turning on the first PMOS transistor P21 for supplying the pumping voltage. Since the pumping voltage is supplied through the turned-on first PMOS transistor P21, the first node K21 maintains a potential in a high state. The second PMOS transistor P22 outputting the power supply voltage VCCR regulated by the potential of the first node K21 that maintains the high state is turned off. In addition, the third PMOS transistor P23 in which the second node K22 maintaining the low state outputs the pumping voltage VVCP by the potential is turned on. Accordingly, the pumping voltage VVCP is output to the output terminal V1 through the third PMOS transistor P23.

The circuit driving when a low state program and a read signal are input to erase or read a repair cell will be described below.

The program and read signals in the low state are inputted to the inverter I21 through the NMOS transistor N21 which is supplied with the power supply voltage V _CC to the gate and always maintained on. Since the signal in the low state is inverted to the high state through the inverter I21, the second node K22 maintains the potential in the high state, thereby turning off the first PMOS transistor P21 for supplying the pumping voltage. . Since the first PMOS transistor P21 is turned off and the pumping voltage is not supplied, the first node K21 maintains a potential in a low state. The second PMOS transistor P22 that outputs the power supply voltage VCCR regulated by the potential of the first node K21 that maintains the low state is turned on. In addition, the third PMOS transistor P23 whose second node K22 maintains the high state outputs the pumping voltage VVCP by the potential is turned off. Therefore, the regulated power supply voltage VCCR is output to the output terminal V1 through the second PMOS transistor P22.

As described above, the positive bias circuit outputs the pumping voltage VVCP when the program and read signals maintain the high state, and outputs the regulated power supply voltage VCCR when the program and read signals remain high.

The driving method of the circuit when the program and read signals in the high state and the erase signal in the low state are input will be described below.

The positive bias circuit 11 inputs a high state program and read signal to output a pumping voltage of about 13V. The first PMOS transistor P11 of the inverting means 14 is turned on by the erase signal in the low state, and the first NMOS transistor N11 is turned off. Therefore, the pumping voltage output from the positive bias circuit 11 is output through the first PMOS transistor P11. The pumping voltage output through the inverting means 14 is outputted to the output terminal through the second PMOS transistor P12 whose gate is in the ground state and is always kept on. On the other hand, the negative charge pump circuit 12 outputs a negative high voltage of about -12V. This negative high voltage is input to the negative voltage transfer circuit 13. Since the negative voltage transfer circuit 13 inputs the erase signal in the low state, the negative voltage transfer circuit 13 outputs the high state signal so that the third PMOS transistor P13 is turned off so that the negative high voltage is not output to the output terminal. Therefore, a pumping voltage of about 13V is output to the output terminal, and the flash memory cell of the repair fuse control circuit is programmed.

The circuit driving when the program and read signals in the low state and the erase signal in the high state are input will be described as follows.

The positive bias circuit 11 inputs a low state program and read signal to output a regulated power supply voltage. The first PMOS transistor P11 of the inverting means 14 is turned off by the erase signal in the high state, and the first NMOS transistor N11 is turned on to form a path to the ground. Therefore, since the regulated power supply voltage output from the positive bias circuit 11 is not applied, the output terminal of the inverting means 14 goes low. On the other hand, the negative charge pump circuit 12 outputs a negative high voltage of about -12V. This negative high voltage is applied to the negative voltage transfer circuit 13. Since the negative voltage transfer circuit 13 inputs an erase signal in a high state and outputs a signal of about -15V, the negative voltage transfer circuit 13 turns on the third PMOS transistor P13 to output a negative high voltage to the output terminal without a voltage drop. However, since the gate and the source maintain the ground potential, the second PMOS transistor P12 may prevent breakdown due to a negative high voltage. Therefore, a negative high voltage of about -12 V is output to the output terminal, thereby erasing the flash memory cell of the repair fuse control circuit.

The circuit driving when the program and read signals in the low state and the erase signal in the low state are input will be described as follows.

The positive bias circuit 11 inputs a low state program and read signal to output a regulated power supply voltage. The first PMOS transistor P11 of the inverting means 14 is turned on by the erase signal in the low state, and the first NMOS transistor N11 is turned off. Thus, the regulated power supply voltage output from the positive bias circuit 11 is output through the first PMOS transistor P11. The regulated power supply voltage is output to the output terminal through the second PMOS transistor P12 in which the gate is grounded and always turned on. On the other hand, the negative charge pump circuit 12 outputs a negative high voltage of about -12V. This negative high voltage is applied to the negative voltage transfer circuit 13. Since the negative voltage transfer circuit 13 inputs the erase signal in a low state, the third PMOS transistor P13 is turned off so that the negative high voltage is not output to the output terminal. Therefore, the regulated power supply voltage is output to the output terminal, thereby reading the flash memory cell of the repair fuse control circuit.

When the output signal of the flash memory cell control circuit of the repaired fuse control circuit driven as described above is input to the first signal S1 of the repair fuse control circuit, the bias condition of the repair fuse control circuit is shown in [Table 1].

A signal S2 signal S1 signal V _D V _S V _SG 1st flash memory cell program 0 One 13 V V _CC 0 V 1.8 V Erase the first flash memory cell One One -12V V _CC Floating 0 V 2nd flash memory cell program One One 13 V V _CC 0 V 1.8 V Erase Second Flash Memory Cell 0 One -12V V _CC Floating 0 V Reading Address 0 VCCR 0 V V _CC V _CC

As shown in Table 1, in order to erase the first and second flash memory cells, a control gate control signal of -12V is applied to the control gate and the source is floated.

As described above, according to the present invention, since the flash memory cell of the repair fuse control circuit can be erased to recover before the repair, the repair can be restored to the state before the repair during the check of the repair characteristics or during the repair. This failure can be replaced by another redundancy line, improving the operating characteristics of the flash memory device.

Claims (2)

A positive bias circuit for selectively outputting a positive high voltage and a regulated supply voltage in accordance with program and read signals; Inverting means for inverting the output voltage of the positive bias circuit in accordance with the erase signal; First switching means for transmitting the output voltage of the inverting means to an output terminal; A negative charge pump circuit that outputs a negative high voltage, A negative voltage transfer circuit for transferring the output voltage of the negative charge pump circuit in accordance with the cancellation signal; And a second switching means for transferring the output voltage of the negative charge pump circuit to the output terminal in accordance with the output signal of the negative voltage transfer circuit. 2. The flash memory cell control circuit of claim 1, wherein the first and second switching means are PMOS transistors.