KR100542688B1 - Read disturbance detection circuit of repair register cell and its erasing method - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a read disturbance detection circuit of a repair register cell and an erase method thereof.

2. The technical problem of the invention

The read disturbance of the repair register cell is detected to detect an error in data stored in the repair register cell, and the reliability of the device is improved by erasing the repaired repair cell.

3. Summary of the Solution of the Invention

A repair register cell in which a read disturb error has occurred is added to a sense amplifier for sensing data of a repair register cell by detecting a read circuit of a repair resistor cell having an inverter having an input terminal having a β ratio larger than that of an input terminal of the sense amplifier. When the main memory cell is detected and erased, the erase bias is applied and erased simultaneously.

Description

Read Disturbance Detection Circuit and Repair Method of Repair Register Cells

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read disturbance detection circuit of a repair register cell, and in particular, a repair register cell that stores information repaired in a redundancy circuit of a flash memory device. A read discontinuity detection circuit of a repair register cell which detects this error and erases a repair register cell in which an error occurs when an error occurs in information stored as a read disturbance due to the continuous read after cell) is erased and its erasing It is about a method.

In a flash memory device, when a failed bit occurs, a redundancy circuit is prepared so that the failed bit can be repaired and used as a normal device. Here, the repair register cell is used to store the information to be repaired when performing the repair. In order to sense the state of the repair register cell, a sense amplifier as shown in FIG. 1 is used. The configuration and driving method thereof will be described below.

1 is a circuit diagram of a sense amplifier having a conventional single-ended sensing structure, and is configured as follows.

The first NMOS transistor N11 is turned on by the reference voltage V _REF generated by the reference voltage generator 11 operated according to the enable signal, and is connected to the drain terminal of the repair resistor cell. Supply current from the repair resistor cell. The second NMOS transistor N12 is operated by a reset bar RSTb signal during a power-up reset operation to supply a memory cell current applied through the first NMOS transistor N11 to the latch circuit 12. The first PMOS transistor P11 is operated according to the reset bar RSTb signal, and supplies a power supply voltage V _CC to the latch circuit 12. The latch circuit 12 is composed of first and second inverters I11 and I12 to latch data. The third NMOS transistor N13 is connected between the output terminal of the latch circuit 12 and the ground terminal V _SS to adjust the potential of the output terminal of the latch circuit 12 according to the reset (RST) signal. The third and fourth inverters I13 and I14 are connected between the output terminal of the latch circuit 12 and the output terminal OUT to delay and output the output signal of the latch circuit 12.

The driving method of the sense amplifier configured as described above is as follows.

First, the driving method in the case where the reset signal in the high state is applied from the power-up reset circuit to reset the chip will be described.

When the reset (RST) signal is applied in a high state, a reset bar (RSTb) signal in a low state is applied to the second NMOS transistor N12 and the first PMOS transistor P11 to turn off the second NMOS transistor N12. The first PMOS transistor P11 is turned on. Therefore, even when the reference voltage V _REF is applied and the first NMOS transistor N11 remains in the on state, the second NMOS transistor N12 remains in the off state. Therefore, the repair resistor cell current is transferred to the latch circuit 12. It is not authorized. On the other hand, the power supply voltage V _CC is applied to the latch circuit 12 by the first PMOS transistor P11 maintaining the turn-on state, so that the input terminal of the latch circuit 12 maintains a high state. The signal at the input terminal of the latch circuit 12 that maintains the high state is inverted to the low state through the first inverter I11 and is turned on by the third NMOS transistor N13 turned on by the reset state RST signal in the high state. Having a ground potential keeps it completely low. The signal at the output terminal in the low state is delayed through the third and fourth inverters I13 and I14 and output to the output terminal OUT.

A driving method when the power-up reset signal is applied in a low state will be described below.

When the reset RST signal is applied in the low state, the second NMOS transistor N12 is turned on by the high reset bar RSTb signal, and the first PMOS transistor P11 is turned off. Therefore, since the first PMOS transistor P11 is turned off, the power supply voltage V _CC is not supplied to the latch circuit 12, and the repair resistor cell is turned on because the first and second NMOS transistors N11 and N12 are turned on. Current is supplied to the latch circuit 12.

The current supplied to the latch circuit 12 is determined according to the state of the repair register cell. When the state of the repair register cell is in the erase state, the state of the input terminal of the latch circuit 12 remains high to some extent and then is low. When the state of the repair register cell is in the program state, since the repair register cell current does not flow, the input terminal of the latch circuit 12 remains in a high state.

When the state of the repair register cell is in the erased state, the input terminal of the latch circuit 12 goes low and is inverted to a high state through the first inverter I11 to maintain this state while maintaining the third and fourth inverters I13. And delayed through I14).

On the other hand, when the state of the repair register cell is a program state, the input terminal of the latch circuit 12 goes high and is inverted to a low state through the first inverter I11 to maintain this state while maintaining the third and fourth inverters. The delay is output through (I13 and I14).

However, when the repair register cells are erased, an error may occur in the stored information due to the read disturbance when repeated reading continues, but the reliability of the device may be degraded by the sense amplifier as described above. Cannot be detected. In particular, a device operated by a low voltage has a low read bias of a repair resistor cell, and thus, an erase threshold voltage of a cell is lowered. In this case, the above problem may be further caused.

Accordingly, the present invention is a repair register cell that can detect the read disturbance of the repair register cell to detect that an error occurs in the data stored in the repair register cell, and erase the repair register cell detected an error to improve the reliability of the device An object of the present invention is to provide a read disturbance detection circuit and a method of erasing the same.

According to an embodiment of the present invention, a read discontinuity detection circuit of a repair register cell latches initial information according to a first control signal, and latches data of a repair register cell according to the first and second control signals. And a second means for detecting whether a read disturbance is generated according to an output signal of the first means and data of the repair register cell.

According to another aspect of the present invention, there is provided a method of erasing a repair register cell, wherein an erase bias is applied to a repair register cell in which a read disturbance is generated in an erase step of the memory cell, thereby simultaneously erasing the memory. do.

The present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a sense amplifier having a single-ended sensing structure in which a read disturbance detection circuit according to the present invention is added.

The first NMOS transistor N21 is turned on by the reference voltage V _REF generated by the reference voltage generator 21 operated according to the enable signal, and is connected to the drain terminal of the repair resistor cell. Supply current from the repair resistor cell. The second NMOS transistor N22 is operated by the reset bar RSTb signal during the power-up reset operation to supply the repair resistor cell current applied through the first NMOS transistor N21 to the first latch circuit 22. The first PMOS transistor P21 is operated according to the reset bar RSTb signal, and supplies a power supply voltage V _CC to the first latch circuit 22. The first latch circuit 22 is composed of first and second inverters I21 and I22 to latch data. The third NMOS transistor N23 is connected between the output terminal of the first latch circuit 22 and the ground terminal V _SS to adjust the potential of the output terminal of the first latch circuit 22 according to the reset RST signal. The third and fourth inverters I23 and I24 are connected between the output terminal of the first latch circuit 22 and the first output terminal OUT to delay and output the output signal of the first latch circuit 22.

The fifth and sixth inverters I25 and I26 delay the potential of the first node K21 and apply it to the second latch circuit 23. At this time, since the fifth inverter I25 has a larger β ratio than the first inverter I21 of the first latch circuit 22, the fifth inverter I25 has a trip point that is faster than the first inverter I21. The second latch circuit 23 consists of the seventh and eighth inverters I27 and I28 to latch the potential of the first node K21. The ninth inverter I29 inverts the data latched in the second latch circuit 23 and inputs it to the NOR gate 24. The NOR gate 24 logically combines the output signal of the ninth inverter I29 and the output signal of the fourth inverter I24 and outputs the result to the second output terminal FOUT.

The driving method of the sense amplifier to which the read disturbance detection circuit according to the present invention configured as described above is added is as follows.

First, the driving method in the case where the reset signal in the high state is applied from the power-up reset circuit to reset the chip will be described.

When the reset (RST) signal is applied in a high state, a reset bar (RSTb) signal in a low state is applied to the second NMOS transistor N22 and the first PMOS transistor P21 to turn off the second NMOS transistor N22. The first PMOS transistor P21 is turned on. Therefore, even if the reference voltage V _REF is applied and the first NMOS transistor N21 remains on, the repair resistor cell current is maintained in the first latch circuit 22 because the second NMOS transistor N22 remains off. Is not authorized). Meanwhile, the power supply voltage V _CC is applied to the first latch circuit 22 by the first PMOS transistor P21 maintaining the turn-on state, so that the input terminal of the first latch circuit 22 maintains a high state. The signal of the input terminal of the first latch circuit 22 that maintains the high state is inverted to the low state through the first inverter I21 and is turned on by the high reset reset (RST) signal of the third NMOS transistor N23. Maintains a low state because it has a ground potential. The output terminal signal of the first latch circuit 22 in the low state is delayed through the third and fourth inverters I23 and I24 and output to the first output terminal OUT.

On the other hand, the potential of the first node K21 in the high state is delayed through the fifth and sixth inverters I25 and I26 and input to the second latch circuit 23. The output terminal of the second latch circuit 23 goes low, and the low state signal is inverted to a high state through the ninth inverter I29 and input to the NOR gate 24. The NOR gate 24 inputs the output signal of the ninth inverter I29 in the high state and the output signal of the fourth inverter I24 in the low state to output the low state signal through the second output terminal FOUT. .

A driving method when the reset operation of the chip is terminated and the power-up reset signal is applied to the low state will be described below.

When the reset RST signal is applied in a low state, the second NMOS transistor N22 is turned on by the high reset bar RSTb signal, and the first PMOS transistor P21 is turned off. Therefore, the power supply voltage V _CC is not supplied to the first latch circuit 22 because the first PMOS transistor P21 is turned off, and the first and second NMOS transistors N21 and N22 are turned on, so the repair is performed. The resistor cell current is supplied to the first latch circuit 22.

The current supplied to the first latch circuit 22 is determined according to the state of the repair register cell. When the state of the repair register cell is in the erased state, the input terminal of the first latch circuit 22, that is, the first node K21, The state remains high to some extent and then transitions to a low state, and since the memory cell current does not flow when the state of the repair register cell is a program state, the input terminal of the first latch circuit 22 remains high. Done.

When the repair register cell is in the program state, since the input terminal of the first latch circuit 22 maintains the high state, the first node K21 maintains the high state. The state of the first node K21 that maintains the high state is inverted to a low state through the first inverter I21 of the first latch circuit 22, and is inverted to a high state again through the second inverter I22. Latch the input data. The signal at the output terminal of the first latch circuit 22 in the low state is delayed through the third and fourth inverters I23 and I24 and output to the first output terminal OUT.

On the other hand, the potential of the first node K21 that maintains the high state is delayed through the fifth and sixth inverters I25 and I26 and input to the second latch circuit 23. The signal input in the high state is inverted to the low state through the seventh inverter I27 of the second latch circuit 23 and inverted to the high state through the eighth inverter I28 to latch the data. The signal at the output terminal of the second latch circuit 23 that maintains the low state is inverted to the high state through the ninth inverter I29 and input to the NOR gate 24. The NOR gate 24 logically combines the signal of the high state and the signal of the first output terminal OUT in the low state to output the low state signal.

When the repair register cell is in an erased state, the first node K21 maintains a high state and then transitions to a low state. However, since the β ratio is larger than that of the first inverter I21 of the first latch circuit 22, the trip occurs. In the fifth inverter I25 having a fast point, the transition state is first detected and the operation thereof will be described below.

The potential of the first node K21, which maintains the low state, is delayed through the fifth and sixth inverters I25 and I26 and input to the second latch circuit 23. The low state signal transitions to the high state through the seventh inverter I27 of the second latch circuit 23, and transitions back to the low state through the eighth inverter I28 to latch data. The signal at the output terminal of the second latch circuit 23 that maintains the high state is inverted to the low state through the ninth inverter I29 and input to the NOR gate 24. Meanwhile, the signal of the first node K21 in the low state is inverted to the high state through the first inverter I21 of the first latch circuit 22, and the signals of the high state are in the third and fourth inverters I23 and. Delayed through I24) is output to the first output terminal (OUT). Accordingly, the signal of the first output terminal OUT in the high state and the signal of the low state are input to the NOR gate 24 and are logically combined to output the low-state signal to the second output terminal FOUT.

The operation when the repair register cell is in an erased state but receives a disturbance for continuous reading is described.

When the repair resistor cell receives the disturbance, the threshold voltage of the cell increases, and thus the first node K21 in the low state inputs a potential in the fifth inverter I25. However, only the current before the trip point flows to the first latch circuit 22 so that a current in the reset state of the chip or the programmed state of the repair register cell is applied. In other words, a high state signal is applied. In this case, after the repair register cell is erased, it is not recognized by the sense amplifier as the erased cell due to the disturbance. Therefore, the potential of the first node K21 that maintains the low state is delayed through the fifth and sixth inverters I25 and I26 and input to the second latch circuit 23. The output terminal of the second latch circuit 23 maintains a high state, and this signal is inverted to a low state through the ninth inverter I29 and input to the NOR gate 24. On the other hand, the output terminal of the first latch circuit 22 that maintains the high state becomes a low state, and this signal is output to the first output terminal OUT through the third and fourth inverters I23 and I24. The NOR gate 24 inputs and logically combines the output signal of the first output terminal OUT in the low state and the output signal of the ninth inverter I29 in the low state to output a high state signal.

Table 1 shows the conditions of the repair resistor cell of the sense amplifier to which the read disturbance detection circuit according to the present invention as described above is added.

3 is a block diagram of erasing a main memory cell together when a disturb error occurs in a repair register cell.

The sense amplifier circuit 31 is a sense amplifier to which the read disturbance detection circuit according to the present invention shown in FIG. 2 is added. Here, when the read disturbance is detected, the second output terminal FOUT outputs a high state signal, and the signal and the erase signal ERASE of the second output terminal FOUT are input to the AND gate 32. When the two signals are in the mode high state, the AND gate 32 outputs a high state signal, turns on the NMOS transistor N31 to apply a source voltage to the main cell M11. In addition, the erasing gate voltage is applied to the gate terminal of the main cell M11 by the switching means S11 operated according to the state of the first node K31 which is the output terminal of the AND gate 32. That is, since the first node K31 maintains the high state, the switching means S11 is turned on so that the erase gate voltage is applied to the drain of the main cell M11. In this state, the main cell M11 is erased while the repair register cell is also erased.

4 is a graph illustrating an operation result of a sense amplifier in which a read disturbance detection circuit is added when an error does not occur in a repair register cell, and FIG. 5 is a readout disturbance detection circuit added when a disturbance error occurs in a repair register cell. It is a graph showing the operation result of one sense amplifier. As illustrated, when a disturbance error of the repair register cell is detected, the second output terminal FOUT may maintain a high state.

6 is a flowchart illustrating a method of erasing a repair register cell in which a disturbance error occurs according to the present invention, and a method of simultaneously erasing a repair register cell in which a disturbance error occurs according to the present invention is simultaneously erased. It is to.

When the erase command is input, the address and the fail counter are reset (401), and then the preprogram operation is performed (402), and the program is executed in byte units or word units (403). After the program is executed, program verification is performed (404) to check whether the program operation was successfully performed (405). If the program operation is not successfully performed, it is checked whether the program operation failed by the maximum value set in the fail counter (406). If the program operation fails by the maximum value set in the fail counter, it is determined as a failed cell. Otherwise, the fail operation is incremented and the program operation is performed (403). If the program is successfully executed, it is checked whether the program has been programmed up to the last address (408). If the program has not been programmed up to the last address, the address is increased (409) and the program operation is performed again (403). If the program is successfully programmed up to the last address, an erase operation is performed after resetting the address and the fail counter (410). In order to erase the repair disturbance cell at the same time as the main memory cell, it is checked whether the read disturbance detection circuit detects the disturbance of the repair register cell (411). As a result of the inspection, when the disturbance of the repair register cell is detected, after applying an erase bias of the repair register cell (412), the main memory cells simultaneously perform an erase operation (412). Otherwise, the normal erase operation is performed only on the main memory cell. (413). An erase verification is performed (414) to check whether it has been erased normally (415). If it is not normally erased, it is checked whether the erase operation by the maximum value set in the fail counter has failed (416). If the program operation fails by the maximum value set in the fail counter, it is determined as a failed cell. Otherwise, the fail counter is incremented and it is checked whether the read disturbance of the repair register cell is detected (411). As a result of the erase verification, if the erase is successfully performed, it is checked whether the erase is performed until the last address (418). If the erase verification is not performed until the last address, the address is increased (419) and then erase verification is performed (414). If the address is erased to the last address, the address and the fail counter are reset, and then a post program is executed (420). Post program verification is performed (421) to check whether the operation has been performed normally (422). If the post program is not successfully executed as a result of the check, it is checked whether the post program operation by the maximum value set in the fail counter has failed (423). If the post program operation fails by the maximum value set in the fail counter, it is determined as a failed cell. If not, the post program operation is performed after increasing the fail counter (420). If the post program is verified as a result of the post program verification, it is checked whether the post program is post programmed up to the last address (425). If the post program is not performed until the last address, the address is increased (426) and then the post program is executed (420). If the post program is successfully executed up to the last address, it is determined that the cell has been successfully erased.

As described above, according to the present invention, when the repair register cell storing the repaired information in the redundancy circuit of the flash memory device is erased and subsequently reads, an error occurs in the information stored in the read disturbance, thereby reducing the reliability of the device. A problem can be added to the sense amplifier by detecting a repair resistor cell in which the read disturbance has been generated, thereby detecting and erasing an error, thereby improving device reliability.

1 is a circuit diagram of a sense amplifier having a single-ended sensing structure of a conventional repair cell.

2 is a circuit diagram of a sense amplifier incorporating a read disturbance detection circuit according to the present invention.

3 is a block diagram of erasing a repair register cell in the event of a disturbance error.

4 is a graph illustrating an operation result of a sense amplifier in which a read disturb detection circuit is added when no error occurs in the repair register cell.

5 is a graph illustrating an operation result of a sense amplifier in which a read disturb detection circuit is added when a disturb error occurs in a repair register cell.

6 is a flowchart illustrating a method of erasing a repair register cell in which a disturbance error occurs according to the present invention.

<Description of the symbols for the main parts of the drawings>

11 and 21: reference voltage generator 12: latch circuit

N11 to N13: first to third NMOS transistors

P11: first PMOS transistor

I11 to I14: first to fourth inverters

22 and 23: first and second latch circuit

24: NOR gate

N21 to N23: first to third NMOS transistors

P21: first PMOS transistor

I21 to I29: first to ninth inverters

Claims (6)

A switching unit for outputting data of a repair register cell in response to a signal output from a first control signal and a reference voltage generator; First latch means for latching data of the repair register cell output from the switching unit in response to the first control signal; Second latch means for latching after delaying data of the repair register cell output from the switching unit for a predetermined time; And a detecting means for detecting whether a read disturb occurs in the repair register cell according to a combined signal by combining the output signal of the first latch and the output signal of the second latch. Distortion detection circuit. The method of claim 1 wherein the first means And a delay means for delaying and outputting the data of the repaired register cell which is latched, and initializing means for initializing the first latching means. The method of claim 1, wherein the second means And a delay means for delaying data of the repair register cell and transferring the delayed data to the second latch. The method of claim 1, wherein the detecting means And a logic means for logically combining and outputting the output signal of the second latch means and the output signal of the first latch means. 2. The read disturbance detection circuit of a repair register cell according to claim 1, wherein the β ratio of the inverter of the input terminal of the second latch means is larger than the β ratio of the inverter of the input terminal of the first latch means. Incrementing a preprogram and a program operation in a memory cell by incrementing an address or a deadline counter; Resetting the address and closing counter when the program operation is successful, and then performing an erase operation of the memory cell by incrementing the address or closing counter; Resetting the dress or closing counter when the erase operation is successful, and then executing the post program of the memory cell by incrementing the address or closing counter; If the post program operation is successfully performed, determining that the cell has been successfully erased, And erasing simultaneously with the memory cell by applying an erase bias to a repair register cell having a read disturbance generated in the erase operation of the memory cell.