KR19990085681A - Wiring formation method of semiconductor device by damascene process - Google Patents

Abstract

The wiring formation method of a semiconductor device by a damascene process is disclosed. In the present invention, forming a first planarized interlayer insulating film covering the conductive layer on a semiconductor substrate having a conductive layer, forming an etch stop interlayer insulating film on the planarized interlayer insulating film, and the etch stop Forming a planarized second interlayer insulating film over the interlayer insulating film, etching the flattened second interlayer insulating film to form a groove, and forming a wiring layer in the groove by a damascene process. A wiring forming method of a semiconductor device is provided.

Description

Wiring formation method of a semiconductor device by a damascene process

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, when forming a wiring of a semiconductor device by a damascene process, an interlayer insulating film is formed to prevent an electrical short between the wiring layer formed by the damascene process and a lower conductive layer. It relates to a wiring forming method.

In order to improve layout margins and product characteristics due to high integration of semiconductor devices, it is a general trend to adopt a CMP (Chemical Mechanical Polishing) process. Basically, the adoption of the CMP process enables the tungsten damascene and tungsten plug forming processes to form a tungsten conductive layer with a low sheet resistance, such as conventional metals such as aluminum, and also provides a low resistance. It is possible to form contact holes to have.

However, the margin of the interlayer insulating layer is insufficient between the tungsten damascene and the lower conductive layer due to the change of the thickness of the tungsten damascene layer according to the change of the amount etched by the CMP and the thickness of the interlayer insulating layer removed by the CMP. Phenomenon occurs, and this phenomenon remains a problem to be solved in the CMP process.

In order to solve this problem, the conventional CMP margin of the dielectric film was improved by increasing the thickness of the dielectric film used as the interlayer insulating film. However, according to this method, the aspect ratio of the contact hole formed to form the tungsten plug is increased, resulting in an increase in contact resistance. Therefore, there is a limit to using such a method.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a wiring of a semiconductor device which can secure a margin of an interlayer insulating film during a CMP process when forming a wiring by a damascene process.

1 to 12 are cross-sectional views according to a process sequence to explain a wiring forming method according to a preferred embodiment of the present invention.

13 is a cross-sectional view illustrating a state in which excessive etching is performed on the interlayer insulating film in the wiring forming method according to the present invention.

14 is a cross-sectional view showing a result of forming a wiring layer and a contact by a damascene process in the wiring forming method according to the present invention.

In order to achieve the above object, in the present invention, forming a planarized first interlayer insulating film covering the conductive layer on the semiconductor substrate on which the conductive layer is formed, and forming an etch stop interlayer insulating film on the planarized interlayer insulating film Forming a planarized second interlayer insulating film on the etch stop interlayer insulating film, etching the flattened second interlayer insulating film to form a groove, and forming a wiring layer in the groove by a damascene process. It provides a wiring forming method of a semiconductor device comprising the step of forming.

Preferably, the etch stop interlayer insulating film is formed of a silicon nitride film,

The planarized second interlayer insulating film is formed of a P-TEOS film.

According to the present invention, an electric short circuit between the damascene layer and the lower conductive layer can be prevented even when excessive etching is performed when the dielectric film is etched to form a groove or planarized by a CMP process.

Next, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 to 12 are cross-sectional views according to a process sequence to explain a wiring forming method according to a preferred embodiment of the present invention. In this example, a case of forming a static random access memory (SRAM) cell on a silicon substrate will be described.

Referring to FIG. 1, an isolation layer 12 and a gate oxide layer 14 are formed on a semiconductor substrate 10.

Referring to FIG. 2, the gate conductive layer 16 of the MOS transistor is formed on the semiconductor substrate 10 on which the gate oxide film 14 is formed. The gate conductive layer 16 is formed of doped polysilicon, for example.

Referring to FIG. 3, a planarized interlayer insulating film 20 covering the entire surface of the semiconductor substrate 10 on which the gate conductive layer 16 is formed, for example, an USG (Undoped Silicate Glass) film is formed.

Referring to FIG. 4, the planarized interlayer insulating film 20 is patterned to form a first interlayer insulating film 20a having a contact hole H1 exposing the gate conductive layer 16 and the semiconductor substrate 10. do.

Referring to FIG. 5, a gate conductive layer 22 of a thin film transistor (TFT) used as a load element of an SRAM cell is formed in an upper surface of the interlayer insulating layer 20a and the contact hole H1. The gate conductive layer 22 is formed of doped polysilicon, for example.

Referring to FIG. 6, a gate insulating film 24 of a TFT, for example, a high temperature oxide (HTO) film, is formed on an entire surface of the semiconductor substrate 10 on which the gate conductive layer 22 is formed.

Referring to FIG. 7, the gate insulating layer 24 is patterned to partially expose the gate conductive layer 22. Thereafter, a thin channel conductive layer 26, for example, an amorphous polysilicon layer, of the TFT in contact with the exposed gate insulating film 22 is formed.

Referring to FIG. 8, a planarized second interlayer insulating film 30, for example, an HTO film, is formed on the semiconductor substrate 10 on which the channel conductive layer 26 is formed.

Referring to FIG. 9, a third interlayer insulating film 40, for example, a silicon nitride film, is formed on the second interlayer insulating film 30. The third interlayer insulating film 40 is formed of a dielectric film having a high etching selectivity with respect to the interlayer insulating film to be formed on the upper surface, which serves as an etch stop layer during etching for the damascene process in a subsequent process.

Referring to FIG. 10, a planarized fourth interlayer insulating film 50 is formed on the third interlayer insulating film 40. The fourth interlayer insulating film 50 is formed of a material film having a different etching selectivity from the third interlayer insulating film 40, for example, a P-TEOS film.

Referring to FIG. 11, the fourth interlayer insulating layer 50 is etched to form a wiring by a damascene process to form a groove H2 and a plug contact hole H3 for wiring formation. In this case, the groove H2 and the plug contact hole H3 are completed through separate photolithography processes.

Referring to FIG. 12, a barrier film (not shown), for example, a Ti / TiN film is formed on an inner wall of the groove H2 and the plug contact hole H3, and tungsten is deposited, and then the groove H2 is formed by a CMP process. The wiring layer 52 and the contact 54 are formed in the plug contact hole H3.

FIG. 13 is a cross-sectional view illustrating a state in which excessive etching is performed on the fourth interlayer insulating film 50. In the present invention, since the third interlayer insulating film 40 having an etching selectivity higher than that of the fourth interlayer insulating film 50 is formed below the fourth interlayer insulating film 50, the groove ( Even when excessive etching is performed when H 2 ′) and the plug contact hole H 3 ′ are formed, the third interlayer insulating layer 40 may serve as an etch stop layer to prevent etching to the lower conductive layer.

FIG. 14 is a cross-sectional view illustrating a result of forming the wiring layer 52a and the contact 54a by the damascene process in the groove H2 'and the plug contact hole H3', respectively. The third interlayer insulating film 40 serves as an etch stop layer even when excessive CMP is formed when wiring is formed in the groove H2 'and the plug contact hole H3' to perform the damascene process. Short circuit phenomenon between 52a and the lower conductive layer can be prevented from occurring.

As described above, according to the present invention, since an interlayer insulating film is formed by stacking two or more dielectric films having different etch selectivity between the damascene layer made of a conductive material such as tungsten and the lower conductive layer, the groove is formed by etching the dielectric film. Even when excessive etching occurs during the planarization by the CMP process or the CMP process, an electrical short circuit between the damascene layer and the lower conductive layer can be prevented.

The present invention has been described in detail with reference to preferred embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made by those skilled in the art within the scope of the technical idea of the present invention. Do.

Claims (3)

Forming a planarized first interlayer insulating film covering the conductive layer on the semiconductor substrate on which the conductive layer is formed; Forming an etch stop interlayer insulating film on the planarized interlayer insulating film; Forming a planarized second interlayer insulating film on the etch stop interlayer insulating film; Etching the planarized second interlayer insulating film to form a groove; And forming a wiring layer in the groove by a damascene process. The method of claim 1, wherein the etch stop interlayer insulating film is formed of a silicon nitride film. The method of claim 1, wherein the planarized second interlayer insulating film is formed of a P-TEOS film.