KR19990085293A - Horizontal sync signal detection device for digital television - Google Patents

Abstract

The present invention relates to a horizontal synchronization signal detection device in a digital TV receiver using a residual side band (VSB) method. By simultaneously detecting the synchronization signal and the data symbols on the left and right sides of the section, even when the horizontal sync signal is distorted by the ghost, the horizontal sync signal can be accurately determined, and the influence of the ghost even when checking the reliability of the detected horizontal sync section Also, it is possible to prevent the horizontal synchronization signal from occurring due to the ghost. In addition, by detecting the horizontal synchronizing signal using only the most significant bit having the code information among the input digital data, the overall circuit configuration is simplified, and the number of gates can be reduced when IC is integrated, so the integration is easy and the IC size is reduced. In addition, the cost can be reduced.

Description

Horizontal sync signal detection device for digital television

The present invention relates to a horizontal synchronization signal detection apparatus in a digital TV receiver using a residual side band (VSB) method.

High Definition Television (High Definition Television) is the next generation of digital television systems developed to allow you to feel the impression of a theater in your room. Compared to current analog TVs, the screen resolution is much higher (e.g. 1080 × 1920), wider in the horizontal direction (4: 3.5: 3.1.85: 1.2.4: 1, etc.). 16: 9), CD level sound is supplied in multiple channels (up to 5.1 channels).

Such digital TVs are being standardized by the US, Europe, and Japan in their own broadcasting methods and standards. In the United States, the transmission format adopts the residual sideband (VSB) method proposed by Zenith in the United States, the compression format adopts MPEG (MPEG) for video compression, and Dolby AC-3 for audio compression. The display format is specified to be compatible with existing display methods.

Error correction coding (ECC) is performed on the compressed image data to digitally transmit the image data compressed according to the above standard. At this time, in order to facilitate data recovery on the receiving side, a synchronization signal is created and inserted into a predetermined period between the data before transmitting the data.

The sync signal is largely classified into two types, one as a horizontal sync signal and a data segment sync signal, and the other as a vertical sync signal and a field sync signal.

Looking at one data segment first to know the synchronization signals, as shown in FIG. 1, it is composed of four symbols of the horizontal synchronization signal and 832 symbols of data, the horizontal synchronization signal is not error correction coded. In other words, each data segment is composed of four symbols of a horizontal synchronization signal and a 828 symbol data signal. The frame consists of 313 data segments. The 313 data segment consists of one field sync segment and a 312 general data segment including a training sequence signal.

That is, the transmitting side, such as a broadcasting station, passes a mapper that changes to a desired power level before transmitting a signal. In the case of 8 VSB for terrestrial broadcasting, the output level of the mapper is 8 symbol values (amplitude level), that is,- 168, -120, -72, -24, 24, 72, 120, 168. In addition, the mapper forcibly creates and inserts 4 symbol horizontal sync signals for every 832 symbols by appointment, and field sync signals are forcibly created and inserted at 313 data segment positions. At this time, the promised form of the horizontal synchronization signal is logically 1, 0, 0, 1, and the mapper output level is assigned to '120' when the synchronization is '1' and '-120' when the '0'. That is, the horizontal synchronizing signal has only two levels and is repeated every data segment continuously.

Therefore, in the form of the signal transmitted from the transmitting side, as shown in FIG. 2, the horizontal synchronization signal and the error correction coded data, which are not error corrected coded, are continuously transmitted while forming one data segment.

On the other hand, when a receiving side such as a television receives a VSB modulated RF signal as shown in FIG. 3 through an antenna, the tuner 31 converts a frequency of a desired channel into an IF signal by tuning, and the FPLL unit 32 The IF signal output from the tuner 31 is demodulated into baseband I and Q signals to lock frequency and phase. That is, the FPLL unit 32 is a circuit in which a frequency tracking loop and a PLL are integrated, and locks a frequency first and then locks a phase when the frequency is locked.

The analog / digital (A / D) conversion unit 33 converts the I signal of the FPLL unit 32 into 10-bit digital data. Here, the Q signal is used only for carrier recovery. The synchronization recovery unit 34 restores the horizontal synchronization signal, the field synchronization signal, etc., which were inserted at the time of transmission, using the digitally converted 10-bit data for use in timing recovery. These synchronization signals are designed to facilitate the recovery of the received data. When they are detected incorrectly, the recovery of the data is not performed properly, which greatly affects the whole system.

The equalization and error correction unit 35 uses the horizontal and field synchronization signals restored by the synchronization recovery unit 34 as a training signal to detect linear distortion of amplitude causing interference between symbols and ghosts generated by reflections from buildings or mountains. After correcting equalization, the error generated through the transmission channel is corrected. The video decoder 36 decodes the equalized and error corrected signal using an MPEG algorithm to make the signal visible to the viewer.

In this case, the synchronization recovery unit 34 receives digital data of a plurality of bits (for example, 10 bits) output from the A / D converter 33 and between the horizontal synchronization signal type '1001' and the received signal. The correlation value is calculated, added to the signal input just before one segment, and compared with a predetermined threshold to generate a horizontal synchronization signal indicating the position of the horizontal synchronization inserted by the transmitting side.

However, since the above-described synchronization recovery unit 34 performs integration by using all 10 bits of digital data, assuming that the precision of the delayer for delaying the symbol of one data segment is 6 bits, the circuit configuration is extended to 10 × 6 bits. This becomes very complicated and the gate count is geometrically increased when IC is integrated. This leads to an increase in price with an increase in IC size.

In addition, the horizontal synchronization signal has a shape of '1001', but due to the algorithm characteristic of the FPLL unit 12, the polarity may be inverted to have the form of '0110'. However, conventionally, the synchronization signal was detected without considering the case where the polarity was inverted. Therefore, there is a problem that synchronization detection is not performed correctly.

Therefore, a method for solving this problem has been filed by the applicant (Domestic Patent Application No .: 97-61160, filing date: 97.11.19).

On the other hand, the signal transmitted from the broadcasting station reaches the receiver via the over-the-air channel. In this process, noises are added to the original signal. These noises can be modeled in many forms, including white Gaussian noise and ghosts caused by multiple waves. The effect of the white Gaussian noise can be easily eliminated by continuously integrating the horizontal sync signal periodically inserted in the transmitter. However, ghosts, in particular, ghosts with delays of less than three symbols, distort the shape of the horizontal synchronization signal, greatly degrading the performance of the horizontal synchronization signal detector.

4 illustrates an embodiment in which a ghost is inserted into an original analog horizontal synchronization signal, and the original horizontal synchronization signal as shown by the dotted line of FIG. 4 (b) to the original horizontal synchronization signal as shown in FIG. If a ghost inserted more than half of the signal and delayed by about 1.5 symbols is inserted, the original horizontal sync signal is modified as shown in FIG. In this case, the data interval is 0 because the average value is 0. In this case, it can be seen that when the polarity of the original signal is not inverted, the horizontal synchronization signal is converted to '1000', and if the polarity of the original signal is inverted due to the characteristics of the FPLL unit 32, it is converted to '0111'. have.

Therefore, when the horizontal synchronizing signal is distorted as described above, it is impossible to detect the horizontal synchronizing signal. However, in a real situation, a ghost having a size of 0.6 or more with a delay of about 1.5 symbols may occur frequently.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a horizontal synchronization signal detection apparatus of a digital TV that accurately detects a horizontal synchronization signal even when the horizontal synchronization signal is distorted by ghost.

Another object of the present invention is to provide an apparatus for detecting a horizontal synchronizing signal of a digital TV which examines the reliability of the detected horizontal synchronizing signal in consideration of the influence of ghost.

1 is a view showing the structure of a data frame of a general digital TV

FIG. 2 is a diagram illustrating a transmission form of one data segment of FIG. 1.

3 is a block diagram of a general digital TV receiver

4A to 4C are waveform diagrams illustrating an embodiment of a process in which a ghost is inserted into an original horizontal synchronization signal to deform the horizontal synchronization signal;

5 is a block diagram of a horizontal synchronization signal detection apparatus of a digital TV according to the present invention;

FIG. 6 is a detailed block diagram of the segment correlation unit of FIG. 5. FIG.

FIG. 7 is a detailed circuit diagram of the positive and negative polarity detector of FIG. 6.

FIG. 8 is a detailed block diagram of the segment integrator of FIG. 5. FIG.

9 is a detailed block diagram illustrating an embodiment of the segment decoder of FIG. 5.

10 is a detailed block diagram illustrating another embodiment of the segment decoder of FIG. 5.

Explanation of symbols for the main parts of the drawings

31: Tuner 32: FPLL section

33: A / D converter 34: Synchronous recovery unit

35: equalization / ECC section 36: video decoder

51: segment correlation unit 52: segment integration unit

53: segment slicer 54: segment decoder

61: positive polarity detector 62: negative polarity detector

63: output control unit 64, 82, 84: flip-flop

81: adder 83: limiter

85: 830 Symbol Delay 91,96: 832 Counter

92,97: reliability checker 93,98: horizontal sync signal generator

A feature of the horizontal synchronization signal detection apparatus of the digital TV according to the present invention for achieving the above object is a normal horizontal and negative polarity synchronization signal using the most significant bit and the control signal having code information in the input digital data Detects positive and negative horizontal sync signal patterns considering the ghost inserted together with the pattern, adds the data output as a result of the detection to the integral value before one data segment, and compares it with a specific threshold value. If it is determined to be large, it is to output a signal called a horizontal synchronization section.

Another feature of the present invention is that if the integrated value of the horizontal sync interval is less than a certain threshold due to the ghost, the reliability is kept to the previous state, and the reliability is increased only when the value of the integrated horizontal sync interval is larger than the specific threshold. If the reliability is higher than a certain value after the operation, the horizontal synchronization signal is generated at the timing corresponding to the block requiring the horizontal synchronization signal and output to the corresponding block.

According to another aspect of the present invention, the detection of the horizontal sync signal pattern corresponding to the presence of ghost is performed after setting a plurality of positive and negative horizontal sync signal patterns having a high probability of being deformed due to the ghost. The horizontal synchronization signal section and the data symbols on the left and right sides of the section are simultaneously checked for discrimination.

Another feature of the present invention is that if the sequentially input code bits are input in any one of a pattern of 1001, 0100011 (ghost is present after the original signal), and 1110 (ghost is present before the original signal), the positive horizontal sync is performed. Detection by signal patterns.

Another feature of the present invention is that if the code bits sequentially input are input in any one of the patterns 110, 111100 (ghost is present after the original signal), 00111001 (ghost is present before the original signal), the negative horizontality is applied. It is to detect by a synchronous signal pattern.

Another feature of the present invention is that +2 or +1 is output for segment integration when a positive horizontal sync signal pattern is detected, and +2 or +1 according to a control signal indicating reliability when a negative horizontal sync signal pattern is detected. Outputs -1 otherwise.

According to such a horizontal synchronizing signal detecting apparatus, even if a ghost is present in the original horizontal synchronizing signal and the horizontal synchronizing signal is deformed, the horizontal synchronizing signal can be detected accurately, and the horizontal synchronizing signal is also considered by taking into account the influence of the ghost during reliability check. Malfunctions of blocks that require signals can be prevented.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram illustrating a horizontal synchronization signal detecting apparatus of a digital TV according to the present invention, wherein the most significant bit (Din [9]) having code information among the 10-bit digital data (DIN 9; 0) and a control signal The segment correlator 51 which detects the pattern of the horizontal synchronizing signal even when the ghost is inserted and outputs a logic signal according to the ghost, and continuously adds the output data of the segment correlator 51 at intervals of 832 symbols. Segment integrator 52 that separates the horizontal sync section and the data section, and when it is determined that the output of the segment integrator 52 is greater than a certain threshold, the segment slicer outputting a signal called a horizontal sync section ( 53) and checking the reliability of the horizontal sync section output from the segment slicer 53, and then horizontally to another block requiring the horizontal sync signal. It consists of a segment decoder 54 which provides a synchronization signal. In addition, the segment decoder 54 generates a control signal to control the output of the segment correlation unit 51.

As shown in FIG. 6, the segment correlation unit 51 receives only the most significant bit (Din [9]) having code information (DIN 9; 0) among 10-bit digital data input thereto, and has a positive polarity. The positive polarity detector 61 detecting the synchronization signal pattern receives only the most significant bit DIN [9] having the code information (DIN 9; 0) among the 10-bit digital data inputted therein and has a negative polarity horizontal synchronization signal pattern. Is detected by the negative polarity detecting unit 62 and the positive polarity detecting unit 61, and +2 is output when the horizontal synchronizing signal pattern is detected by the negative polarity detecting unit 62. An output control unit 63 for outputting 2 or +1, and outputting -1 if the horizontal synchronization signal pattern is not detected in either of the positive and negative polarity detection units 61 and 62, and the output data of the output control unit 63; Is a flip-flop 64 for timing alignment.

FIG. 7 illustrates an embodiment in which the positive electrode detection unit 61 and the negative electrode detection unit 62 of FIG. 6 are implemented as gates, and a delay unit for sequentially delaying the input code bits Din [9] by one clock. 71-1 to 71-7 and the AND gate 72-1 to output '1' when the respective outputs of the delayers 71-2 to 71-5 are in the '1001' form, and the delay unit 71-. If each of the outputs 2 to 71-5 is in the form of '0110', the AND gate 72-2 for outputting '1' and the outputs of the delayers 71-1 to 71-7 are in the form of '0100011', '1' if the AND gate 72-3 for outputting '1', the code bits Din [9] input and the outputs of the delayers 71-1 to 71-6 are '1100010' type. AND gate 72-4 for outputting, AND gate 72-5 for outputting '1' if each output of the delayers 71-1 to 71-7 is in the form of '1011100' Din [9]) and the AND gate 72-6 for outputting '1' when the respective outputs of the delayers 71-1 to 71-6 are in the form of '0011101', the AND gate 7 Inputs of the outputs of the OR gates 73-1 and AND gates 72-2, 72-5, and 72-6 that receive and output the respective outputs of 2-1,72-3,72-4 as inputs The OR gate 73-2 is configured to be ORed together. The retarders 71-1 to 71-6 may be configured as flip-flops.

Here, the AND gate 72-1 detects a positive horizontal sync signal pattern in a state where no ghost is present, and the AND gate 72-2 detects a negative horizontal sync signal pattern in a state where there is no ghost. The AND gate 72-3 detects a positive horizontal sync signal pattern considering the case where the ghost is inserted after the original signal, and the AND gate 72-4 detects the case where the ghost is inserted before the original signal. Horizontal sync signal pattern detection of the negative, the AND gate 72-5 is a negative horizontal sync signal pattern detection considering the case where the ghost is inserted after the original signal, and the AND gate 72-6 is a ghost than the original signal It is used for the detection of the negative horizontal sync signal pattern considering the case inserted before. Therefore, when the positive horizontal sync signal pattern is detected regardless of the presence or absence of ghost, the ora gate 73-1 is negative when the ora gate 73-2 is negative or negative. When the synchronization signal pattern is detected, '1' is output to the output controller 63.

In the present invention configured as described above, the shape of the four-level horizontal sync signal inserted into every data segment is promised to have '1001'. If the sync phase of the FPLL unit 32 is 0 degrees, it has '1001'. When the synchronous phase of the FPLL unit 32 is 180 degrees, the polarity is reversed to have '0110'. Accordingly, the 10-bit digital signal output from the A / D converter 33 cannot know the polarity of the signal due to the inaccuracy of the FPLL unit 32. That is, since the polarity of the input signal may be initially changed, the type of the horizontal synchronization signal may be '0110'.

In addition, when the synchronous phase of the FPLL unit 32 is 0 degrees and the ghost is present after the original signal (for example, a position delayed by +1.5 symbols), the pattern of the horizontal synchronous signal is 1000 and the ghost is the original signal. If it exists earlier (for example, -1.5 symbol delayed position), the probability of transformation to '0001' is high. When the synchronous phase of the FPLL unit 32 is 180 degrees and the ghost is present after the original signal (for example, a position delayed by +1.5 symbols), the pattern of the horizontal synchronous signal is '0111' and the ghost is the original signal. If it exists earlier (for example, -1.5 symbol delayed position), it is likely to be transformed into '1110'. Accordingly, the segment correlation unit 51 may detect the horizontal synchronization signal pattern when the input signal pattern is one of '1001', '0110', '1000', '0001', '0111', and '1110'. . However, when the pattern of the original horizontal sync signal and the pattern of the modified horizontal sync signal are simultaneously detected when there is a ghost, the horizontal sync signal detection performance may be deteriorated. This is because there is a high probability of having such a pattern among the data.

Accordingly, in the present invention, the pattern corresponding to the presence of the ghost simultaneously detects the horizontal synchronization section of the four symbols deformed by the ghost and the data symbols on the left and right sides of the section, thereby lowering the probability of occurrence in the data section, thereby reducing the horizontal synchronization signal. Prevents deterioration in detection performance.

Patterns that take this into account include 0100011 (ghosts are positive behind the original signal), 1110 (ghosts are positive before the original signal), 111100 (ghosts are negative after the original signal), 0011101 (negative polarity). Ghosts are present before the original signal). The horizontal synchronizing signal pattern considering the data symbols on the left and right of the horizontal synchronizing section is the most likely pattern, and other patterns can be detected according to the designer's circuit design method. Here, the underlined dark portion is a section of the horizontal synchronization signal modified by the ghost.

4 is an example in which the horizontal synchronizing signal is deformed due to ghosting, the input analog horizontal synchronizing signal waveform is as shown in FIG. 4 (a), and the data value inserted at the transmitting side is a, -a, -a, a. Has a value of -b at position P due to low pass filtering at the transmit side. Here, the -b value is smaller than the -a value. At this time, when a ghost of a certain size is generated, that is, when a ghost having a magnitude of about 0.6 of the original signal and a delay of about +1.5 symbols is inserted as shown in FIG. 4 (b), the original signal is set by the -b value of the P point. A sign is changed and A / D conversion is output in the form of '0100011' as shown in FIG. In this case, the horizontal synchronization signal cannot be recovered conventionally.

However, in the segment correlation unit 51 of the present invention, data segments inputted using only the most significant bit having the sign information among the outputs of the A / D conversion unit 33 are 1001, 0110, 0100011, 1100010, 1011100, 0011101. It detects which one of which has the form, or the other form. That is, the positive polarity detector 61 of the segment correlation unit 51 detects a case in which the input code bit pattern is one of 1001, 0100011, and 1100010, and the negative polarity detector 62 phases the three patterns. In this case, for example, one of 0110, 1011100, and 0011101 is detected and the result is output to the output control unit 63 as a logic signal.

To this end, only the most significant sign bit [Din [9] of the 10-bit digital data output from the A / D converter 33 is used to delay the delays 71-1 to 71-7 of the segment correlation unit 51. Delayed by 1 symbol. At this time, the AND gate 72-1 outputs '1' if each of the outputs of the delayers 71-2 to 71-5 is '1001' type, and the AND gate 72-2 outputs the delay unit ( If each output of 71-2 to 71-5 is in the form of '0110', it outputs '1'. The AND gate 72-3 outputs '1' when each output of the delay units 71-1 to 71-7 has a type of '0100011', and the AND gate 72-4 inputs a sign bit (Din). [9]) If the respective outputs of the retarders 71-1 to 71-6 are in the form of '1100010', '1' is output. When the outputs of the AND gate 72-5 and the delayers 71-1 to 71-7 are in a '1011100' form, '1' is output, and the AND gate 72-6 is input with a sign bit (Din). [9]) If the outputs of the delayers 71-1 to 71-6 are in the form of '0011101', '1' is output.

Table 1 below shows a pattern detection state of the horizontal synchronization signal.

Data interval Horizontal sync signal section Data interval ×× 1 0 0 1 ×× Positive, steady state Detection at end gate 72-1 ×× 0 1 1 0 ×× Negative, steady state Detection at end gate 72-2 × 0 1 0 0 0 1 1 Positive, + presence of delay ghost Detection at end gate 72-3 1 1 0 0 0 1 0 × Positive polarity,-presence of delayed ghosts Detection at end gate 72-4 × 1 0 1 1 1 0 0 Negative, + Delay Ghost Detection at end gate 72-5 0 0 1 1 1 0 1 × Negative,-presence of delayed ghosts Detection at end gate 72-6

That is, the AND gate 72-1 has a positive horizontal sync signal pattern without a ghost inserted therein, and the AND gate 72-2 has a negative horizontal sync signal pattern with a ghost not inserted therein; The AND gate 72-3 is a positive horizontal sync signal pattern considering the ghost inserted after the original signal, and the AND gate 72-4 is a positive horizontal sync considering the ghost inserted before the original signal The signal pattern, the AND gate 72-5 is a negative horizontal sync signal pattern considering the case where the ghost is inserted after the original signal, and the AND gate 72-6 is a case where the ghost is inserted before the original signal. The considered negative horizontal sync signal pattern is detected.

The OR gate 73-1 receives the respective outputs of the AND gates 72-1 and 72-2 and outputs 1 when any one of them is '1', and the OR gate 73-2 is Each of the outputs of the AND gates 72-1, 72-3, and 72-4 is received as an input, and if any one of them is '1', '1' is output to the output controller 63. That is, the output of the ora gate 73-1 becomes the output of the positive polarity detector 61, and the output of the ora gate 73-2 becomes an output of the negative polarity detector 62. This is the case where the positive horizontal sync signal pattern is detected when the output of the OR gate 73-1 is '1', and when the output of the OR gate 73-2 is '1', the negative horizontal sync signal pattern is detected. It means the case of detection.

In the case other than the six patterns, the outputs of the AND gates 72-1 to 72-6 and the OR gates 73-1 and 73-2 are all '0' and the outputs of the two or more AND gates. At the same time, it does not become '1'.

When the output of the positive polarity detector 61 is '1', that is, when the pattern of the horizontal synchronization signal is detected by the positive polarity detector 61, the output controller 63 always outputs '2'. However, when the output of the negative polarity detector 62 is '1', that is, when the horizontal sync signal pattern is detected by the negative polarity detector 62, the output controller 63 is output according to the control signal output from the segment decoder 54. ), The output value is different. That is, when the control signal input from the segment decoder 54 indicates an initial state, for example, when the output of the negative polarity detecting unit 62 is '1' in a period where there is no reliability, the output control unit 63 outputs '2'. When the control signal indicates that a predetermined time has passed after the detection of the horizontal synchronizing signal, for example, when the output of the negative electrode detection unit 62 is' 1 'in a section where reliability is accumulated above a predetermined value, the output control unit 63 may indicate' Output 1 '. If the pattern of the horizontal synchronization signal is detected after a certain time after the detection of the horizontal synchronization signal, the polarity of the input signal is already corrected, and thus may be a normal data section. Will print '1'.

In addition, the output control unit 63 does not detect a horizontal sync signal pattern when the outputs of the positive and negative polarity detectors 61 and 62 are all '0', that is, neither of the positive and negative polarity detectors 61 and 62. If not, it is determined as a normal data interval and always -1 is output. At this time, since the horizontal synchronization signal of 4 symbols is inserted for every 832 symbols, the probability of '-1' is highest in the output control unit 63.

The output data of the output control unit 63 is inputted to the flip-flop 64, timing-aligned, and then input to the segment integrating unit 52.

The segment integrating unit 52 continuously adds an input signal at intervals of 832 symbols to distinguish a data section from a horizontal sync section. That is, when the transmitted signal is mixed with noise while passing through the channel, it may not always have the form of a horizontal synchronization signal. Therefore, the position of the horizontal synchronization signal can be determined only by integrating the values of several data segments.

To this end, as shown in FIG. 8, the segment integrator 52 adds the output data of the segment correlation unit 51 to an adder 81 and a data output from the adder 81. The flip-flop 82 for timing alignment of the limiter, the limiter 83 for limiting the output of the flip-flop 82 when the output of the flip-flop exceeds a predetermined precision limit, for timing alignment of the data output from the limiter 83 A flip-flop 84 and a 830 symbol delay 85 for delaying data output through the flip-flop 84 for 830 symbols. Here, since the input data is delayed by two symbols by one symbol by the flip-flops 82 and 84, the data output from the 830 symbol delay unit 85 is 832 symbol delayed data.

At this time, since the segment integrating unit 52 is configured in an infinite loop, it is necessary to first set an initial value. For example, if the output data of the 830 symbol delay unit 85 is configured to have 6-bit precision and 31 and -32 are set to the upper limit value and the lower limit value, the first 832 symbols are input to the adder 81. The symbol delay unit 85 is set to output -32 as an initial value for 832 symbols.

Accordingly, the adder 81 adds -32 output from the 830 symbol delayer 85 and data sequentially output from the segment correlation unit 51 during the first 832 symbols, and then timings the data through the flip-flop 82. Are arranged and output to the limiter 83.

In this case, since the data output from the 830 symbol delay unit 85 is assumed to have 6 bits of precision, the output of the adder 81 has 7 bits of precision by the addition process. However, due to hardware limitations, the accuracy of the integrator cannot be infinitely increased. Therefore, an integrator of limited precision should be used. If the integration is continued with limited precision, overflow or underflow occurs, so that the limiter 83 has a limit of 6 bits of data output from the adder 81. Beyond this, it limits the upper limit value or the lower limit value among the 6-bit values to prevent overflow or underflow. For example, if the signal input to the limiter 83 exceeds 32, these values cannot be expressed as 6 bits, so the output is limited to 31, which is the upper limit of 6 bits, and values exceeding -33 are the lower limit of 6 bits. The output is limited to -32. The output of the limiter 83 is timing-aligned through the flip-flop 84 and then fed back to the 830 symbol retarder 85 and output to the segment slicer 53.

For example, assuming that the segment correlation unit 51 outputs +2 (ie, horizontal sync interval) only in one symbol and -1 (ie, data interval) in the other symbol for 832 symbols, the adder ( The output of 81) becomes -33 at the symbol position where -1 is output, and -30 at the symbol position where +2 is output. The limiter 83 outputs a limit of -33 to -32, which is a lower limit of 6 bits, and outputs -30 as it is.

When the output of the adder 81 is fed back to the adder 81 after the 832 symbols are delayed again through the flip-flops 82 and 84 and the 830 symbol retarder 85, the output of the adder 81 is -1. The symbol position is -33 at the output symbol position and -28 at the symbol position at which +2 is output. The limiter 83 outputs -33 as -32, and -28 as it is. That is, in the adder 81, data at the same position is added to each data segment. Therefore, the segment integrating unit 52 integrates every 832 symbols.

In this case, the segment correlation unit 51 may output 1 as well as 2 or -1 as described above. In this case, the adder 81 adds 1 to the integral value before one data segment.

If this integration process is repeatedly performed for several data segments, the integration value increases in the horizontal synchronization signal section, and the integration value decreases in the general data section. That is, since the data output from the segment correlator 51 is likely to be -1, the data section is reduced to-when the integration is repeated repeatedly, and the integration section is +2 or +1. When repeated, it increases to the + side. Therefore, as time passes, the sync interval converges to +31 and the data interval converges to -32. At this time, although the data section may have one pattern of 1001, 0110, 0100011, 1100010, 1011100, and 0011101 to increase instantaneously, it eventually becomes smaller than 0 after time passes.

As described above, since the present invention performs integration using only sign bits, the precision of the 830 symbol delay unit 85 is extended to only 6 bits. Thus, the number of gates of the 830 symbol retarder 85 becomes small, which simplifies the circuit and thereby lowers the price.

The output of the segment integrating unit 52 is input to the segment slicer 53.

At this time, since the integral value of the segment integrating unit 52 has a large value in the horizontal synchronizing signal section and a small value in the data section, the segment slicer 53 has this specific threshold value based on a predetermined specific threshold value. If the integral value of the segment integrating unit 52 has a larger value, a signal informing that the segment integrating unit 52 is the horizontal synchronization signal section is output to the segment decoder 54.

FIG. 9 illustrates an embodiment of the segment decoder 54. The 832 counter 91 and 832 outputting an enable signal when the count value has a specific value while sequentially performing a count from 1 to 832. The reliability check unit 92, which is enabled by the enable signal output from the counter 91 and checks the reliability of the signal input from the segment slicer 53, and the reliability of the reliability check unit 92 has a predetermined value or more. It is composed only of the horizontal synchronization signal generator 93 for generating a horizontal synchronization signal at a specific count value position of the 832 counter 91 only.

In FIG. 9 configured as described above, the 832 counter 91 performs a count while looping from 1 to 832, and outputs an enable signal to the reliability check unit 92 when the count value reaches a predetermined value. The reliability check unit 92 is enabled only when the enable signal is input from the 832 counter 91 to check the reliability of the signal input from the segment slicer 53. That is, when the reliability check unit 92 outputs a horizontal synchronization signal (when the integral value is larger than a specific threshold value) from the segment slicer 53 when the reliability checker 92 is enabled, the reliability checker 92 increases the reliability by one step. Decrease. When the reliability is greater than or equal to a certain value, a control signal indicating the reliability is output to the horizontal synchronizing signal generator 93 and the segment correlation unit 51. Here, the control signal is used as a segment lock signal to other blocks (eg, timing recovery, polarity correction, vertical synchronization detection block, etc.) that require a horizontal synchronization signal. The blocks that require a horizontal sync signal only begin operation when they are segment lock.

The horizontal synchronizing signal generator 93 generates a horizontal synchronizing signal at a position where the count value of the 832 counter 91 becomes a specific value when a control signal for generating a horizontal synchronizing signal is input from the reliability check unit 92. do. In this case, since the synchronization signals required in each block do not coincide in timing, when setting a specific value of the 832 counter 91, the synchronization signals are determined according to the timing required in each block, and the horizontal synchronization signal is set at the position of the value. When generated and output to the block, the synchronization signal is output in accordance with the timing required for each block.

On the other hand, the larger the ghost, the more the synchronization signal pattern is deformed, the smaller the size of the original signal at the output of the segment integrator 52 can be. That is, the integrated value of the horizontal synchronization signal section integrated in the integrator 52 may be larger than the integrated value of the data section but may be smaller than a specific threshold due to ghosting. Then, the segment slicer 52 does not output a signal indicating this even in the horizontal synchronization signal section. In this case, the reliability check unit 92 of the segment decoder 54 lowers the reliability. That is, when enabled by the 832 counter 91, if the signal indicating that the horizontal sync interval from the segment slicer 53 is not input, the confidence value is lowered.

If this state is repeated and the reliability is not increased above a certain value, the control signal is not output and the horizontal sync signal generator 93 does not generate the horizontal sync signal, and thus, other blocks requiring the horizontal sync signal ( For example, timing recovery, polarity correction, vertical sync detection block, etc.) do not operate normally.

FIG. 10 is a case where this is improved, and the block structure is the same as that of FIG. 9, except that the reliability of the signal input from the 832 counter 96 is only checked using the signal input from the segment slicer 53 as an enable signal. That is, in the same condition as above, FIG. 9 lowers the reliability, but FIG. 10 differs in that it maintains the reliability to a previous state.

To this end, the reliability check unit 97 is enabled only when a signal indicating that the horizontal sync interval is output from the segment slicer 53 is used to check the reliability of the output to the 832 counter 96, and the 832 counter 96 is 1 To 832 while performing a count while the count value reaches a predetermined value, the predetermined logic signal is output to the reliability check unit 92.

That is, if the integral value of the horizontal synchronization section is smaller than a specific threshold by the ghost, and the signal indicating the horizontal synchronization section is not output from the segment slicer 53, the reliability check unit 97 is not enabled and thus does not change the reliability. Do not. Then, even when the ghost is large, sometimes the integral value of the horizontal synchronization section exceeds a certain threshold, so the reliability check unit 97 at this time is enabled to increase the reliability maintained in the previous state. At this time, the logic signal is always generated from the 832 counter 96 at the same position regardless of the ghost.

When the above process is repeated and the reliability is greater than or equal to a predetermined value, the reliability check unit 97 outputs a control signal indicating this to the horizontal synchronization signal generator 98 and the segment correlation unit 51. Here, the control signal is used as a segment lock signal to other blocks (eg, timing recovery, polarity correction, vertical synchronization detection block, etc.) that require a horizontal synchronization signal. The blocks that require a horizontal sync signal only begin operation when they are segment lock. The operation of the horizontal synchronization signal generator 98 is the same as that of the horizontal synchronization signal generator 93.

That is, the segment decoder having the structure as shown in FIG. 10 can generate a horizontal synchronization signal even when the synchronization signal pattern is deformed much by ghost, thereby preventing the case where other blocks cannot operate due to the ghost.

As described above, an apparatus for detecting a horizontal synchronization signal of a digital TV according to the present invention has the following advantages.

First, when detecting the pattern of the horizontal sync signal, the horizontal sync signal of the original state as well as the horizontal sync signal of the four symbols deformed by the ghost and the data symbols on the left and right sides of the section are simultaneously detected, thereby distorting the horizontal sync signal by the ghost. Even if it is, the horizontal synchronization signal can be detected accurately.

Second, even when the reliability check of the detected horizontal sync interval is considered by the ghost, it is possible to prevent the horizontal sync signal from occurring due to the ghost.

Third, by detecting the horizontal synchronizing signal using only the most significant bit of the input digital data having the sign information, the overall circuit configuration is simplified, and the number of gates can be reduced when IC is integrated, so integration is easy and IC size is reduced. In addition, the cost can be reduced.

Fourth, in determining the pattern of the horizontal synchronization signal using only the sign bit of the received signal, the horizontal synchronization signal pattern having the correct polarity as well as the pattern of the horizontal synchronization signal of the inverted polarity can be detected to detect the accurate horizontal synchronization signal. .

Fifth, when a positive or negative horizontal sync signal pattern is detected in consideration of ghost, +2 is added to the value before 832 symbols, and when a negative horizontal sync signal pattern is detected at a certain value or more, +1 is added. In addition, by adding -1, it is possible to accurately and easily distinguish the data section from the horizontal sync section.

Claims (30)

In the apparatus for detecting the horizontal synchronization signal inserted for each data segment at the transmitting side, A segment correlation unit for detecting a horizontal synchronizing signal pattern when a ghost is inserted together with a normal positive and negative horizontal synchronizing signal pattern by using a most significant bit having a sign information among the input data and a control signal; A segment integrating unit for dividing the horizontal synchronization section and the data section by adding output data of the segment correlation section with a value before one data segment; A segment slicer configured to output a signal called a horizontal synchronization section when it is determined that the output value of the segment integrator is greater than a specific threshold by comparing the output value with the specific threshold; When the reliability of the segment slicer is checked and the reliability is higher than or equal to a predetermined value, the control signal is output to the segment correlation unit and a horizontal synchronization signal is generated at a timing that matches the block requiring the horizontal synchronization signal. And a segment decoder for outputting. The method of claim 1, And digital data input to the segment correlation unit. The method of claim 1, wherein the segment correlation unit When a ghost exists by setting a number of positive and negative horizontal sync signal patterns that are highly likely to be deformed by ghosts, and then simultaneously detecting the horizontal sync signal section of 4 symbols and data symbols on the left and right sides of the section. And detecting a horizontal synchronization signal pattern. 4. The digital TV set according to claim 3, wherein the positive horizontal synchronizing signal having a high probability of deformation due to ghost is set to 1000 (ghost is behind the original signal) and 0001 (ghost is before the original signal). Horizontal sync signal detection device. 4. The digital TV according to claim 3, wherein the negative horizontal synchronization signal having a high probability of deformation due to ghost is set to 0111 (ghost is behind the original signal) and 1110 (ghost is before the original signal). Horizontal synchronization signal detection device. The method of claim 1, wherein the segment correlation unit A positive polarity detector which detects a horizontal synchronous signal pattern having a positive polarity in consideration of ghost along with a horizontal synchronous signal pattern having a positive polarity using the most significant bit having code information among input data; A negative polarity detector which detects a negative polarity horizontal sync signal pattern in consideration of ghost together with a horizontal sync signal pattern of negative polarity using the most significant bit having code information among input data; Outputting a positive constant when a pattern of the horizontal synchronization signal is detected by any of the positive and negative polarity detectors, and outputs a negative constant when the horizontal synchronization signal pattern is not detected by any of the positive and negative polarity detectors. Device for detecting the horizontal synchronization signal of the digital TV. The method of claim 6, wherein the positive detection unit A code bit sequentially input by a combination of a plurality of delay elements, an AND gate, and an ora gate is any one of 1001, 0100011 (ghost is present after the original signal), and 1110 (ghost is present before the original signal) The horizontal synchronization signal detection device of the digital TV, characterized in that detected as a horizontal synchronization signal pattern when input. The underlined dark portion is a section of a horizontal sync signal. The method of claim 6, wherein the negative polarity detecting unit A code bit sequentially input by a combination of a plurality of delay elements, an AND gate, and an ora gate is any one of 110, 111100 (ghost is after the original signal), and 00111001 (ghost is before the original signal). The horizontal synchronization signal detection device of the digital TV, characterized in that detected as a horizontal synchronization signal pattern when input. The underlined dark portion is a section of a horizontal sync signal. The method of claim 6, wherein the output control unit +2 or +1 is output when the pattern of the horizontal synchronization signal is detected by the positive polarity detector, and +2 or +1 is output according to the control signal output from the segment decoder when the pattern of the horizontal synchronization signal is detected by the negative polarity detector. Horizontal sync signal detection device of digital TV. The method of claim 6, wherein the output control unit The negative polarity detector detects a horizontal synchronization signal pattern and outputs +2 when a control signal input from the segment decoder indicates an initial state, and +1 when a reliability is equal to or greater than a predetermined value. Horizontal sync signal detection device. The method of claim 1, wherein the segment integrator is An adder for adding a value before 832 symbols fed back to the output data of the segment correlation unit; And a delay unit which delays the output of the adder for 832 symbols and feeds back to the adder. The method of claim 11, wherein the segment integrator is And a limiter is provided between the adder and the delayer to limit the output of the adder if the output exceeds the limit of a predetermined precision. The method of claim 11, wherein the retarder Two flip-flops that align the timing of input and output data by delaying input data in symbol units, And a 830 symbol delay unit for delaying 830 symbols. The method of claim 1, wherein the segment decoder is A 832 counter for outputting an enable signal when the counted value is a predetermined value and the counted value is preset; A reliability checker which enables the control signal output from the 832 counter and checks the reliability of the signal output from the segment slicer and outputs a control signal only when the reliability is higher than or equal to a predetermined value; And a horizontal synchronizing signal generator for generating a horizontal synchronizing signal at a specific count value position of the 832 counter when the control signal output from the reliability inspecting unit indicates that the reliability is greater than or equal to a predetermined value. The method of claim 1, wherein the segment decoder is A 832 counter for outputting a logic signal when the counted value is a predetermined value and the counted value is preset; A reliability checker which is enabled only when a signal indicating a horizontal synchronization period is output from the segment slicer, and checks the reliability of the output of the 832 counter and outputs a control signal only when the reliability is greater than or equal to a predetermined value; And a horizontal synchronizing signal generator for generating a horizontal synchronizing signal at a specific count value of the 832 counter when the control signal output from the reliability inspecting unit indicates that the reliability is greater than or equal to a predetermined value. In the apparatus for detecting the horizontal synchronization signal inserted for each data segment at the transmitting side, A segment correlation unit for detecting a horizontal synchronization signal pattern having a positive and negative polarity by using a most significant bit having a sign information among the input data and a control signal; A segment integrating unit for dividing the horizontal synchronization section and the data section by adding output data of the segment correlation section with a value before one data segment; A segment slicer which outputs a signal called a horizontal synchronization section when it is determined that the output of the segment integrator is greater than a specific threshold by comparing the output with the specific threshold; If the integrated value of the horizontal sync interval is less than a certain threshold due to ghosting, the reliability remains as it was, and if the integrated horizontal sync interval is greater than a certain threshold, the reliability is increased and then the reliability is above a certain value. When the control signal is output to the segment correlation unit at the same time, the horizontal horizontal signal of the digital TV to generate a horizontal synchronization signal at a timing corresponding to the block that requires a horizontal synchronization signal and output to the block corresponding to the horizontal of the digital TV Synchronous signal detection device. The method of claim 16, And the data input to the segment correlation unit is digital data. The method of claim 16, wherein the segment correlation unit Detection of horizontal sync signal of digital TV, characterized by detecting horizontal sync signal pattern considering ghost insertion along with normal positive and negative horizontal sync signal pattern using the most significant bit having code information among input data Device. The method of claim 18, wherein the segment correlation unit When a ghost exists by setting a number of positive and negative horizontal sync signal patterns that are highly likely to be deformed by ghosts, and then simultaneously detecting the horizontal sync signal section of 4 symbols and data symbols on the left and right sides of the section. And detecting a horizontal synchronization signal pattern. 20. The digital TV set according to claim 19, wherein the positive horizontal synchronization signal having a high probability of deformation due to ghost is set to 1000 (ghost is behind the original signal) and 0001 (ghost is before the original signal). Horizontal sync signal detection device. 20. The digital TV according to claim 19, wherein the negative horizontal sync signal having a high probability of being deformed by the ghost is set to 0111 (ghost is behind the original signal) and 1110 (ghost is before the original signal). Horizontal synchronization signal detection device. The method of claim 16, wherein the segment correlation unit A positive polarity detector which detects a horizontal synchronous signal pattern having a positive polarity in consideration of ghost along with a horizontal synchronous signal pattern having a positive polarity using the most significant bit having code information among input data; A negative polarity detector which detects a negative polarity horizontal sync signal pattern in consideration of ghost together with a horizontal sync signal pattern of negative polarity using the most significant bit having code information among input data; Outputting a positive constant when a pattern of the horizontal synchronization signal is detected by any of the positive and negative polarity detectors, and outputs a negative constant when the horizontal synchronization signal pattern is not detected by any of the positive and negative polarity detectors. Device for detecting the horizontal synchronization signal of the digital TV. The method of claim 22, wherein the positive polarity detector A code bit sequentially input by a combination of a plurality of delay elements, an AND gate, and an ora gate is any one of 1001, 0100011 (ghost is present after the original signal), and 1110 (ghost is present before the original signal) The horizontal synchronization signal detection device of the digital TV, characterized in that detected as a horizontal synchronization signal pattern when input. The underlined dark portion is a section of a horizontal sync signal. The method of claim 22, wherein the negative polarity detector A code bit sequentially input by a combination of a plurality of delay elements, an AND gate, and an ora gate is any one of 110, 111100 (ghost is after the original signal), and 00111001 (ghost is before the original signal). The horizontal synchronization signal detection device of the digital TV, characterized in that detected as a horizontal synchronization signal pattern when input. The underlined dark portion is a section of a horizontal sync signal. The method of claim 22, wherein the output control unit +2 or +1 is output when the pattern of the horizontal synchronization signal is detected by the positive polarity detector, and +2 or +1 is output according to the control signal output from the segment decoder when the pattern of the horizontal synchronization signal is detected by the negative polarity detector. Horizontal sync signal detection device of digital TV. The method of claim 22, wherein the output control unit The negative polarity detector detects a horizontal synchronization signal pattern and outputs +2 when a control signal input from the segment decoder indicates an initial state, and +1 when a reliability is equal to or greater than a predetermined value. Horizontal sync signal detection device. The method of claim 16, wherein the segment integrator is An adder for adding a value before 832 symbols fed back to the output data of the segment correlation unit; And a delay unit which delays the output of the adder for 832 symbols and feeds back to the adder. 28. The apparatus of claim 27, wherein the segment integrator is And a limiter is provided between the adder and the delayer to limit the output of the adder if the output exceeds the limit of a predetermined precision. 28. The apparatus of claim 27, wherein the retarder Two flip-flops that align the timing of input and output data by delaying input data in symbol units, And a 830 symbol delay unit for delaying 830 symbols. The method of claim 16, wherein the segment decoder A 832 counter for outputting a logic signal when the counted value is a predetermined value and the counted value is preset; A reliability checker which is enabled only when a signal indicating a horizontal synchronization period is output from the segment slicer, and checks the reliability of the output of the 832 counter and outputs a control signal only when the reliability is greater than or equal to a predetermined value; And a horizontal synchronizing signal generator for generating a horizontal synchronizing signal at a specific count value of the 832 counter when the control signal output from the reliability inspecting unit indicates that the reliability is greater than or equal to a predetermined value.