KR19990081249A - Solid state imaging device - Google Patents

Abstract

The present invention relates to a solid-state image pickup device, in order to mitigate the signal charge MERGE suddenly made from the end of the HCCD region to the FD region by forming the butterfly of the last transfer gate of the HCCD region larger than the other transfer gates In the structure of a solid-state imaging device in which a light conversion conversion region, a vertical charge transfer region, a single charge transfer region, and a signal detection unit are formed on a semiconductor substrate, a plurality of arrays are arranged on the semiconductor substrate of the horizontal transfer charge region, but have different ends. A transfer gate formed to have a larger width than the stage, an output gate formed to be positioned after the last transfer gate among the transfer gates, and a floating diffusion region formed after the output gate, and including an HCCD region. Since the signal charge transferred through the MERGE from the end of the HCCD region to the FD region is gentle In this area, the potential profile can be prevented from reverse inclination, thereby increasing the charge transfer efficiency to reproduce a clear image.

Description

Solid state imaging device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid state image pickup device, and more particularly, to a solid state image pickup device having an improved structure of an end portion of a horizontal charge coupled device (hereinafter referred to as HCCD) region.

1 shows a plan view of a general solid state image pickup device.

A solid state image pickup device is an apparatus for generating electrons by light, arranging charge-coupled devices in a directional manner, and detecting signal charges transmitted thereby. In other words, it is a device that transfers charges excited by light through a directional CCD array and then amplifies this signal to obtain a predetermined output signal. As such, the solid state image pickup device, a device for converting an image signal into an electrical signal, has a vertical charge transfer (Vertical) for receiving a photo diode (PD), a photoelectric conversion region, and signal charges generated and accumulated in the PD. A pixel array unit (or PD array unit) arranged in unit cells configured as a charge coupled device (hereinafter, referred to as a VCCD) region, a horizontal charge coupled device, and a signal detection unit are included. The signal charges accumulated in the PD are sequentially transferred to the VCCD and the HCCD and output through the signal detection unit.

The operation of a general solid state image pickup device will be briefly described as follows.

When the light focused through the microlens reaches the light receiving unit PD, the charge generated by the photoelectric effect accumulates in the potential well under the PD. This collected charge is transferred to the charge transfer path VCCD by the change of potential caused by the voltage across the transfer gate. The transmitted charges move in sequence through the VCCD, and then move along a wider path called HCCD, which eventually collects in the floating diffusion region (FD). The charge collected in the FD region is sensed by using the point that the potential of the FD region changes up and down according to the amount of charge, and then is discharged to the drain.

2 and 3 schematically show the termination portion and the FD region portion of the HCCD region in the solid state image pickup device according to the prior art, FIG. 2 is a plan view, and FIG. 3 is along the cut line II of FIG. 2. It is sectional drawing shown.

The "HCCD region", the "FD region" and the "drain region" are electrically connected by BCCD (BCCD) which is an n-type impurity region, and the output gate OG is located between the HCCD region and the FD region, and the FD The reset gate RG is positioned in the drain region close to the region.

In the substrate, a p-type well (p-WELL) is formed in an n-type semiconductor substrate (N-sub), and BCCD doped with n-type impurities is formed in a p-type well (p-WELL).

In the HCCD region, a first transfer gate G1 and a second transfer gate G2 are alternately arranged for horizontal charge transfer, and a first transfer gate (hereinafter, referred to as a last transfer gate) positioned at an end of the HCCD region. Next, there is an output gate OG formed of the same material as the material on which the second transfer gate is formed. The lower portion of the substrate corresponding to the lower portion of the second transfer gate G2 is doped with a low concentration of p-type impurities (indicated by a portion indicated by "p-" in the drawing) to enable two-phase clocking.

In the prior art shown in the drawings, only the first polysilicon layer and the second polysilicon layer are used to form each transfer gate (for example, the first transfer gate is formed using the first polysilicon layer, and the second The transfer gate is formed using a second polysilicon layer). At this time, the output gate (OG) is formed using a second polysilicon layer. The width is doubled as compared with the first and second transfer gates.

The FD region forms an N + region for contact with BCCD, and the N + region is connected to the sensing AMP. The signal charge is connected to an external connection terminal while changing the potential of the N + region of the FD region and detected as an output signal.

In the drain region, a reset gate RG and a reset drain RD, which is another N + region, are formed to allow the charge of the FD region to be discharged to the outside. A reset drain electrode (not shown) is connected to the reset drain RD, and an electrode pulse is applied thereon to discharge the charge transferred to the drain region to the outside.

4, the charge transfer operation in the conventional solid state image pickup device will be described.

As described above, the signal charge generated in the PD is moved to the VCCD, and also to the end of the VCCD with the HCCD by VCCD CLOCKING in the VCCDD, and then to the HCCD, and also to the HCCD end point by the HCCD CLOCKING in the HCCD. The movement of signal charge at the HCCD termination is described as follows.

When t = t1, a voltage signal is applied to each gate so that the voltage pulses of (Hφ1, Hφ2, φOG) become (5V, 0V, 2V). The dislocation profile at each position is the same as the dislocation profile shown at t = t1 in FIG. Therefore, the signal charges at the last portion of the HCCD region are transferred to the portion having the potential barrier formed by the output gate, i.e., the lower substrate of the last gate electrode of the HCCD region by the newly formed potential profile.

When t = t2, a voltage signal is applied to each gate so that the voltage pulses of (Hφ1, Hφ2, φRG) become (0V, 5V, 2V). The dislocation profile at each position is the same as the dislocation profile shown at t = t2 in FIG. Thus, the newly formed potential profile moves the signal charges on the lower substrate of the last gate electrode of the HCCD region to the FD region beyond the barrier of the potential potential of the output gate OG.

The signal charges beyond the output gate OG to the FD region are converted into voltage by the capacitance of the FD region, and the change of the voltage is transferred to the sensing AMP and is represented as a result of the final output.

As can be seen from FIG. 2 in the related art described above, the signal charge transferred through the HCCD region is rapidly generated from the end of the HCCD region to the FD region. Thus, as shown in FIG. 5, the potential profile at the relatively wide output gate forms a reverse slope, thereby making it difficult to transfer charges from the HCCD region to the FD region. As a result, a problem arises in that it is possible to reduce the horizontal charge transfer rate to reproduce an inconsistent image. This problem is even worse, especially when the charge is small.

An object of the present invention is to make the butterfly of the last transfer gate of the HCCD region larger than the other transfer gates to mitigate the MERGE of the signal charge which is rapidly generated from the end of the HCCD region to the FD region, thereby reducing the adversity in the potential profile. It is to prevent the formation of yarn.

The solid-state imaging device of the present invention for this purpose is a solid-state imaging device in which a light conversion conversion region, a vertical charge transfer region, a single charge transfer region and a signal detector are formed on the semiconductor substrate, a plurality of solid state image pickup devices on the semiconductor substrate of the horizontal transfer charge region A plurality of transfer gates arranged so as to have a width greater than that of the other stage, an output gate formed next to the last transfer gate among the transfer gates, and a floating diffusion region formed after the output gate It includes.

1 is a general plan view of a solid state imaging device

2 is a schematic plan view of HCCD and FD portions of a solid state image pickup device according to the related art.

3 is a cross-sectional view taken along the line II of FIG. 2.

4 is a potential profile with time in the solid state image pickup device shown in FIG.

FIG. 5 is a view schematically showing reverse slope of a potential profile in a conventional solid state image pickup device. FIG.

6 is a schematic plan view of HCCD and FD portions of the solid state image pickup device according to the present invention;

7 is a cross-sectional view taken along the line II-II of FIG. 6.

8 is a potential profile with time in the solid state image pickup device shown in FIG.

6 and 7 are views for explaining a solid state image pickup device according to the present invention. The terminal and the FD region of the HCCD region are schematically illustrated. FIG. 6 is a plan view, and FIG. 7 is a sectional view taken along the line II-II of FIG. Sectional view along the line. Compared with the conventional technique described above, the butterfly of the last transfer gate of the HCCD region is large, and the low concentration n-type impurity region is separately provided in a part of the lower substrate of the multi-film transfer gate.

The "HCCD region", the "FD region" and the "drain region" are electrically connected by BCCD (BCCD) which is an n-type impurity region, and the output gate OG is located between the HCCD region and the FD region, and the FD The reset gate RG is positioned in the drain region close to the region. In the substrate, a p-type well (p-WELL) is formed in an n-type semiconductor substrate (N-sub), and BCCD doped with n-type impurities is formed in a p-type well (p-WELL).

In the HCCD region, the first transfer gate G1 and the second transfer gate G2 are alternately arranged for horizontal charge transfer, and the last transfer gate is positioned at the end thereof. The last transmission gate is wider than the other transmission gates. The last stage transfer gate may be formed twice as wide as other transfer gates. Therefore, by reducing the abrupt MERGE of signal charges, it is possible to prevent the reverse slope of the potential profile. At this time, the potential profile under the last transfer gate may be wider and smoother than the potential profile of other transfer gates in the HCCD region. However, as shown in the drawing, when the low concentration n-type impurity region 65 is formed in the lower substrate of the last transfer gate toward the FD region, a potential profile in which one step is entered may be formed in the lower transfer gate. Therefore, it is possible to reduce the problem of dislocation profiles caused by forming the last transfer gate wide.

After the last transfer gate, there is an output gate OG formed of the same material as the material forming the second transfer gate. In this case, the width of the output gate may be smaller than that of the related art in consideration of the wider last transfer gate. The lower portion of the substrate corresponding to the lower portion of the second transfer gate G2 is doped with a low concentration of p-type impurities (indicated by a portion indicated by "p-" in the drawing) to enable two-phase clocking.

In the prior art shown in the drawings, only the first polysilicon layer and the second polysilicon layer are used to form each transfer gate (for example, the first transfer gate is formed using the first polysilicon layer, and the second The transfer gate is formed using a second polysilicon layer). At this time, the output gate (OG) is formed using a second polysilicon layer. The width is doubled as compared with the first and second transfer gates.

The FD region forms an N + region for contact with BCCD, and the N + region is connected to the sensing AMP. The signal charge is connected to an external connection terminal while changing the potential of the N + region of the FD region and detected as an output signal.

In the drain region, a reset gate RG and a reset drain RD, which is another N + region, are formed to allow the charge of the FD region to be discharged to the outside. A reset drain electrode (not shown) is connected to the reset drain RD, and an electrode pulse is applied thereon to discharge the charge transferred to the drain region to the outside.

The charge transfer in the solid state image pickup device of the present invention will be described with reference to FIG. 8, which shows the potential profile with time in the solid state image pickup device shown in FIG.

As described above, the signal charge generated in the PD is moved to the VCCD, and also to the end of the VCCD with the HCCD by VCCD CLOCKING in the VCCDD, and then to the HCCD, and also to the HCCD end point by the HCCD CLOCKING in the HCCD. The movement of signal charge at the HCCD termination is described as follows.

When t = t1, a voltage signal is applied to each gate so that the voltage pulses of (Hφ1, Hφ2, φOG) become (5V, 0V, 2V). The dislocation profile at each position is the same as the dislocation profile shown at t = t1 in FIG. Therefore, the signal charges at the last portion of the HCCD region are transferred to the portion having the potential barrier formed by the output gate, i.e., the lower substrate of the last gate electrode of the HCCD region by the newly formed potential profile. Despite the wide formation of the last transfer gate, since the low concentration n-type impurity region 65 is formed at the lower portion thereof, it shows a sequential dislocation profile in which a step is entered and the entire surface is evenly stepped.

When t = t2, a voltage signal is applied to each gate so that the voltage pulses of (Hφ1, Hφ2, φRG) become (0V, 5V, 2V). The dislocation profile at each position is the same as the dislocation profile shown at t = t2 in FIG. Thus, the newly formed potential profile moves the signal charges on the lower substrate of the last gate electrode of the HCCD region to the FD region beyond the barrier of the potential potential of the output gate OG.

The signal charges beyond the output gate OG to the FD region are converted into voltage by the capacitance of the FD region, and the change of the voltage is transferred to the sensing AMP and is represented as a result of the final output.

According to the present invention, since the signal charge transferred through the HCCD region is MERGE smoothly from the end of the HCCD region to the FD region, the reverse profile can be prevented from occurring at this portion. In addition, by adding another potential step at the end of the HCCD, the charge transfer efficiency can be increased to reproduce a clear image.

Claims (4)

In a solid state image pickup device in which a light conversion conversion region, a vertical charge transfer region, a single charge transfer region, and a signal detector are formed on a semiconductor substrate, A plurality of transfer gates arranged on an upper portion of the semiconductor substrate in the horizontal transfer charge region, the last end of which is larger in width than the other end; An output gate formed to be positioned after a last transfer gate among the transfer gates; And a floating diffusion region formed after said output gate. The method according to claim 1, And an n-type impurity region formed in a portion of the semiconductor substrate below the last transfer gate of the transfer gates toward the floating diffusion region. The method according to claim 1, And the width of the last transfer gate is about twice the width of the other transfer gates. The method according to claim 1, And the butterfly of the output gate is not different from the width of the other transfer gates of the horizontal charge transfer region.