KR19990080821A - Capacitor of semiconductor device and method of forming the same - Google Patents

Abstract

A capacitor of a semiconductor device and a method of forming the same are disclosed. The present invention forms a lower electrode on a semiconductor substrate and forms a dielectric film covering the lower electrode with a ferroelectric material. A first conductive material containing a platinum group element on the dielectric film is deposited by physical vapor deposition to form a first upper electrode. A second conductive material not containing a platinum group element is deposited on the first upper electrode by a chemical vapor deposition method or the like to form a second upper electrode. The first upper electrode is formed to have a thickness smaller than that of the second upper electrode, for example, 5% to 40% of the thickness of the second upper electrode.

Description

Capacitor of semiconductor device and method of forming the same

The present invention relates to a semiconductor device, and more particularly, to a capacitor and a method of forming the same.

Ferroelectric material or high-dielectric material such as PZT (PbZrTiO ₃ ) or BST ((Ba, Sr) TiO ₃ ) is applied to a semiconductor device such as a ferroelectric random access memory (FRAM) or a dynamic random access memory Is proposed.

The use of a platinum group metal or a platinum group metal oxide as an electrode material when a ferroelectric material is used as a dielectric film is disclosed in David E. Kotecki, "A review of high dielectric material for DRAM capacitor", Integrated Ferroelectrics, 1997, Vol. 16, 19). According to David's paper, a platinum group or a platinum group oxide has a large work function and a shottky barrier is formed at the interface with the dielectric layer, so that the leakage current of the capacitor can be suppressed.

However, when the plate electrode, which is the upper electrode, is formed of the platinum group metal or the platinum group oxide, the step coverage of the plate electrode along the step of the lower electrode, that is, the storage node, This poor problem arises. That is, platinum group metals such as platinum (pt) and the like are usually formed by sputtering these thin films. At this time, the step coverage is poor at about 30% or less.

Unit cell area according to DRAM generation and characteristics of storage electrode required when using BST DRAM generation Design rule (㎛) Cell area Capacitance ^* (fF / cell) Storage Electrode Height (탆) Aspect ratio ^** 256 megabits (Mbit) 0.25 0.75 25-30 Flatness - 1 Gigabit (Gbit) 0.18 0.25 25 > 0.26 탆 > 1.4 4 Gigabit 0.15 0.11 25 > 0.59 탆 > 5.4

Assuming that the dielectric capacity per unit area of BST is 100 fF / 탆 ²

** Storage electrode height / design rule

On the other hand, according to David's article mentioned above, the storage electrode height as described in Table 1 is required in order to assure the capacitance as the semiconductor device is highly integrated. According to Table 1, a storage electrode having a storage electrode height of 0.26 탆 or more and an aspect ratio of 1.4 or more should be used to implement a DRAM capacitor of 1 gigabit or more. Considering the thickness of the dielectric layer covering the storage electrode, that is, the thickness of the BST of 200 ANGSTROM to 500 ANGSTROM, the aspect ratio of the entire storage electrode and the dielectric layer becomes larger.

Therefore, as shown in FIG. 1, voids may be formed or a defect that a part of the dielectric film is exposed may occur. The occurrence of such defects can occur not only by the above-mentioned sputtering but also by physical vapor deposition such as thermal evaporation or laser beam evaporation.

An attempt to form a platinum group or platinum group metal oxide electrode by chemical vapor deposition (CVD) in order to improve the step coverage defect that occurs when the platinum group or platinum group metal oxide electrode is formed by such physical vapor deposition is proposed . However, in the chemical vapor deposition method, it is difficult to realize a thin film having sufficient electric or physical properties with respect to the ferroelectric material such as BST. For example, the platinum thin film may be deformed during the subsequent heat treatment process after the platinum thin film is formed, so that a step coverage failure such as exposing the lower dielectric film, that is, the BST film, may occur. Further, platinum hexafluoroacetylacetonate (hereinafter referred to as "Pr-HFA") or ruthenium-trimethylheptanedionate (hereinafter referred to as "Ru-TMHD") used for the above chemical vapor deposition The same source cost is high and the deposition efficiency is low and high expense is consumed.

In order to improve defective step coverage of the platinum group or platinum group metal oxide thin film, a method of forming the upper electrode, that is, the plate electrode, with a non-platinum group metal nitride has been proposed. For example, a method of forming a non-platinum group metal nitride such as titanium nitride (TiN), tungsten nitride (WN) or the like as an upper electrode has been proposed. However, when the upper electrode is formed of the non-platinum group metal nitride, the leakage current characteristic is poor (Pierre-Yves Lesaicherre, " G bit scale DRAM stacked capacitor with ECR MOCVD SrTiO ₃ over RIE patterned RuO ₂ / TiN storage node ", Integrated Ferroelectrics, 1995, vol. 11, pp. 81-100).

2 is a graph schematically showing leakage current characteristics of a TiN / BST / Pt thin film structure.

Specifically, the BST film is formed to a thickness of about 400 Å by a sputtering method. The polarity of the applied voltage is based on the voltage applied to the TiN film as the upper electrode. That is, (-) V means that (-) voltage is applied to the upper electrode. In FIG. 2, the leakage current when the (-) voltage is applied is larger than the leakage current when the (+) voltage is applied is 1000 times or more. Due to the characteristics of the leakage current, it can be seen that the TiN / BST / Pt structure is not suitable for the capacitor. This is due to the fact that the work function of TiN is only 2.92 eV, which is less than 5.4 eV of Pt. That is, when the negative voltage is applied, the magnitude of the leakage current is determined by the Schottky barrier interface characteristic at the interface between the upper electrode, that is, the TiN film and the BST film, and when the positive voltage is applied The magnitude of the leakage current is determined by the Schottky barrier interface characteristics at the interface between the lower electrode, that is, the Pt film and the BST film. Therefore, a Schottky barrier is not formed between the TiN film and the BST film more than between the Pt film and the BST film. Accordingly, the magnitude of the leakage current when the (-) voltage is applied is increased.

Disclosure of the Invention Technical Problem [8] The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method of manufacturing a semiconductor device, which is capable of suppressing leakage current and preventing the occurrence of coating defects such as voids and uneven deposition at the time of forming an upper electrode, And a capacitor of a semiconductor device using a dielectric film of a ferroelectric material that can be implemented.

It is another object of the present invention to provide a method of manufacturing a semiconductor device which suppresses leakage current and prevents the occurrence of coating defects such as voids and uneven deposition when forming an upper electrode, The present invention provides a method of forming a capacitor of a semiconductor device using a dielectric film of a ferroelectric material.

1 is a cross-sectional view schematically showing a problem of a conventional capacitor forming method.

2 is a graph schematically showing leakage current characteristics of a TiN / BST / Pt thin film structure.

3 is a cross-sectional view schematically showing a capacitor according to a first embodiment of the present invention.

FIGS. 4 to 10 are cross-sectional views illustrating a method of forming a capacitor according to a second embodiment of the present invention.

11 is a cross-sectional view illustrating a method of forming a capacitor according to a third embodiment of the present invention.

12 is a cross-sectional view illustrating a method of forming a capacitor according to a fourth embodiment of the present invention.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a lower electrode formed on a semiconductor substrate; a dielectric film covering the lower electrode; a first upper portion formed of a first conductive material containing a platinum group element on the dielectric film; And a second upper electrode formed on the first upper electrode and formed of a second conductive material not containing a platinum group element.

The lower electrode is formed of a platinum group metal or a platinum group oxide. The dielectric layer may be formed of Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, or Bi ₄ Ti ₃ O ₁₂ . The first conductive material is a platinum group metal or a platinum group metal oxide. The platinum group metal is platinum, palladium, osmium, ruthenium, or iridium, and the platinum group metal oxide is ruthenium oxide, iridium oxide, or osmium oxide. The second conductive material is a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal suicide. Wherein the non-platinum group metal is a refractory metal such as copper, aluminum, gold, silver, titanium, tantalum or tungsten and the non-platinum group metal nitride is selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, Or tantalum aluminum nitride.

The first upper electrode is formed by a physical vapor deposition method such as a sputtering method, a vacuum deposition method, or a laser beam deposition method. The second upper electrode is formed by an electroplating method, a chemical vapor deposition method, a sol-gel method, or the like. The first upper electrode is thinner than the second upper electrode, for example, 5% to 40% of the thickness of the second upper electrode.

According to another aspect of the present invention, a lower electrode is formed on a semiconductor substrate. The lower electrode is formed of a platinum group metal or a platinum group oxide. A dielectric film covering the lower electrode is formed. The dielectric layer may be formed of Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, or Bi ₄ Ti ₃ O ₁₂ .

A first upper electrode is formed of a first conductive material containing a platinum group element on the dielectric layer. The first conductive material is a platinum group metal or a platinum group metal oxide. The platinum group metal is platinum, palladium, osmium, ruthenium, or iridium, and the platinum group metal oxide is ruthenium oxide, iridium oxide, or osmium oxide. The first upper electrode is formed by a physical vapor deposition method such as a sputtering method, a vacuum deposition method, or a laser beam deposition method.

A second upper electrode is formed on the first upper electrode by a second conductive material not containing a platinum group element. The second conductive material is a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal suicide. Wherein the non-platinum group metal is a refractory metal such as copper, aluminum, gold, silver, titanium, tantalum or tungsten and the metal nitride is selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride or tantalum Aluminum nitride and the like. The second upper electrode is formed by a chemical vapor deposition method, an electroplating method, a sol-gel method, or the like.

The first upper electrode is formed to have a thickness smaller than that of the second upper electrode, for example, 5% to 40% of the thickness of the second upper electrode.

And annealing the resultant having the first upper electrode after the forming the first upper electrode. Forming an insulating film covering the second upper electrode after forming the second upper electrode, and annealing the resultant having the insulating film formed thereon. The annealing is performed by heat treating at a temperature of approximately 400 ° C to 800 ° C. The heat treatment is performed in a nitrogen atmosphere or a nitrogen atmosphere containing oxygen.

And planarizing the second upper electrode after forming the second upper electrode. The planarization is performed by a chemical mechanical polishing method or an etch-back method.

According to the present invention, it is possible to prevent leakage currents such as voids and non-uniform deposition phenomenon when the upper electrode is formed while suppressing a leakage current, thereby achieving a step coverage that overcomes a step according to the aspect ratio of the dielectric film and the lower electrode A capacitor of a semiconductor device using a dielectric film of a ferroelectric material and a method of forming the capacitor can be provided.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the embodiments of the present invention can be modified into various other forms, and the scope of the present invention should not be construed as being limited by the above-described embodiments. The embodiments of the present invention are provided to enable those skilled in the art to more fully understand the present invention. Therefore, the thickness and the like in the drawings are exaggerated in order to emphasize a clearer description, and elements denoted by the same symbols in the drawings denote the same elements. Also, when a film is described as being "on" or in contact with another film or semiconductor substrate, any film may be present in direct contact with the other film or semiconductor substrate, or a third film in between may be present .

3 schematically shows a cross section of a capacitor according to the first embodiment of the present invention.

Specifically, the capacitor according to the first embodiment of the present invention comprises a lower electrode 400, which is a storage electrode, and an upper electrode, which is a plate electrode composed of a first upper electrode 610 and a second upper electrode 650, A dielectric layer 500 is formed on the interface between the first upper electrode 610 and the lower electrode 400.

The dielectric layer 500 is made of a ferroelectric material or a high-dielectric material. Such as Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, or Bi ₄ Ti ₃ O ₁₂ The entire material or the ferroelectric material. The dielectric layer 500 is formed to have a constant thickness according to a required capacitance. For example, when the dielectric layer 500 is formed using BST, a BST layer is formed to a thickness of about 100 to 500 ANGSTROM to be used as the dielectric layer 500. At this time, the BST film is formed by sputtering or chemical vapor deposition.

The lower electrode 400 is formed of a platinum group metal or a platinum group metal oxide suitable for the dielectric layer 500 formed of the high dielectric constant material or the ferroelectric material. For example, the lower electrode 400 may be formed of a platinum group metal such as platinum (Pt), palladium (Pd), osmium (Os), ruthenium (Ru), or iridium (Ir), or may be formed of ruthenium oxide (RuO ₂ ) (IrO ₂ ), osmium oxide (OsO ₂ ), and the like.

The first upper electrode 610 is made of a first conductive material containing a platinum group element. For example, a platinum group metal such as platinum, palladium, osmium, ruthenium or iridium, or a platinum group metal oxide such as ruthenium oxide, iridium oxide or osmium oxide. The first upper electrode 610 is formed by a physical vapor deposition method. For example, sputtering, thermal evaporation, laser beam evaporation, or the like.

Generally, when a platinum group metal or a platinum group metal oxide is deposited by physical vapor deposition, voids or coating defects may occur as the thickness of a thin film formed becomes thicker. That is, if the thickness of the thin film is increased to some extent, the step coverage becomes poor, which is a degree of covering the step of the lower electrode 400 or the dielectric film 500 at the lower part. However, if the thickness of the thin film is thinner than a certain thickness, the occurrence of voids or coating defects can be suppressed. That is, the thin film formed by physical vapor deposition exhibits a high step coverage within a certain thickness range.

Using the thin film deposition characteristics, the first upper electrode 610 is formed by forming a thin film within a thickness range in which voids or coating defects do not occur. On the other hand, the thin film of the platinum group metal or the platinum group metal oxide formed by the physical vapor deposition method has excellent electrical characteristics. Accordingly, by forming the thin film as described above, it is possible to realize the first upper electrode 610 having the excellent electrical characteristics and preventing the deterioration of the step coverage.

The thickness of the first upper electrode 610 formed as described above may vary depending on the step of the lower dielectric layer 500 or the lower electrode 400 or may vary depending on the width of the lower electrode 400, 2 upper electrode (650). For example, about 5% to 40% of the thickness of the second upper electrode 650. Preferably about 20% of the thickness of the second upper electrode 650. That is, if the second upper electrode 650 is formed to a thickness of about 1000 Å to 5000 Å, the thickness of the first upper electrode 610 is about 50 Å to 2000 Å. Preferably about 200 Å or less. As described above, the first upper electrode 610 formed to have such a small thickness can be prevented from defects such as voids or coating defects, so that excellent step coverage can be realized.

The second upper electrode 650 is formed so as to cover the first upper electrode 610 with a total thickness of the first upper electrode 610 and the upper electrode thickness of the capacitor required. That is, as described above, the first upper electrode 610 does not satisfy the required capacitor upper electrode thickness because the first upper electrode 610 is formed to a thickness small enough to prevent occurrence of voids or coating defects. Accordingly, the second upper electrode 650 is formed to have a predetermined thickness on the first upper electrode 610 to satisfy the required upper electrode thickness. For example, to a thickness of about 1000 to 5000 ANGSTROM. In order to overcome the step difference of the first upper electrode 610, the second upper electrode 650 is formed in such a manner that excellent step coverage can be obtained. That is, the second upper electrode 650 is formed by a chemical vapor deposition method or the like with a second conductive material not containing a platinum group element. The second upper electrode 650 may be formed by filling the valleys between the first upper electrodes 610 using an electroplating method or a sol-gel method in addition to the chemical vapor deposition method have.

As the second conductive material, a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal suicide is used. For example, a non-platinum group metal having heat resistance characteristics such as copper (Cu), aluminum (Al), gold (Au), silver (Ag), titanium (Ti), tantalum (Ta) or tungsten (W) (TiN), tantalum nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN), or tantalum aluminum And a non-platinum group metal nitride such as nitride (TaAlN).

Furthermore, a source material such as titanium tetrachloride (TiCl ₄ ) is used to form the thin film by depositing the second conductive material by a chemical vapor deposition method. Since such a source material is not a noble metal, a lower cost is required compared with a platinum group metal or the like. Therefore, cost reduction can be realized.

FIGS. 4 and 5 are cross-sectional views illustrating a method of forming a capacitor according to a second embodiment of the present invention.

4 schematically shows the step of forming the first insulating film pattern 200 on the semiconductor substrate 100. As shown in FIG.

Specifically, a bit line 250 or gates 210 and 230 are formed after the device isolation layer 150 is formed on the semiconductor substrate 100. Thereafter, a first insulating film for insulating the bit line 250 or the gates 210 and 230 is formed. The first insulating layer is patterned to form a first insulating layer pattern 200 having a contact hole 270 for exposing the semiconductor substrate 100.

5 schematically illustrates the step of forming a plug 310 that fills the contact hole 270. Referring to FIG.

Specifically, a first conductive layer, for example, a doped polycrystalline silicon layer, a metal layer, or a metal silicide layer that covers the first insulating film pattern 200 is formed. At this time, the first conductive layer has a thickness enough to fill the contact hole 270. Next, the first conductive layer is planarized until the surface of the first insulating layer pattern 200 is exposed by an etch back or a chemical mechanical polishing method to fill the contact hole 270. Then, (310).

FIG. 6 schematically shows the step of forming the lower electrode 400 on the plug 310.

A metal nitride layer such as a titanium nitride layer, a tungsten nitride layer, a titanium silicon nitride layer, or a tantalum silicon nitride layer, or a tungsten silicide (WSi) layer or the like is formed on the resultant product on which the plug 310 is formed. A silicide layer or the like is formed. The second conductive layer is formed by a sputtering method or the like.

A third conductive layer is formed on the second conductive layer. The third conductive layer is formed of a platinum group metal or a platinum group metal oxide in consideration of the dielectric layer 500 to be formed later. For example, platinum is sputtered under a pressure of about 1 mtorr to 10 mtorr in an argon (Ar) atmosphere, a power density of about 0.1 W / cm 2 to about 10 W / cm 2 and a semiconductor substrate temperature of about room temperature to about 500 ° C Platinum layer is formed.

Next, the third conductive layer and the second conductive layer are patterned to form a lower electrode 400 and a barrier layer 350. At this time, the patterning is performed by forming a photoresist pattern or an oxide pattern on the third conductive layer and using it as an etch mask. For example, the patterning is performed by etching a part of the third conductive layer exposed by the etching mask using a mixed gas of argon, chlorine gas (Cl ₂ ), or oxygen gas (O ₂ ) as a reaction gas. At this time, the etching may be performed by a magnetron enhanced reactive ion etching method. Thus, the third conductive layer is selectively etched to form the lower electrode 400. Next, the second conductive layer is sequentially etched to form a barrier layer 350. The barrier layer 350 suppresses mutual transfer between the lower electrode 400 and the plug 310 at the interface between the lower electrode 400 and the plug 310.

7 schematically shows the step of forming a dielectric film 500 covering the lower electrode 400. In FIG.

Specifically, a dielectric film 500 is formed on the lower electrode 400 by using a physical vapor deposition method such as a chemical vapor deposition method or a sputtering method. The dielectric layer 500 is made of a high-dielectric material or a ferroelectric material. Such as Ta ₂ O ₅ , SrTiO ₃ , (Ba, Sr) TiO ₃ , PbZrTiO ₃ , SrBi ₂ Ta ₂ O ₉ , (Pb, La) (Zr, Ti) O _3, or Bi ₄ Ti ₃ O ₁₂ The entire material or the ferroelectric material. The dielectric layer 500 is formed to have a constant thickness according to a required capacitance. For example, when the dielectric layer 500 is formed using BST, a BST layer is formed to a thickness of about 100 to 500 ANGSTROM to be used as the dielectric layer 500.

Here, a method using the sputtering method will be described as an example. A sputtering process was performed using a sintered body target having a Ba: Ti: Sr ratio of 0.5: 0.5: 1, using a mixed gas of argon gas and oxygen gas under a pressure of 1 mtorr to 10 mtorr as a sputtering gas BST thin film is formed. At this time, the semiconductor substrate is maintained at a temperature of about room temperature to about 600 ° C.

On the other hand, a BST thin film can be formed by a chemical vapor deposition method. For example, by using an organic gas based on Ba (TMHD) ₂ , Sr (TMHD) ₂ and Ti (TMHD) ₂ and an oxidizing gas such as oxygen gas and nitrogen monoxide gas (N ₂ O) A BST thin film can be formed under the conditions of a semiconductor substrate temperature of about 600 DEG C and a pressure of about 1 torr to 10 torr. When the aspect ratio of the lower electrode 400 is greater than 1, it is preferable to form the BST thin film by chemical vapor deposition because the step coverage should be excellent.

8 schematically shows the step of forming the first upper electrode 610 on the dielectric film 500. [

Specifically, a first upper electrode 610 is formed on the dielectric layer 500 with a first conductive material containing a platinum group element. As the first conductive material, a platinum group metal such as platinum, palladium, osmium, ruthenium, or iridium, or a platinum group metal oxide such as ruthenium oxide, iridium oxide, or osmium oxide may be used. The first upper electrode 610 is formed using a physical vapor deposition method such as a sputtering method using the first conductive material. That is, the first upper electrode 610 may be formed by a thermal vacuum deposition method, a laser beam deposition method, or the like in addition to the sputtering method.

A case where the first upper electrode 610 is formed by a sputtering method is as follows. Such as platinum, palladium, osmium, ruthenium or iridium, under conditions of a pressure of about 1 mtorr to 10 mtorr, a power density of 0.1 W / cm2 to 10 W / cm2 and a semiconductor substrate temperature of about room temperature to about 500 angstrom, A platinum group metal is sputtered to form a thin film and used as the first upper electrode 610. Or a temperature condition of about room temperature to 200 ° C, argon gas and oxygen gas at a ratio of about 12: 8 sccm (standard cubic centimeter per minute), IrO ₂ or RuO ₂ is deposited at a power of 0.3 to 1.0 kW And is used as the first upper electrode 610. At this time, the thin film formed by the sputtering method can impart excellent electrical characteristics to the capacitor.

In general, when a platinum group metal or a platinum group metal oxide is deposited by sputtering or the like, voids or coating defects may occur as the thickness of the thin film becomes thicker. That is, when the thickness of the thin film is increased to some extent, the step coverage becomes poor, which is the degree of covering the step of the lower electrode 400 or the dielectric film 500 at the lower part. However, when the thickness of the thin film is thinner than a certain thickness, the occurrence of voids or coating defects is suppressed. That is, the thin film formed by the physical vapor deposition method exhibits high step coverage within a certain thickness range.

Using the thin film deposition characteristics, the first upper electrode 610 is formed by forming a thin film within a thickness range in which voids or coating defects do not occur. On the other hand, the thin film of the platinum group metal or the platinum group metal oxide formed by the physical vapor deposition method has excellent electrical characteristics. That is, since the work function of the thin film of the platinum group metal or the platinum group metal oxide is as high as about 5.4 eV in the case of the platinum thin film, the Schottky barrier is formed at the interface between the dielectric film 500 and the first upper electrode 610, It is possible to give excellent electrical characteristics such as suppressing leakage current to the formed capacitor. By forming the thin film as described above, the first upper electrode 610 having excellent electrical characteristics can be realized, which prevents the step coverage from being deteriorated.

The thickness of the first upper electrode 610 formed as described above may vary depending on the step of the lower dielectric layer 500 or the lower electrode 400 or may vary depending on the width between the lower electrodes 400, (650 in FIG. 3) to be formed in the second upper electrode (see FIG. 3). For example, about 5% to 40% of the thickness of the second upper electrode 650. Preferably about 20% of the thickness of the second upper electrode 650. That is, if the second upper electrode 650 is formed to a thickness of about 1000 Å to 5000 Å, the thickness of the first upper electrode 610 is about 50 Å to 2000 Å. Preferably about 200 Å or less. As described above, the first upper electrode 610 formed to have such a small thickness can be prevented from defects such as voids or coating defects, so that excellent step coverage can be realized.

FIG. 9 schematically shows the step of annealing the resultant formed with the first upper electrode 610.

Specifically, the first upper electrode 610 is formed of a first conductive material containing a platinum group element as described above, and annealing is performed. This annealing process is performed to improve the interfacial characteristics of the first upper electrode 610 and the dielectric film 500. For example, a mixed gas containing approximately 1% to 10% of oxygen gas is introduced into nitrogen gas (N ₂ ) or nitrogen gas as an atmosphere, and heat treatment is performed at a temperature of approximately 400 ° C to 800 ° C for approximately 1 minute to 60 minutes The annealing process is performed.

10 schematically shows the step of forming a second upper electrode 650 on the first upper electrode 610. FIG.

Specifically, the second upper electrode 650, which covers the first upper electrode 610 with a thickness that is appropriate for the total thickness of the first upper electrode 610 and the upper electrode thickness of the capacitor required, is formed. That is, as described above, the first upper electrode 610 does not satisfy the required capacitor upper electrode thickness because the first upper electrode 610 is formed to a thickness small enough to prevent occurrence of voids or coating defects. Accordingly, the second upper electrode 650 is formed to have a predetermined thickness on the first upper electrode 610 to satisfy the required upper electrode thickness. For example, to a thickness of about 1000 to 5000 ANGSTROM. Furthermore, the second upper electrode 650 can be formed to a thickness that fills all the spaces between the lower electrodes 400, thereby realizing a capacitor in which the lower electrode 400 is completely filled with the conductor.

The second upper electrode 650 is formed in such a manner that excellent step coverage can be obtained in order to overcome the stepped portion of the first upper electrode 610. For example, a second conductive material not containing a platinum group element is deposited by a chemical vapor deposition method, an electroplating method, a sol-gel method, or the like to form a second upper electrode 650.

As the second conductive material, a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal suicide is used. Platinum group metals such as tungsten suicide (WSi) or titanium silicide (TiSi), or titanium nitride (TiN), which have heat resistant properties such as copper, aluminum, gold, silver, titanium, tantalum or tungsten, Platinum group metal nitrides such as tungsten nitride (WN), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), titanium aluminum nitride (TiAlN) or tantalum aluminum nitride (TaAlN)

An example of the case where the above-mentioned second conductive material is deposited by a chemical vapor deposition method is as follows. For example, a titanium nitride thin film is formed by chemical vapor deposition at a temperature of about 700 ° C using titanium tetrachloride (TiCl ₄ ) or Ti [N (CH ₂ CH ₃ )] and ammonia gas (NH ₃ ) . The tungsten silicide thin film is formed by chemical vapor deposition at about 400 ° C. using tungsten hexafluoride gas (WF ₆ ) and silane gas (SiH ₄ ). In the case of a tungsten film, a chemical vapor deposition method is performed at a temperature of about 300 ° C to 500 ° C using hexafluorosilicate gas and hydrogen gas (H ₂ ). In the case of a copper film, chemical vapor deposition is performed at a temperature of about 350 ° C. using Cu (HFA) ₂ and hydrogen gas.

The source material used for forming the thin film by depositing the second conductive material by a chemical vapor deposition method, for example, titanium tetrachloride, tungsten hexafluoride gas, or ammonia gas (NH ₃ ) This is cheap. Therefore, the total cost can be reduced. The thin film made of the second conductive material formed by the chemical vapor deposition method exhibits excellent step coverage compared to the platinum group metal or platinum group metal oxide thin film. The second upper electrode 650 may be formed by an electroplating method, a sol-gel method, or the like in addition to the case where the second upper electrode 650 is formed using the chemical vapor deposition method as described above.

The second upper electrode 650 is formed to form the upper electrode of the capacitor including the first upper electrode 610 and the second upper electrode 650, as described above. After forming the second insulating film covering the upper electrode, a metal wiring or the like is formed.

11 is a cross-sectional view illustrating a method of forming a capacitor according to a third embodiment of the present invention, and schematically shows a step of forming a second insulating layer 700 and then annealing.

The third embodiment differs from the second embodiment in that the annealing step performed to improve the interfacial characteristics of the first upper electrode 610 and the dielectric film 500 is not performed before forming the second upper electrode 650 After the second insulating film 700 covering the second upper electrode 650 is formed. In the third embodiment, the same reference numerals as those in the second embodiment denote the same elements.

Specifically, the annealing step described with reference to FIG. 9 is performed after forming the second insulating film 700 covering the second upper electrode 650 in the second embodiment. The second insulating layer 700 may be formed of silicon oxide, undoped silicon glass, borophosphosilicate glass (BPSG), spin on glass (SOG), phosphosilicate glass (PSG), silicon nitride, aluminum oxide, . The annealing is performed by heat-treating the substrate at a temperature of about 400 ° C to 800 ° C for about 1 minute to 60 minutes using nitrogen gas or nitrogen gas containing 1% to 10% oxygen gas as an atmosphere.

12 schematically shows a step of planarizing the second upper electrode 650 in a sectional view shown to explain a method of forming a capacitor according to a fourth embodiment of the present invention.

The fourth embodiment is different from the second embodiment in that the second upper electrode 650 is formed by a chemical vapor deposition method and then the second upper electrode 650 is planarized for a subsequent process. In the fourth embodiment, the same reference numerals as those in the second embodiment denote the same elements.

Specifically, after the second conductive material is deposited to form the second upper electrode 650, the surface of the second upper electrode 650 is etched back or chemically mechanically polished Planarize. Next, a second insulating film 700 covering the second upper electrode 650a thus planarized is formed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention.

According to the present invention, by forming the first upper electrode with the first conductive material containing a platinum group element, excellent electrical characteristics at the interface between the dielectric film and the first upper electrode can be realized. That is, since the first conductive material containing the platinum group element has a high work function, a Schottky barrier is formed at the interface between the first upper electrode and the dielectric layer to suppress the generation of leakage current.

The first upper electrode is deposited to a thin thickness. As a result, occurrence of voids or uneven coating defects can be suppressed. Thus, deterioration of the capacitance due to deterioration of step coverage of the upper electrode can be prevented.

Further, after the first upper electrode is formed thin, the second upper electrode is formed of a second conductive material containing no platinum group element so as to realize good step coverage. Therefore, the step coverage of the upper electrode composed of the first upper electrode and the second upper electrode is greatly improved.

Moreover, the second conductive material can be supplied at a lower cost than the first conductive material, and most of the total upper electrode thickness is satisfied by the thickness of the second upper electrode. Therefore, the cost can be reduced compared with the case of forming the upper electrode only with the first conductive material containing the platinum group element.

Claims (29)

A lower electrode formed on a semiconductor substrate; A dielectric layer covering the lower electrode; A first upper electrode formed of a first conductive material containing a platinum group element on the dielectric layer; And And a second upper electrode formed on the first upper electrode and formed of a second conductive material not containing a platinum group element. The capacitor of claim 1, wherein the lower electrode is formed of a platinum group metal or a platinum group oxide. The method of claim 1, wherein the dielectric layer is _{Ta 2 O 5, SrTiO 3,} (Ba, Sr) TiO 3, PbZrTiO 3, SrBi 2 Ta 2 O 9, (Pb, La) (Zr, Ti) O 3 and Bi ₄ Ti ₃ O _12, and the like. The capacitor of claim 1, wherein the first conductive material is a platinum group metal or a platinum group metal oxide. The method of claim 2 or 4, wherein the platinum group metal is any one selected from the group consisting of platinum, palladium, osmium, ruthenium, and iridium, and the platinum group metal oxide is at least one selected from the group consisting of ruthenium oxide, iridium oxide, And a capacitor connected in series with the capacitor. 2. The capacitor of claim 1, wherein the second conductive material is a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal suicide. The capacitor of claim 6, wherein the non-platinum group metal is any one selected from the group consisting of copper, aluminum, gold, silver, titanium, tantalum, and tungsten. 7. The semiconductor device according to claim 6, wherein the non-platinum group metal nitride is any one selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride and tantalum aluminum nitride. Of the capacitor. The capacitor of claim 1, wherein the first upper electrode is thinner than the second upper electrode. 10. The capacitor of claim 9, wherein the first upper electrode has a thickness of 5% to 40% of the thickness of the second upper electrode. Forming a lower electrode on a semiconductor substrate; Forming a dielectric layer covering the lower electrode; Forming a first upper electrode with a first conductive material containing a platinum group element on the dielectric layer; And And forming a second upper electrode on the first upper electrode with a second conductive material not containing a platinum group element. 12. The method of claim 11, wherein the lower electrode is formed of a platinum group metal or a platinum group oxide. 12. The method of claim 11, wherein the dielectric layer is _{Ta 2 O 5, SrTiO 3,} (Ba, Sr) TiO 3, PbZrTiO 3, SrBi 2 Ta 2 O 9, (Pb, La) (Zr, Ti) O 3 and Bi ₄ a capacitor forming a semiconductor device characterized in that is formed of one selected from the group consisting of Ti ₃ O _12. 12. The method of claim 11, wherein the first conductive material is a platinum group metal or a platinum group metal oxide. The method of claim 12 or 14, wherein the platinum group metal is any one selected from the group consisting of platinum, palladium, osmium, ruthenium, and iridium, and the platinum group metal oxide is selected from the group consisting of ruthenium oxide, iridium oxide, Wherein the first conductive film is one selected from the group consisting of silicon oxide and silicon oxide. 12. The method of claim 11, wherein the second conductive material is a non-platinum group metal, a non-platinum group metal nitride, or a non-platinum group metal silicide. 17. The method of claim 16, wherein the non-platinum group metal is any one selected from the group consisting of copper, aluminum, gold, silver, titanium, tantalum, and tungsten. 17. The semiconductor device according to claim 16, wherein the non-platinum group metal nitride is any one selected from the group consisting of titanium nitride, tungsten nitride, tantalum nitride, titanium silicon nitride, tantalum silicon nitride, titanium aluminum nitride and tantalum aluminum nitride. / RTI > 12. The method of claim 11, wherein the first upper electrode is formed by physical vapor deposition. 20. The method of claim 19, wherein the physical vapor deposition is any one selected from the group consisting of a sputtering method, a vacuum deposition method, and a laser beam deposition method. 12. The method of claim 11, wherein the second upper electrode is formed by a chemical vapor deposition method, an electroplating method, or a sol-gel method. 12. The method of claim 11, wherein the first upper electrode is formed to be thinner than the second upper electrode. 23. The method of claim 22, wherein the first upper electrode is formed to a thickness of 5% to 40% of the thickness of the second upper electrode. 12. The method of claim 11, wherein after forming the first upper electrode And annealing the resultant having the first upper electrode formed thereon. 12. The method of claim 11, wherein after forming the second upper electrode Forming an interlayer insulating film covering the second upper electrode; And Further comprising the step of annealing the resultant formed with the interlayer insulating film. 26. The method of claim 24 or 25, wherein the annealing is performed by heat treating at a temperature of about 400 < 0 > C to 800 < 0 > C. 27. The method according to claim 26, wherein the heat treatment is performed in a nitrogen atmosphere or a nitrogen atmosphere containing oxygen. 12. The method of claim 11, wherein after forming the second upper electrode Further comprising: planarizing the second upper electrode. ≪ RTI ID = 0.0 > 11. < / RTI > The method according to claim 28, wherein the planarization is performed by a chemical mechanical polishing method or an etch-back method.