KR19990076581A - Electronic anti-theft device and its method - Google Patents

Abstract

The present invention relates to antitheft devices and methods for use with portable electrical or electronic devices, in particular mobile phones or personal computers.

The invention includes a first data store in which an encrypted code is stored in an electrical device, and a removable second data store in a removable rechargeable battery unit comprising a battery and a memory store. The security code is transmitted to the first data store when the battery unit is inserted. If the code is recognized as a valid authentication code, the device can be enabled and operated in a conventional manner. Otherwise, the device will be electrically disabled.

When recharging (from a charger with means for resupplying a stable code) the electrical device cannot be used unless the battery unit receives the refreshed security code, so the device is useless when the battery is exhausted.

Preferably the charger is modified such that a valid security code is transmitted to the battery unit at each recharge.

Description

Electronic anti-theft device and its method

In today's society, crime is unfortunately increasing. Thieves in particular are a daily problem. Thieves often steal expensive portable electronic devices such as personal portable computers, video cameras, and mobile phones. These devices can be expensive to replace, and in the case of personal portable computers, theft of these devices can mean potential exposure of highly confidential material stored on the computer.

Summary of the Invention

It is an object of the present invention to overcome the above mentioned problems by providing an anti-theft system comprising a method and apparatus suitable for use with the above mentioned types of electronic devices, although it is understood that they can be used with other types of electronic devices.

DE-A1-3803357 (Philips) discloses a security system for use with portable electronic equipment. The system consists of a battery charger selected for use with the equipment. The charger has a code transmitter and a code receiver. If the code received from the charger does not match the code stored in the code receiver, the code receiver deactivates the equipment.

The disclosed system is for use with equipment having a built-in rechargeable battery. A disadvantage of the disclosed conventional system is that it takes considerable time to recharge the battery until the system can be used again when the energy source is depleted. Most of today's mobile electronic devices are equipped with a second rechargeable battery to easily replace the rechargeable battery in case the user runs out of power. The equipment cannot be used with the already mentioned recharger because the battery is not removable.

Another disadvantage of conventional systems is that batteries that are charged using "unauthorized" chargers can be physically removed (disconnected) by an unauthorized person and there is no mechanism to verify the authenticity of a recharged battery. Can be exchanged for

According to a first aspect of the invention there is provided an apparatus for receiving a removable battery unit, said battery unit comprising a rechargeable battery and a memory storage, said device optionally enabling the device upon receipt of a valid authentication code. Or a comparison means for comparing the security code stored in the device with the authentication code provided by the memory store to suppress the function of the device upon receipt of an invalid authentication code.

When enabled, the electronic device will function normally. For example, in the case of a mobile phone, it can be used to make or answer a call. However, if the security code is not an authorized code provided by the battery unit, the electronic device will be disabled. In other words, the device is "jamming" so that it cannot be used for its intended purpose. The inhibition will be performed electronically.

According to another feature of the invention, a first data store for storing a security code (the stored code), means for reading an authentication code, means for comparing the authentication code with the stored code, and when the authentication code is a valid authentication code An electrical or electronic device having means for enabling the operation of the device is provided, said device being used to receive a removable and rechargeable battery unit comprising a battery and a memory reservoir.

Conveniently, the battery is a rechargeable battery having a volatile memory such as random access memory (RAM) or an erasable programmable storage device such as erasable programmable read only memory (EPROM).

Preferably, the authorization code is generated from a code source provided in the battery charger used to recharge the battery and transmitted to the memory during recharging.

Therefore, the device is effectively manufactured for use with the owner's charger, i.e. a battery that is charged with a "certified" charger, and the device cannot be used unless the correct authorization code is resupplied as soon as the battery is discharged.

Since most portable electrical or electronic devices are supplied with one or more removable and rechargeable batteries and a removable battery charger (usually not transported or stored with the device) (to reduce weight and size), the present invention is directed to DE-A1. More robust and more flexible than the already mentioned system disclosed in -3803357.

According to another feature of the invention, there is provided a battery charger for charging a battery, the charger having a primary code source, and said code source for transmitting an authentication security code to a data store in a battery unit while the battery is being recharged. Means for responding to.

Preferably the battery charger supplies the cord during the supply of the current required to recharge the battery. The battery unit and the battery charger may be configured such that any security code still held in the memory store in the battery unit is first erased and a new security code is written to the store in the battery unit at the beginning of the charging cycle. The system has a higher level of security. Similarly, the electrical or electronic device may have means for automatically erasing the code in the memory store if an attempt is made to gain access to the storage in the battery unit. Automatic erasing can be performed by the battery unit or device.

According to another feature of the invention, there is provided a battery unit comprising a rechargeable battery and a data memory storage (eg EPROM) in which an authentication security code is written.

Preferably the authentication security code is sent to the battery unit when the battery is recharged.

Preferably, prior to use, the battery unit is required to deliver a code having a single period more than once and the device is configured to receive the code more than once.

The security code does not allow any identification of the code by the possession of an electronic device comprising the battery unit (including the "primary" code and providing an encrypted form of an authentication code) and the security code (to be protected). To be encrypted.

Conveniently, the circuitry arranged in the battery unit is effective for reading data, the circuit comprising means for identifying a connection of the battery unit to a charger, means for storing and erasing the data when stored, and Means for decoding the data and means for storing the serial data after a predetermined period when the data is provided to the charger.

Preferably the circuitry provided in the battery unit comprises means for writing data into an electrical or electronic device, the data writing means means for identifying a connection of the electronic device to the battery unit, means for reading stored data, the Means for encoding data and means for transmitting the encoded data to the electronic device.

Advantageously the data is used in the form of serial data. And means for reading a second data piece (second portion of the code), means for encoding the data by adding to a sequential data piece generated by a pseudo random number sequence generator, and an authentication code generated sequentially in the electronic device. Means for retransmitting may be provided.

Means may be provided for stopping the transmission until the battery unit is removed from the electronic device.

According to another feature of the invention, there is provided a method of charging a rechargeable battery, characterized in that a security code is transmitted to a memory reservoir in the battery unit.

Embodiments of the present invention will now be described with reference to the accompanying drawings by way of example only.

The present invention relates to an electronic anti-theft device and method thereof, and more particularly to an anti-theft system for use with portable electronic equipment.

1 is an overall block diagram showing the concept of the present invention.

2 is a circuit diagram of a battery charger.

3 is a circuit diagram of a battery unit.

4 is a circuit diagram of an electronic device.

1 schematically illustrates the performance of a task, only to illustrate the underlying principles thereof. It is not the only way to achieve the broad object of the present invention.

The electronic device 24 includes a first data store 26 for storing a code; Means (23) for comparing the stored code with the security code received from the second data store (21); And means for enabling the electronic device 24 when the security code is a valid authentication code, wherein the second data store 21 is housed in a removable and rechargeable battery unit 10. .

1 shows a rechargeable battery unit 10 (described in more detail below with reference to FIG. 3) connected to a battery charger 12 (described in more detail below with reference to FIG. 2) via power lines 12a and 12b. Described). The battery charger 12 is in turn connected to the main power supply across A and B. Data entry means 14, such as a keypad, transmits a coded security signal (authentication code) to a memory reservoir 16 housed inside the battery charger 12. The storage 16 includes electronic memory elements, such as random access memory (RAM) chips (not shown). Therefore, the authentication code (or authentication code generator) is stored in the battery charger 12. The code is transmitted to the storage 21 in the battery unit 10 via a separate data link 18. Alternatively, the authentication code may be transmitted to the battery unit 10 via dedicated connections 12a and 12b.

4 shows a circuit that can be a personal digital computer or a telephone.

The electronic device 24 houses the battery unit 10. This is illustrated by the dashed line surrounding the coupled portable module 25. The battery unit 10 is removable and removable from the module 25.

The embodiment described in more detail below with reference to FIGS. 2-4 uses only 4-bit security with a “random number” of communication. Therefore, it is not as safe as it is required. As would be expected by one skilled in the art, commercial performance may only be slightly more complex physically since it may use 8, 12, or even 16 bit random numbers, otherwise the same will be the same. However, it will provide much higher security.

2 shows how two 4-bit codes from the battery unit to the mobile electronic device 24 are written to the battery unit 10 by the charger 12 as a single 8-bit word. The charger 12 has an oscillator having a resistor 930, a capacitor 32, and a Schmitt inverter 34 (part of IC1). There is also a counter 40 and a shift register 42 that function similarly to a series inverter. This generates a clock signal. Gating means 44 is used to form a serial pulse width modulated data stream at output pin 46.

The master clock oscillator 48 (frequency f) continuously executes the counter 40 and generates a clock. Therefore, the counter Q1 generates a square wave at f / 2. Counter Q5 counts at f / 32 (the remaining stages of counter Q5 are not directly related to the present invention). Hence counter Q5 is alternately high for the first set of sixteen clock pulses and low for the subsequent sixteen set of clock pulses.

Shift register 42 is clocked by counter Q1 (eg, half the master clock speed at f / 2). The parallel input line of the shift register 42 is connected high (for VDD) or low (for VSS) to represent 1 to represent 8-bit data. Therefore, two 4-bit code numbers are used by the battery unit 10 and the electronics 24 are programmed by connecting high or low to parallel input lines. This can be achieved for example with a dip switch (not shown).

The serial / parallel select line of the shift register 42 is connected to the Q5 pin of the counter 40. When Q5 is high, parallel data of the shift register input line is jammed. When Q5 is low, the data is shifted sequentially from QH at f / 2. Therefore, QH remains at the level of input H for 16 master clock periods while counter Q5 is high. When Q5 goes low, 8-bit serial data is pulled low for the next eight block periods. The process is then repeated.

Inverters 50 and 52, "AND " gates 54, 56 and 58, and " OR " gates 60 and 62 may generate the master clock to generate the pulse width modulated serial data stream at f / 2. Q1, Q5) and shift register QH. The pulse length is half of the period of the master clock 48 when the represented data is zero, and 1.5 times the period of the master clock 48 when the data represents one.

When the counter Q5 is high, the inverter 64 and the " AND " gate 66 block data, so that only the data shown in the output 46 is required 8 bits after Q5 goes low. Becomes Therefore, the battery charger 12 generates an 8-bit pulse width modulated data stream representing data programmed over the output pin of the shift register. The data is repeated every 32 cycles of the master clock 48. It requires eight clock cycles and is interrupted for 24 clock cycles (the output data line is low).

The circuit described with reference to FIG. 2 does not require valid data to be received twice. Such changes to the above embodiments are well known to those skilled in the art. The circuit can be easily changed to perform this function. In other words, data validation when receiving two correct data sequence sets is required to enable the device in turn.

3 shows a circuit diagram of the battery unit. The circuit is arranged in the battery unit 10. The circuit comprises two sections: a circuit for reading data from the battery charger 12 and a circuit for writing data to the electronic device 24.

Referring to FIG. 3 in detail, the battery unit 10 is connected to the input line 67 so that the voltage on the input of the inverter 70 rises to VDD. The output of the inverter 70 goes low and generates a positive pulse that resets the counter 74 at the output of the inverter 72. Q14 of counter 74 resets the row to enable the clock through OR gate 76. The serial pulse width modulated data is provided to monostables 78 and 80 (M / S 78 and M / S 80). In a particularly preferred embodiment the timing can be derived from a master clock (not shown). M / S 78 and M / S 80 are triggered by the edges going to the amount of the input waveform. The M / S 80 may retrigger and have a slightly longer period than the incoming data. Therefore, the " Q " of the M / S 80 goes high at the beginning of 8-bit data and remains high for their duration. The Q of the M / S 80 clocks the " D " type latch 82 (D82) to set 80 data input states (connected to Q5 of the counter 74) to " Q " and " AND " Transfer to gate 84. The data pin of " D " type latch 82 and its Q go low until Q5 of counter 74 goes high, and the resulting clock is shifted through AND 84 to shift registers 86 and 88. To prevent it from being sent to. Therefore, illegal data is cut off at power up.

At the beginning of each input data stream (when Q5 of counter 74 is high) of D-type latch 82 Directs the row generating the reset pulse through resistor 90, capacitor 92 and inverter 94 to shift registers 86 and 88. This reset can be edge triggered and will not require a timing component. Until the Q13 of the counter 74 goes high, the derived clock does not reach the shift registers 86 and 88 by the AND gate 84 and no new data is written until the charge lasts for 4096 clock periods. . This delay will be set for a few minutes to improve security.

The monostable 78 has the same period as that of the charger clock. Therefore, the monostable 78 Goes high (the end of the monostable cycle), the state of the "data input" line represents the data sent from the battery charger 12.

The clock derived through AND gate 84 clocks the data from the "data input" into shift registers 86 and 88. Therefore, the shift register is repeatedly reset and loads data when Q13 of the counter 74 is high during charging. The clock is suppressed through the OR gate 76 when Q14 of the counter 74 goes high. In this case the period stops and leaves the final data set sent to shift registers 86 and 88. The battery unit 10 then stays in this state when it is removed from the charger 12 and reconnected (when the sequence is repeated) or when connected to the electronic device 24.

The battery unit has a clock oscillator including a continuously operated inverter 98, a capacitor 100 and a resistor 102. Pseudo random sequence generator PRS is formed of shift register 104 and exclusive OR gate 106 (XOR 106). OR gate 108 and NOR gate 110 prevent the PRS from latching all LOW states. This produces a sequence of (2 ⁿ ) -1 numbers of length n bits (where n is the stage number in the shift register). When the battery unit 10 is disconnected from the electronic device 24, the request of the line is held high through the resistor 112 to close the reset counter 114 and the "D" type latch 116. Hold and enable the clock with a pseudo random sequence generator through AND gate 118.

When the battery unit 10 is connected to the electronic device 24, the request line takes low, releases the reset line, and functions the pseudo random sequence generator clock through the AND gate 118 and the OR gate 120. Suppress The counter 114 is released when clocked and reset through the OR gate 122 and Q9 and Q10 go high when the clock of the counter is disabled via the AND gate 124 and the OR gate 122. Count until Q9 of the counter 114 controls the state of the two-to-one line selector 132 and therefore selects one of the data in the shift register 86 or 88. This includes the first or second four bits for the authentication code. Initially Q9 of counter 114 is low and data from shift register 86 is selected.

As already disclosed the pseudo random sequence (P.R.S) generator stops when its clock is suppressed by the low reset line. The 4-bit full adder 130 generates the sum of 4-bit output data Q0 to Q3 from the 4-bit data selected from the PRS and the shift register 86. Obviously a more secure system will have a larger bit length.

The sum is provided to the four first parallel input lines of the shift register 126 and the remainder is tied low. Data is jammed to register 126 when Q8 of counter 114 is high and shifted from QH (synchronized with the counter's clock) when Q8 goes low. D-type latch 116 and OR gate 128 generate a batch of eight clock pulses following the low transition of counter 114 Q8 to clock the data output and provide a clock pulse to the electronic device. Of course, the data can be transmitted when the pulse width modulated data stream, like the battery charger 12, transmits the data to the battery unit 10 during charging via a single connection and combined with its clock.

When counter 114 Q8 goes low, Q9 goes high and clocks P.R.S. through OR gate 120, the next 4-bit output data is provided to adder 130. Since counter 114 Q9 is now high, the data selector 132 passes the second 4 bits of the authentication code from shift register 88 to the 4-bit full adder 130.

The sum of P.R.S. and the four bits provided by the line selector are again provided to the shift register 126, jammed when the counter 114 Q8 is high and shifted from QH as serial data when low.

Counter 114 Q9 and Q10 are now high and the clock of counter 114 is disabled via AND gate 124 and OR gate 122, until request line goes high and then goes back low ( For example, the battery unit 10 is removed and reconnected to the electronic device 24) to prevent further data transmission. Therefore, the first four bit code data is obtained randomly and added to the corresponding number of clock pulses of the electronic device and the number of four bits transmitted. This in turn involves the sum of the "random" 4-bit numbers according to the sequence generated with the second 4-bit code data and the corresponding clock pulse.

The operation of the electronic device component is now shown in more detail with reference to FIG. 4, wherein the electronic device 24 is a preset authentication code (two numerically programmed in the charger 12 numerically controlled and transmitted to the battery unit 10). Electronic means for reading the same as in the code (in this example), and the serial number added from the battery unit 10 as already disclosed with reference to FIG. 3 by adding the data to the "random number" generated by the PRS generator. Means for comparing the sum with data.

The authorization code is preset by connecting two 8-bit inputs to one line selector 133 high or low. Such data can of course be stored in ROM (not shown) in commercial practice. When the battery unit 10 is connected, a power on reset is generated by the inverter 134, the resistor 136 and the capacitor 138. The first 4 bit code data CODE is selected and added to the output of the pseudo random number sequence generator PRS as already disclosed by the 4 bit full adder ADDER 140. The PRS is of the "D" type latch 142 Is clocked continuously because it resets high through AND gate 144. The oscillator is formed by the resistor 146, the capacitor 148, and the inverter 150. The output of the adder 140 therefore provides a series of four bit words representing the sum of the successive outputs of the first CODE and the PRS.

The serial data and its clock are provided by the battery unit 10 as already disclosed and loaded into the shift register 135. It also clocks the monostable 137, which can be retriggered and has a period twice the incoming clock, resulting in its Goes low during data reception. At the end of 4-bit data, Returns high and clocks the high of D-type latch 152 Q. Therefore, the output of AND gate 152 goes high, enabling the output of the 4-bit comparator via AND gate 158. MS 1 during receipt of sequential data The row at suppresses the comparison through AND gates 154 and 158 so that a correct comparison (which occurs due to data modulation during data loading) does not occur in the invalid state.

The output of the ADDER 140 is compared with the data encoded from the battery unit 10 using a 4-bit size comparator. If the data is the same as the output of the comparator 156 go high and clock the " D " type latch 160 through AND gate 158. Since D1 does not have a changed state, the Q of the " D " type latch 160 remains low (e.g., does not change). The PRS output at electronic device 24 now corresponds to the PRS state in battery unit 10 when encoding a 4-bit code. That is, the two PRSs are synchronized. When the PRS is clocked at some step past the output resulting in an equilibrium of sum and input data, the output of the 4-bit comparator 156 (again) clocks the latch 142 via the inverter 162. Go low. Of latch 142 Goes low to suppress the PRS clock. Q of latch 142 goes high and selects a second CODE word via a line selector. Therefore, the pseudo random sequence generator stops at some point in excess of the number resulting in equilibrium, for example at the same point in time as used by the PRS in the battery unit 10 to encode the second CODE. The second electronic device CODE is selected and therefore the sum predicts the next expected encoded data from the battery unit 10. When a second piece of encoded data is received from the battery unit it is compared with the output of the ADDER 140 (which has already occurred as described) and the two codes are the same or if the code provided by the battery unit is an authentication code The comparator 156 output goes high. Hence the latch 160 is clocked and sends a high to Q indicating that the data provided to its D input and received data is now valid and authorizing the operation of the electronic device 25.

If a third 4-bit word is received from the battery unit 10, then the D-type latch 164 has a high clocked at its Q. Latches 146 and 160 are reset through OR gate 166 to prevent authentication. This can only happen if an unauthorized user attempts to conquer the system.

Therefore, two authentication codes are transmitted from the battery charger 12 to the electronic device through the battery unit 10, where both codes are recognized as valid and thus authorized to the device user. Both codes are encrypted to prevent unauthorized users who occupy both the battery unit and the electronic device from querying the link between them to successfully identify the authentication code. The device is therefore valuable to a thief only until the battery is discharged and exhausted. When this happens, if the thief does not have the knowledge of the code, further use will be prevented since battery charging will be associated with the loss of the code stored in the device. Alternatively, the code stored in the storage unit of the battery unit may be erased.

Although the present invention has been described above in accordance with one preferred embodiment of the present invention, various modifications may be made without departing from the spirit of the present invention as defined by the appended claims. It is obvious to those skilled in the art.

Claims (11)

An apparatus for receiving a removable battery unit having a rechargeable battery and a memory reservoir, the apparatus comprising: Comparison means for comparing the security code stored in the device with the authentication code provided by the memory store, and optionally enabling the device upon receipt of a valid authentication code and the function of the device upon receipt of an invalid authentication code. And a means for suppressing the battery unit accommodating device. A first data store for storing code; Means for comparing the stored code with a security code received from a second data store; And means for enabling the electronic device when the security code is a valid authentication code, comprising: And the second data store is supported by or disposed within the removable and rechargeable battery unit. The method according to claim 1 or 2, The security code stored in the second storage device is automatically erased when the battery is exhausted. The method of claim 3, The code is encrypted. Sending a security code from a second data store to a first data store in the electronic device, and comparing the security code with an already stored code, so that the electronic device is authorized to validate the security code. In the electronic anti-theft method that is enabled when And wherein said second data store is disposed in or in a removable and rechargeable battery unit. The method of claim 5, And wherein said security code is transmitted to said device at least once. The method according to claim 5 or 6, And the security code stored in the second storage device is automatically erased when the battery is exhausted. The method of claim 7, wherein The battery unit is located in a battery charger, wherein a new security code is generated by the battery charger. The method of claim 8, And wherein the security code is encrypted. In a modified battery charger, Means for enabling a security code to be written; Means for storing the security code; Means for supplying current to recharge the battery unit in electrical contact with the charger; And And means for transmitting said security code to said battery unit while said battery is being recharged. A battery unit comprising a rechargeable battery and a data store on which a security code is written.