KR19990074912A - Test Vector Generation Circuit for Semiconductor Devices - Google Patents

Abstract

The test vector generation circuit which can improve test efficiency is described. The test vector generation circuit used in the semiconductor device test according to the present invention includes a basic input stage and a plurality of shift registers connected in parallel with the basic input stage so that a desired value can be applied to a test of the semiconductor device during one clock cycle. Thus, a basic input is input in parallel to the shift registers to shorten the test time.

Since it is input in parallel to the flip-flop constituting the test vector generation cycle, the desired value can be applied to the test for one clock cycle, thereby reducing the test time.

Description

Test Vector Generation Circuit for Semiconductor Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test vector generator circuit used in a semiconductor device, and more particularly to a test vector generator circuit capable of improving test efficiency.

As the cost of testing semiconductor circuits increases, the importance of fast and effective test methods is emerging. To increase test effectiveness, test vectors that cover a wide range of defects should be applied. However, in recent high integrated circuits, it is not easy to generate such a test vector. In order to compensate for this, a structural method of a circuit is widely used, and a representative example is a method of manufacturing a scan design using a scan cell. In conventional circuits, memory devices such as flip-flops make circuit testing difficult, so scan cells are used to control the flip-flop directly to the primary input and to monitor the primary output directly. By constructing, a defect can be covered extensively.

However, when building such a scan design, all flip-flops are configured using serial shift registers, so as many times as many clock cycles are needed in the scan chain to input the desired pattern of data. Do. Therefore, there is a disadvantage in that a lot of time is required for the test. In addition, even when a pattern is input to a specific flip-flop, since it is configured as a linear shift, there is a disadvantage in that another flip-flop must be passed unnecessarily.

FIG. 1 is a block diagram schematically illustrating a conventional test vector generation circuit. When a conventional scan cell is used, test data T_DATA for testing is input in series, so that a clock cycle equal to the number of flip-flops is required. Do.

FIG. 2 is a block diagram illustrating a typical test data input circuit, in which data input through a pad is provided as data DATA and test data T_DATA through a demultiplexer DEMUX.

As mentioned, according to the conventional test vector generation circuit, it is difficult to control each state at the basic input, and more states require more patterns and time to reach a specific state.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a test vector generation circuit capable of improving test efficiency.

1 is a block diagram schematically illustrating a conventional test vector generation circuit.

2 is a block diagram illustrating a general test data input circuit.

3 is a block diagram illustrating a test vector generating circuit according to an exemplary embodiment of the present invention.

In order to achieve the above object, a test vector generation circuit according to the present invention includes a basic input stage and a plurality of shift registers connected in parallel with the basic input stage so that a desired value can be applied to a test of a semiconductor device during one clock cycle. do.

Thus, the test time is shortened.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

3 is a block diagram illustrating a test vector generating circuit according to an exemplary embodiment of the present invention.

The test vector generation circuit according to the present invention has shift registers, for example flip-flops F / F1 to F / Fn, connected in parallel to the basic input, as shown in FIG.

Data DATA and test data T_DATA are input to the flip-flop input terminal using multiplexers MUX1 to MUXn. By the test mode signal input to the select line of the multiplexer, the test vector generation circuit performs a general function using the data DATA in the normal mode, and applies the test data T_DATA to the desired value in the test mode. Perform the test with).

As described above, since all test data T_DATA is input to the flip-flop in parallel, a desired value can be applied to the test for one clock cycle.

That is, according to the present invention, it is possible to improve the efficiency of the test by implementing the conventional sequential circuit so that these states can be directly controlled from the basic input without using a scan cell. This uses the test mode signal to control each flip-flop at the primary input in the test mode to set the desired state directly and to function normally in the normal mode. The counter for this may be configured as follows, for example.

output q; input reset, test_mode, di;

always ()

if (reset == 1) q = 0;

else q = q + 1;

In the circuit configured as described above, the count 100 can be obtained only after performing the state from 1 to 99, which is time consuming, and even if the scan cell is used, the previous serial shift registers must be passed. You need a test clock of.

However, if the circuit is implemented as follows, the desired state can be applied directly at the input, thereby reducing the test time.

output q; input reset, test_mode, test_data;

always ()

if (reset == 1) q = 0;

else if (test_mode) q = test_data

else q = q + 1;

Subsequently, an example of use in the state syntax is as follows.

input one, two, test_mode, test_data;

state S0, S1, S2, S3,... … , S100

always ()

if (reset) next = S0;

else if (test_mode == 1) current = test_data;

else

current = next;

case (current)

S0: if (one) next = S1;

else if (two) next = S2;

S1: if (one) next = S2;

else if (two) next = S3;

S2: if (one) next = S3;

else if (two) next = S4;

·

·

S99: if (one) next = S100;

else if (two) next = S0;

S100: if (one) next = S0;

else if (two) next = S1;

endcase

end

In the above syntax, since each state proceeds in series, it is necessary to go through the previous state in order to reach a particular state, but it is possible to directly reach the desired state by adding test logic. Thus, the test time is shortened. For example, when a specific state S100 is to be set, conventionally, at least 50 states, for example, S0-> S2-> S4-> S6->... You must go through S100, but you can create state S100 at once by using the test data (T_DATA).

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.

According to the present invention as described above, since all the test data (T_DATA) is input in parallel to the flip-flop constituting the test vector generation time, it is possible to apply the desired value to the test for one clock cycle, so that the test time It can be shortened.

Claims (1)

In the test vector generation circuit used for testing a semiconductor device, A basic input; And a plurality of shift registers connected in parallel with the basic input stage so that a desired value can be applied to a test of the semiconductor device during one clock cycle.