KR19990074905A - SRAM Cells - Google Patents

Abstract

Disclosed are an SRAM cell capable of reducing the size of a gate length and an offset region of a TFT transistor, that is, a cell size in the longitudinal direction. The SRAM cells are arranged in a longitudinal direction between the first transfer transistor and the second transfer transistor, and the first transfer transistor and the second transfer transistor, which are symmetrically arranged in the diagonal direction and are disposed in the transverse direction. An SRAM cell having a gate electrode of a first driving transistor and a gate electrode of a second driving transistor formed of a first conductive layer, each of which is formed of a second conductive layer, is symmetrical in a diagonal direction, and is formed of the first conductive layer. Between the transfer transistor and the second transfer transistor, the gate electrodes of the first and second TFT transistors having a predetermined length extending in the same longitudinal direction as the gate electrodes of the first and second driving transistors, and extending laterally; V _cc field, a doedoe extended by a predetermined length along the perpendicular direction from the V _cc area region of the TFT transistor A channel region disposed on the gate electrode, an offset region extending by a predetermined length in a direction perpendicular to the channel region, and a storage node region extending in the same direction as the offset region from the offset region, respectively; It is formed of a conductive layer and has first and second channels symmetrically in a diagonal direction.

Description

SRAM Cell

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an SRAM cell employing a TFT as a load device.

A static random access memory (SRAM) cell is typically composed of a flip-flop circuit consisting of two access transistors, two drive transistors, and two load elements. In particular, an SRAM employing a thin film transistor (hereinafter referred to as TFT) as a load element maintains a low standby current and a bulk type compared to an SRAM employing a resistor as a load element. Compared to full CMOS SRAMs employing PMOS transistors as load devices, there is an advantage in that the degree of integration is large.

On the other hand, the current upon stopping of the TFT-loaded cell is absolutely dependent on the gate length of the TFT transistor and the size of the offset region of the TFT transistor channel. However, as the cell size decreases, the size of the TFT transistor for adjusting the current characteristics at the stop in the TFT-loaded SRAM cell is also reduced. The reduction of the TFT transistor size is an obstacle to the implementation of a high-density SRAM device for low power consumption.

1 is an equivalent circuit diagram of a conventional SRAM cell employing a P-channel TFT as a load element.

Referring to FIG. 1, a conventional SRAM cell employing a P-channel TFT as a load element is connected in parallel between a power supply terminal Vcc and a ground terminal Vss, and is composed of a P-channel TFT and an NMOS transistor, respectively. A pair of inverters and a first transfer transistor T1 and a second transfer transistor T2 connected to a source region (or a drain region) of each of the inverters at an output terminal of the inverter are configured.

The drain region (or source region) of the first transfer transistor T1 and the drain region (or source region) of the second transfer transistor T2 are each a first bit line. B / L ) And second bitline ( ) In addition, the first and the second inverter is connected to the output terminal of the second inverter, the input terminal of the first inverter is connected to the output terminal of the first inverter, to form a latch circuit (latch circuit) do.

FIG. 2 illustrates a portion of a conventional mask pattern for manufacturing the SRAM cell of FIG. 1.

In FIG. 2, reference numeral 20 denotes an SRAM cell, reference numeral 22 denotes a mask pattern defining a TFT, and reference numeral 24 denotes a mask pattern defining a TFT gate electrode.

Referring to Fig. 2, a conventional mask pattern 22 defining a TFT is composed of a Vcc line region 22a, a TFT channel region 22b, an offset region 22c and a storage node region 22d. The pair is arranged symmetrically in the diagonal direction of the SRAM cell 20.

Here, the Vcc line 22a region extends in a straight line along the width of the SRAM cell 20. The TFT channel 22b region extends downwardly (or upwardly) from the Vcc line 22a region by a predetermined length. The offset region 22c continues downwards (or upwards) from the TFT channel 22b region, and the storage node 22d region extends downwards (or upwards) from the offset region 22c.

As described above, in the conventional mask pattern 22 defining the active region, the TFT channel 22b region and the offset region 22c are arranged in a straight line, and thus the size of the gate length and the offset region of the TFT transistor, i.e., in the longitudinal direction. There is a limit to reducing the cell size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an SRAM cell capable of reducing the size of the gate length and the offset region of the TFT transistor, that is, the cell size in the longitudinal direction.

1 is an equivalent circuit diagram of a conventional SRAM cell employing a P-channel TFT as a load element.

FIG. 2 illustrates a portion of a conventional mask pattern for manufacturing the SRAM cell of FIG. 1.

3 to 7 are diagrams illustrating an SRAM cell according to the present invention, illustrating one unit cell.

<Description of the symbols for the main parts of the drawings>

30: SRAM unit cell 32, 34: active area

42: gate of the first transfer transistor 44: gate of the second transfer transistor

46: gate of the second driving transistor 48: gate of the first driving transistor

52, 54: 62, 64: second conductive layer

72, 74: 3rd conductive layer

In order to achieve the above object, the SRAM cell of the present invention has a first transfer transistor and a second transfer transistor arranged in a symmetrical direction in a diagonal direction, and are disposed between the first transfer transistor and the second transfer transistor. In an SRAM cell having a predetermined length in a direction and having a gate electrode of a first driving transistor formed of a first conductive layer and a gate electrode of a second driving transistor, each of which is formed of a second conductive layer and is formed in a diagonal direction. Gates of the first and second TFT transistors which are symmetrically extended and extend with a predetermined length in the same longitudinal direction as the gate electrodes of the first and second driving transistors between the first transfer transistor and the second transfer transistor. electrode, and, as the V _cc region extending in a lateral direction, orthogonal direction from the region V _cc predetermined region of the road A channel region extending on the gate electrode of the TFT transistor, an offset region extending by a predetermined length in a direction perpendicular to the channel region, and a storage node region extending in the same direction as the offset region from the offset region. And first and second channels each formed of a third conductive layer and symmetrically arranged in a diagonal direction.

Here, the first conductive layer and the second conductive layer are preferably formed of polysilicon, and the third conductive layer is preferably formed of polysilicon or amorphous silicon.

Such an SRAM cell can reduce the size of the gate length and offset region of the TFT transistor, that is, the cell size in the longitudinal direction.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention may be modified in many different forms, and the scope of the present invention should not be construed as being limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the thicknesses of layers or regions are exaggerated for clarity. In the drawings, like reference numerals designate like elements. In addition, where a layer is described as being on the "top" of another layer or substrate, the layer may be present in direct contact with the top of the other layer or substrate, with another third layer interposed therebetween.

3 is a diagram illustrating a mask pattern for defining an active region, and is arranged symmetrically in a diagonal direction of a cell.

Referring to FIG. 3, reference numeral 32 denotes a mask pattern for forming an active region of a first transfer transistor and a first driving transistor, and reference numeral 34 denotes an active region of a second transfer transistor and a second driving transistor. For a mask pattern. Reference numeral 30 denotes a unit cell of the SRAM. In the actual process, the photolithography process using the mask patterns 32 and 34 for defining the active region of FIG. 3 is performed to define the active region of the semiconductor substrate, and then the inactive region of the semiconductor substrate is subjected to a conventional device isolation process. An isolation film is formed on the substrate.

4 is a diagram illustrating a mask pattern for forming a first conductive layer, and is disposed symmetrically in a diagonal direction of a cell.

Referring to FIG. 4, reference numeral 42 is a mask pattern for forming a gate of the first transfer transistor, and reference numeral 44 is a mask pattern for forming a gate of the second transfer transistor. Reference numeral 48 denotes a mask pattern for forming a gate of the first driving transistor, and reference numeral 46 denotes a mask pattern for forming a gate of the second driving transistor. In a practical process, a mask pattern 42, 44, 46, 48 for depositing a first conductive layer material, for example polysilicon, on the semiconductor substrate on which the device isolation film is formed and forming the first conductive layer of FIG. The first conductive layer region is defined on the semiconductor substrate by performing a photolithography process, and then the first conductive layer is formed on the semiconductor substrate through a normal etching process.

FIG. 5 is a diagram illustrating a mask pattern for forming a contact connecting the first conductive layer and the second conductive layer, and is disposed symmetrically in a diagonal direction of the cell.

Referring to FIG. 5, reference numeral 52 is a mask pattern for forming a contact hole for simultaneously connecting the active regions of the first transfer transistor and the first driving transistor and the gate electrodes of the second driving transistor and the first TFT. Reference numeral 54 is a mask pattern for forming a contact hole for simultaneously connecting the active regions of the second transfer transistor and the second driving transistor and the gate electrodes of the first driving transistor and the second TFT. In an actual process, after forming an interlayer insulating film on the entire surface of the semiconductor substrate on which the first conductive layer is formed, performing a photo process using mask patterns 52 and 54 for forming contact holes, and then forming contact holes on the semiconductor substrate. After defining the region, a contact hole is formed on the semiconductor substrate through a normal etching process.

FIG. 6 is a diagram showing a mask pattern for forming a second conductive layer, that is, a gate electrode of a TFT, and is arranged symmetrically in the diagonal direction of the cell as in FIG.

Referring to Fig. 6, reference numeral 62 denotes a mask pattern for forming the gate electrode of the first TFT, and reference numeral 64 denotes a mask pattern for forming the gate electrode of the second TFT. In an actual process, a photo process using a mask pattern 62, 64 for forming a second conductive layer after depositing a second conductive layer material, for example polysilicon, on the entire surface of the semiconductor substrate on which the contact hole is formed is performed. The gate electrode region of the first TFT and the gate electrode region of the second TFT are defined on the semiconductor substrate, and then a second conductive layer is formed on the semiconductor substrate through a normal etching process. Typically, the second conductive layer is formed of a polysilicon layer.

Here, the mask pattern (24 of FIG. 2) for forming the conventional second conductive layer is a mask pattern (not shown) for forming the gate of the second driving transistor and a mask pattern for forming the gate of the first driving transistor. (Not shown) and have a generally rectangular shape extending in a direction perpendicular to each other. However, such a pattern (24 in Fig. 2) is difficult to form a pattern due to a step, and in particular, when reducing the size of the cell in the longitudinal direction, there is a limit in reducing the size of the cell because sufficient gate length of the TFT cannot be secured. . However, as shown in FIG. 6, unlike the conventional pattern (24 of FIG. 2), the mask patterns 62 and 64 for forming the second conductive layer according to the present invention form a gate of the second driving transistor. The mask pattern 46 and the mask pattern 48 for forming the gate of the first driving transistor each have a generally rectangular shape extending in the same direction. Such mask patterns 62 and 64 for forming the second conductive layer of the present invention are less susceptible to stepping, making it easy to form patterns, especially when reducing the size of the cell in the longitudinal direction. Since the length can be ensured, it is possible to reduce the cell size in the longitudinal direction as compared with the conventional mask pattern.

7 is a diagram illustrating a mask pattern for forming a third conductive layer, and is disposed symmetrically in a diagonal direction of a cell.

Referring to Fig. 7, reference numeral 72 denotes a mask pattern for forming a channel of the first TFT, and reference numeral 74 denotes a mask pattern for forming a channel of the second TFT. In the actual process, after depositing the third conductive layer material on the entire surface of the semiconductor substrate on which the second conductive layer is formed, the semiconductor layer is subjected to a photo process using mask patterns 72 and 74 for forming the third conductive layer. A channel region of the first TFT and a channel region of the second TFT are defined on the substrate, and then a third conductive layer is formed on the semiconductor substrate through a normal etching process. The third conductive layer is typically formed of a polysilicon layer or an amorphous silicon layer.

Here, the mask patterns 72 and 74 for forming the third conductive layer according to the present invention may include a region of Vcc lines 72a and 74a extending linearly along the width of the SRAM cell 30 and the Vcc lines ( TFT channel 72b, 74b regions extending downwardly (or upwardly) from the regions 72a, 74a by a predetermined length, and offset regions extending generally at right angles from the lower end portions of the TFT channel 72b, 74b regions ( 72c and 74c and areas of storage nodes 72d and 74d that continue to extend along the width of the SRAM cell 30 from the offset areas 72c and 74c.

In general, the offset regions 72c and 74c are formed in the drain region of the TFT to serve as the most important factor for adjusting the magnitude of the current consumption when the TFT-loaded SRAM cell is stopped. As shown in FIG. 2, in the mask pattern 22 for forming the conventional third conductive layer, the channel region 22b and the offset region 22c of the TFT have the same direction as the gate direction of the first and second driving transistors. It has a straight shape. However, the mask patterns 72 and 74 for forming the third conductive layer according to the present invention are formed with a "b" character or "" in which the channel regions 72b or 74b and the offset regions 72c or 74c of the TFT are formed at substantially right angles. It has the shape of a ". That is, according to the present invention, the channel region 72b or 74b of the TFT is disposed in the same direction as the gate direction of the first and second driving transistors, but the offset region 72c or 74c is formed of the first and second driving transistors. It is arranged in a direction perpendicular to the gate direction.

The best embodiment has been disclosed in the drawings and specification above. Herein, specific terms have been used, but these are merely used to describe the present invention and are not used to limit the meaning or the scope of the present invention described in the claims below. For example, the lower film can be replaced with another film such as a nitride film.

As described above, the SRAM cell according to the present invention is disposed such that the channel region of the TFT and the offset region of the TFT have a shape of "|" or "a", so that the gate length and the size of the offset region of the TFT transistor, That is, the cell size in the longitudinal direction can be reduced. Therefore, compared with the conventional SRAM cell, the channel area of the TFT is increased by approximately 20%, thereby lowering the stop current consumption required in the highly integrated low power consumption SRAM.

Claims (3)

The first transfer transistor and the second transfer transistor and the first transfer transistor and the second transfer transistor, which are symmetrical in the diagonal direction and are disposed in the transverse direction, are disposed with a predetermined length in the longitudinal direction between the first transfer transistor and the second transfer transistor. A SRAM cell comprising a gate electrode of a first driving transistor and a gate electrode of a second driving transistor, wherein Each of the second conductive layers is formed to be symmetrical in a diagonal direction, and has a predetermined length in the same longitudinal direction as the gate electrodes of the first and second driving transistors between the first transfer transistor and the second transfer transistor. Gate electrodes of extending first and second TFT transistors; A V _cc region extending laterally, a channel region extending from the V _cc region by a predetermined length at a right angle, and disposed on the gate electrode of the TFT transistor, and a channel length extending from the channel region at a right angle. An offset region extending and a storage node region extending in the same direction as the offset region from the offset region, each having a first conductive layer formed of a third conductive layer and having symmetrical directions in a diagonal direction; RAM cell. The method of claim 1, And the first conductive layer and the second conductive layer are formed of polysilicon. The method of claim 1, The third conductive layer is SRAM cell, characterized in that formed of polysilicon or amorphous silicon.