KR19990073847A - Silicide Forming Method in Semiconductor Manufacturing Process - Google Patents

Abstract

In the manufacturing process of the semiconductor device, the silicide formed to reduce the contact resistance and the resistance of the gate electrode is stabilized to deteriorate in a subsequent thermal process to maintain electrical properties of the n ⁺ silicon region. Isolation between devices through growth, P-wells and N-wells are formed through implantation of dopant material into the active region, gate oxides are formed on the P-wells and N-wells, and dopants are used as gate oxides as masks. The material implantation forms an n ⁺ type diffusion layer and a p ⁺ type diffusion layer, deposits polysilicon on a gate oxide layer, forms a spacer oxide layer, and injects a p type dopant material on the silicon wafer to form an n + diffusion layer and n +. The upper part of the polysilicon region has p-type property, so that the reactivity of silicon and titanium silicide in the subsequent thermal process is reduced. As a result, the silicide layer is thickened to stabilize the electrical properties of the silicon region.

Description

Silicide Forming Method in Semiconductor Manufacturing Process

The present invention relates to a semiconductor manufacturing method, and more particularly, to stabilize the silicides (TiSi ₂ , CoSi ₂ ) formed to reduce contact resistance and gate electrode resistance in a device manufacturing process in a subsequent process. The present invention relates to a silicide formation method in a semiconductor manufacturing process in which electrical properties of n ⁺ silicon regions are maintained.

In general, a titanium silicide layer is formed in order to minimize contact resistance and gate electrode resistance which are generated during the electrode connection of the device or the connection between the device and the device in the semiconductor manufacturing process.

A process of forming a titanium silicide layer in a semiconductor manufacturing process of a conventional LOCOS (hereinafter referred to as "LOCOS") structure is an initial oxide film on a silicon (Si) wafer 1, as can be seen in Figure 1a. The devices are separated through the formation of a CVD layer, the deposition of a nitride film using LPCVD, and the growth of the field oxide film 4 after the dry etching of the nitride film on the field region. Subsequently, a coating film is formed on the silicon wafer 1, and then a pattern is formed in the active region by a photoresist to ion implant the dopants such as phosphorus (P) and boron (B). P-well (2) and N-well (3).

When the formation of the P-wells 2 and the N-wells 3 is completed as described above, the P-wells 2 and the N-wells 3 may be formed by a photolithography process using a gate mask. A gate oxide film 5a (5b) is formed in the region, a pattern is formed in the corresponding region between the gate oxide film 5a (5b) and the fill oxide film 4, and then n-type and p-type dopant materials are ionized, respectively. Injecting to form the n ⁺ type diffusion layer 8 and the p ⁺ type diffusion layer 9. Subsequently, n ⁺ polysilicon 6 on the gate oxide film 5a formed on the P-well 2 and p ⁺ on the gate oxide film 5b formed on the N-well 3. The polysilicon 7 is deposited through a predetermined technique, and the n ⁺ polysilicon 6 and the p ⁺ polysilicon 7 formed on the gate oxide films 5a and 5b are n ⁺ diffusion layers 8. ) And a spacer oxide film 10 is grown on the sides of the n ⁺ polysilicon 6 and the p ⁺ polysilicon 7 to isolate the p ⁺ type diffusion layer 9.

N ⁺ diffusion layer 8, p ⁺ diffusion layer 9, n formed of source, drain and gate regions through a series of local oxidation of silicon (LOCOS) processes as described above. ^When the formation of the ⁺ polysilicon (6) and P ⁺ polysilicon (7) regions is completed, silicide is formed to minimize contact resistance and gate electrode resistance generated during the electrode connection of the device and the connection between the device and the device. As can be seen in FIG. 1B, titanium (11) on top of the n ⁺ diffusion layer (8), p ⁺ diffusion layer (9), n ⁺ polysilicon (6) and P ⁺ polysilicon (7) region Is deposited evenly by atmospheric vapor deposition (APCVD). After the deposition of titanium 11 is performed as described above, the silicon and titanium 11 are reacted by a low temperature rapid thermal annealing (RTA) process, and as illustrated in FIG. 1C, the n ⁺ diffusion layer 8 and The titanium silicide 12 is formed in the p ⁺ diffusion layer 9, the n ⁺ polysilicon 6, and the P ⁺ polysilicon 7 region.

Thereafter, ammonia (NH ₄ OH) is applied such that the titanium silicide 12 remains only in the n ⁺ diffusion layer 8, the p ⁺ diffusion layer 9, the n ⁺ polysilicon 6, and the P ⁺ polysilicon 7 region. The titanium (11) film is selectively etched through an etching solution in which hydrogen peroxide (H ₂ O ₂₎ and water (H ₂ O) are diluted in a predetermined ratio, preferably in a ratio of 1: 1: 5, and a high temperature RTA. Through the process to complete the process for forming the silicide layer in the semiconductor manufacturing process of the LOCOS structure.

As described above, the silicide film formed in the n ⁺ diffusion layer 8, the p ⁺ diffusion layer 9, the n ⁺ polysilicon 6, and the P ⁺ polysilicon 7 region includes phosphorus (P) and arsenic (As). And a dopant material such as boron (B) is formed by reaction of silicon and titanium implanted with n ⁺ silicon doped with phosphorus (P) and arsenic (As) and p ⁺ silicon doped with boron (B). When the reaction of P ⁺ silicon doped with boron (B) is easy to react with the titanium, n ⁺ silicon doped with phosphorus (P) and arsenic (As) is easy to react with the titanium You won't lose.

Therefore, the thickness of the titanium silicide 12 formed on the top of n ⁺ diffusion layer 8 and n ⁺ polysilicon 6 is the titanium silicide formed on top of p ⁺ diffusion layer 9 and p ⁺ polysilicon 7. It becomes thinner than the thickness of (12). In this state, when the high temperature thermal process is performed at a temperature higher than about 800 ° C. to inject the oxide, the electrical properties of the titanium silicide on the n ⁺ diffusion layer and the n ⁺ polysilicon on which the titanium silicide is relatively thin are rapidly degraded. There is a disadvantage in that the junction leakage current and contact resistance are increased.

The present invention has been made in view of the above-described general problems, and its object is boron fluoride (BF ₂ ), which is a p-type dopant material in an n ⁺ silicon region doped with phosphorus (P), arsenic (As), and the like. Alternatively, dopant materials such as boron (B) can be ion implanted at low energy so that the upper part of the n ⁺ silicon region has the properties of p ⁺ silicon so that titanium deposited for silicide formation is easily reactive in the n ⁺ silicon region. In order to stabilize the electrical properties of n ⁺ silicon in a subsequent high temperature thermal process.

1A to 1C are cross-sectional views illustrating a silicide forming process in a semiconductor manufacturing process of a conventional LOCOS structure;

2A to 2C are cross-sectional views illustrating a silicide forming process in a semiconductor manufacturing process of a LOCOS structure according to an embodiment of the present invention.

The present invention for achieving the object as described above, in the manufacturing process of the semiconductor device, between the devices by the growth of the field oxide film on the upper portion of the silicon wafer, the dopant material is injected into the active region P-well and N The wells are formed, and gate oxide films are formed in the P-wells and the N-wells. Injecting n-type and p-type dopant materials to form a gate oxide layer as a mask to form an n ⁺ type diffusion layer and a p ⁺ type diffusion layer, depositing n ⁺ polysilicon and p ⁺ polysilicon on the gate oxide layer, and then n ⁺ type After the spacer oxide layer is formed to isolate the diffusion layer and the p ⁺ diffusion layer, a p-type dopant material is implanted into the silicon wafer so that the upper portions of the n + diffusion layer and the n + polysilicon region have a p-type property and then deposit titanium titanium. Process.

In the silicide formation through the present invention described above, since the upper end portion of the n + silicon region has a p + type property, the reactivity is good in the thermal process after the deposition of the titanium silicide film, so that the silicide film is formed thick and stabilized in the subsequent thermal process, the n + silicon is stabilized. Improve the electrical properties of the area.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the process of forming a silicide layer in a semiconductor manufacturing process of a LOCOS structure according to an embodiment of the present invention, as shown in FIG. 2A, an initial oxide film is formed on a silicon (Si) wafer 101 and a low pressure deposition method is performed. After the deposition of the nitride film used and the dry etching of the nitride film on the field region, the device oxide is separated through the growth of the field oxide film 104. Subsequently, a coating film is formed on the silicon wafer 101, and then a pattern is formed on the corresponding region by a photoresist to ion implant a dopant material such as phosphorus (P) and boron (B) to form a P-well 102. And N-well 103.

As described above, when the formation of the P-well 102 and the N-well 103 is completed, a gate oxide layer may be formed on a predetermined portion of the P-well 102 and the N-well 103 by a photolithography process using a gate mask. 105a) and 105b, a pattern is formed between the gate oxide films 105a and 105b and the fill oxide film 104, and then n + and p type dopant materials are ion implanted, respectively, to form n ⁺ . The diffusion layer 108 and the p ⁺ type diffusion layer 109 are formed. Thereafter, n ⁺ polysilicon 106 is formed on the gate oxide film 105a formed on the P-well 102 and p ⁺ is formed on the gate oxide film 105b formed on the N-well 103. The polysilicon 107 is deposited through a predetermined technique, and the n ⁺ polysilicon 106 and the p ⁺ polysilicon 107 formed on the gate oxide films 105a and 105b are n ⁺ diffusion layers 108. And a spacer oxide film 110 is grown on the sides of the n ⁺ polysilicon 106 and the p ⁺ polysilicon 107 to isolate the p ⁺ type diffusion layer 109.

N ⁺ diffusion layer 108, p ⁺ diffusion layer 109, n formed of source, drain, and gate regions through a series of local oxidation of silicon (LOCOS) processes as described above. ^When the formation of the ⁺ polysilicon 106 and P ⁺ polysilicon 107 regions is completed, a predetermined amount of p-type dopant materials, such as boron fluoride (BF2) and boron (B), is injected at a low energy level through an ion implanter. (113) such that the top 114 of n ⁺ diffusion layer 108 and n ⁺ polysilicon 106 has the properties of p ⁺ diffusion layer 109 and p ⁺ polysilicon 107.

As described above, the n ⁺ silicon region is characterized by p ⁺ type silicon through ion implantation of p-type dopant material, and then the contact storage and gate electrode resistance generated during the electrode connection of the device and the connection between the device and the device are reduced. As can be seen in Figure 2b to form a silicide in a process for minimizing, the n ⁺ diffusion layer 108, p ⁺ diffusion layer 109, n ⁺ polysilicon 106 and P ⁺ polysilicon 107 Titanium 120 is evenly deposited on top of the area by atmospheric vapor deposition (APCVD). After the deposition of the titanium 120 as described above, the silicon and the titanium 120 reacts through a low temperature RTA process so that the n ⁺ diffusion layer 108 and the p ⁺ diffusion layer (as can be seen in FIG. 2c). 109), titanium silicide 121 is formed in the n ⁺ polysilicon 106 and P ⁺ polysilicon 107 regions.

Thereafter, ammonia (NH ₄ OH) is applied such that the titanium silicide 121 remains only in the n ⁺ diffusion layer 108, the p ⁺ diffusion layer 109, the n ⁺ polysilicon 106, and the P ⁺ polysilicon 107. The titanium 120 film is selectively etched through an etching solution in which hydrogen peroxide (H ₂ O ₂₎ and water (H ₂ O) are diluted in a predetermined ratio, preferably, in a ratio of 1: 5, and a high temperature RTA. Through the process to complete the process for forming the silicide layer in the semiconductor manufacturing process of the LOCOS structure.

The above ion implantation to the semiconductor manufacturing process of the LOCOS structure according to the invention, n ⁺ diffusion layers and p ⁺ diffusion layer, n ⁺ polysilicon and p ⁺ polysilicon dopant material of the p-type in the state forming the completion of the steps described in the n ⁺ Since the type diffusion layer and n ⁺ polysilicon have a p ⁺ property, the reactivity of silicon and titanium silicide is improved and the silicide layer is formed thick, so that the electrical properties of the n ⁺ diffusion layer and n ⁺ polysilicon are stabilized in a subsequent thermal process. Reliability is improved in the manufacture of semiconductor devices.

Claims (4)

In the fabrication process of a semiconductor device, the devices are separated through growth of a field oxide film on a silicon wafer, and then a dopant material is injected into an active region to form P-wells and N-wells, and the P-wells and N Forming a gate oxide film in the well, and implanting n-type and p-type dopant materials using the gate oxide film as a mask to form an n ⁺ type diffusion layer and a p ⁺ type diffusion layer, and n ⁺ polysilicon and p in the gate oxide layer ⁺ Depositing polysilicon and then forming a spacer oxide film, And injecting a p-type dopant material on the silicon wafer on which the spacer oxide film is formed to make upper ends of the n + diffusion layer and the n + polysilicon region have a p-type property and then depositing titanium silicide. Silicide Forming Method in Manufacturing Process. The method of claim 1, wherein the dopant material to be implanted after the spacer oxide layer is formed in the process uses low energy. The method of any one of claims 1 to 2, wherein the p-type dopant material is boron fluoride (BF2) or boron (B). The method of claim 1, wherein a predetermined amount of the p-type dopant material to be implanted is implanted.