KR19990070242A - How to Form Multilayer Wiring - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a multi-layered photo mask, wherein a plurality of first dummy patterns are formed in predetermined portions between the first wirings while a plurality of first wirings are formed in predetermined portions on a substrate, and the plurality of first dummy patterns are formed on the substrate. Forming a first interlayer insulating film to cover the plurality of first wirings and the plurality of first dummy patterns, performing the process n-1 (n is a natural number of two or more) times, and the nth interlayer insulating film And forming a plurality of n-th wirings on the substrate. Accordingly, the multi-layered photomask for the multilayer wiring according to the present invention can prevent the short circuit of the upper wiring formed on the interlayer insulating film by forming a wiring pattern and a dummy pattern to improve the topography of the interlayer insulating film covering the wiring pattern and the dummy pattern. It also has the advantage of improving the loading effect.

Description

How to Form Multilayer Wiring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a multilayer wiring, and more particularly, to a method of forming a multilayer wiring in which a dummy pattern is formed in a lower wiring layer to planarize an interlayer insulating film when a multilayer wiring is formed.

As semiconductor devices have been highly integrated, the size of devices has also been reduced, so that the metal wirings have not only been narrowed but also formed of interconnection lines. Multi-layer wiring compensates for the reduction of the area of the device. An important problem in forming a multi-layer wiring is the planarization of Inter Metal Dielectric, which improves the topography of the surface of the interlayer insulating film covering the lower wiring. In forming the upper wiring, it should be possible to prevent shorting of the upper wiring.

1A to 1C are cross-sectional process diagrams showing a method for forming a multilayer wiring according to the prior art.

Conventionally, as shown in FIG. 1A, a conductive material such as copper (Cu), tungsten (W), or aluminum (Al) is deposited on the substrate 11 to form a first conductive material layer, and the first conductive material layer may be formed. A plurality of first wirings 13 are formed by patterning the photolithography method.

Thereafter, as shown in FIG. 1B, impurities having high reflow characteristics as well as insulating properties to cover the first wiring 13 on the substrate 11 are easily doped with high concentrations of impurities. The first interlayer insulating film 15 is formed of BSG (Boro Silicate Glass), PSG (Phospho Silicate Glass), BPSG (Boro-Phospho Silicate Glass), or the like. The second conductive material layer 16 is formed by depositing copper (Cu), tungsten (W), aluminum (Al), or the like on the interlayer insulating film 15. Then, a positive photoresist 17 is coated on the second conductive material layer 16 in which portions reacted with light are removed by a developer, and a flat plate having good light transmittance such as glass, quartz, or the like ( 18) a photo mask (PM) defining a light blocking region 19 by selectively forming a thin metal film such as nickel (Ni), chromium (Cr), and cobalt (Co) to prevent ultraviolet rays from penetrating. It is exposed using.

Next, as illustrated in FIG. 1C, when the photoresist 17 exposed using the photo mask PM is developed, the photoresist may be formed only at a portion corresponding to the light blocking region 19 of the photo mask PM. When the photoresist 17 pattern having the remaining 17 is formed, the second conductive material layer 16 is etched using the photoresist 17 pattern as a mask, and the remaining photoresist 17 is removed. The second wiring 20 is formed in a portion corresponding to the light blocking region 19 of the mask PM.

In order to form the multilayer wiring of two or more layers shown in the drawing, the above-described method is repeated to form a second interlayer insulating film and a third wiring on the second wiring. The n-th interlayer insulating film and the n-th wiring are repeatedly formed on the n-th wiring to form a multilayer wiring semiconductor element having n-layer wiring.

As described above, the method of forming a first wiring in a predetermined portion on a substrate and forming an interlayer insulating film covering the first wiring, and then repeatedly forming a second wiring in a predetermined portion on the interlayer insulating film is repeated to multi-layer wiring. Formed.

However, as the multilayer wiring continues to be formed, there is a limitation in the planarization of the interlayer insulating film between the wiring patterns, and the topography of the portion with the wiring pattern and the portion without the wiring pattern becomes poor. Therefore, if the topography defect is severely generated at the bottom, the upper wiring formed on the interlayer insulating film due to the lack of halation or photo margin at the time of exposure for the patterning of the upper wiring is the upper portion. There is a problem that a short circuit occurs between the wirings.

Accordingly, an object of the present invention is to form a multilayer wiring that can planarize an interlayer insulating film at the time of forming a multilayer wiring to prevent a short circuit between the upper wiring due to a lack of light margin and a halation during exposure for formation of the upper wiring. In providing a method.

A method of forming a multilayer wiring according to the present invention for achieving the above object is to form a plurality of first dummy patterns in a predetermined portion between the first wiring while forming a plurality of first wiring on a predetermined portion on the substrate and on the substrate Forming a first interlayer insulating film so as to cover the plurality of first wires and the plurality of first dummy patterns, performing the step n-1 (n is a natural number of two or more) times, and the nth A step of forming a plurality of n-th wiring on the interlayer insulating film is provided.

1A to 1C are cross-sectional process diagrams showing a method for forming a multilayer wiring according to the prior art.

2A to 2D are cross-sectional process diagrams illustrating a method of forming a multilayer wiring according to an embodiment of the present invention.

Brief description of symbols for the main parts of the drawings

21 substrate 27 first wiring

28 dummy pattern 29 interlayer insulating film

35: second wiring

Hereinafter, with reference to the accompanying drawings will be described the present invention.

2A to 2D are cross-sectional process views illustrating a method of forming a multilayer wiring according to an embodiment of the present invention.

As shown in FIG. 2A, a conductive material such as copper (Cu), tungsten (W), or aluminum (Al) is deposited on the substrate 21 to form a first conductive material layer 22, and the first conductive material layer. A positive type first photoresist 23 in which a portion reacted with light is removed by a developer on the 22 is applied, and ultraviolet rays do not penetrate onto the light-transmitting flat plate 24 such as glass or quartz. The first photo mask PM1 having the first and second light blocking regions 25 and 26 may be formed by selectively forming thin metal films such as nickel (Ni), chromium (Cr), and cobalt (Co). Exposure. The first light blocking region 25 of the first photo mask PM1 is for forming a plurality of first wires, and the second light blocking region 26 of the first photo mask PM2 is the first light blocking. When a plurality of regions are formed to have a predetermined distance between the area 25 and about 1.5 times the first light blocking area 25 and a predetermined distance between the second light blocking areas 26 to form the first wiring. It is for forming a first dummy pattern.

Thereafter, as illustrated in FIG. 2B, the first photoresist 23 exposed by the first photomask PM1 having the first and second light blocking regions 25 and 26 formed thereon is developed to thereby treat the first photo. Only the first photoresist 23 in the portion corresponding to the first and second light blocking regions 25 and 26 of the mask PM1 forms a pattern of the first photoresist 23, and the first photoresist ( 23) The first conductive material layer 22 is etched using the pattern as a mask, and the remaining first photoresist 23 is removed to remove the first and second light blocking regions 25 of the first photo mask PM1. A plurality of first wirings 27 and a plurality of first dummy patterns 28 are formed in portions corresponding to the plurality of first and second ones 26.

After that, as shown in FIG. 2C, not only insulation properties but also good reflow characteristics are formed on the substrate 21 to cover the first wirings 27 and the first dummy patterns 28. A first interlayer insulating film 29 is formed of BSG, PSG, or BPSG doped with a high concentration of impurities, and copper (Cu), tungsten (W), aluminum (Al), etc. are formed on the first interlayer insulating film 29. To form a second conductive material layer 31 by depositing a conductive material. The first interlayer insulating layer 29 covering the first wiring 27 and the first dummy pattern 28 is improved in planarization due to the first dummy pattern 28. The second photoresist 32 of the positive type in which the portion reacted with the light is removed by the developer on the second conductive material layer 31 is coated on the transparent plate 33 such as glass or quartz. ), And a metal thin film such as chromium (Cr) and cobalt (Co) may be selectively formed and exposed using the second photo mask PM2 having the third and fourth light blocking regions 34 and 36. In this case, the third light blocking region 34 is a region for forming a second wiring, and the fourth light blocking region 36 is a predetermined distance from the third light blocking region 34, and is about the third light blocking region 34. It is formed at a distance of 1.5 times or more to form a second dummy pattern together with the second wiring.

Next, as illustrated in FIG. 2D, when the second photoresist 32 exposed using the second photo mask PM2 is developed, the third and fourth light blocking regions 34 of the second photo mask PM2 may be formed. The second photoresist 32 pattern in which the second photoresist 32 remains only in a portion corresponding to the 36 is formed, and the second conductive material layer is formed by using the second photoresist 32 pattern as a mask. When the 31 is etched and the remaining second photoresist 32 is removed, a plurality of second wirings 35 are formed at portions corresponding to the third light blocking region 34 of the second photo mask PM2. In addition, a plurality of second dummy patterns 37 are formed in a portion corresponding to the fourth light blocking region 36.

In order to form a multi-layered wiring having two or more layers by the above-described method, a second interlayer insulating film is formed to cover the plurality of second wirings and the plurality of second dummy patterns, and a plurality of third wirings are formed on a predetermined portion on the second interlayer insulating film. The third dummy pattern; , the interlayer insulating film formed between the respective wiring layers by forming the n-1 wiring and the n-1 dummy pattern from the n-1 layer to the n-1 layer except the n layer which is the uppermost layer in the multilayer wiring having the n layer. Improve the topography of areas with patterns and areas without wiring patterns.

As described above, in the present invention, when the multilayer wiring is formed, a dummy pattern is formed together with the lower wiring to planarize the interlayer insulating film, and thus there is no wiring pattern and a portion with the wiring pattern of the interlayer insulating film covering the lower wiring and the dummy pattern. To improve the topography of the part. Therefore, the upper wiring formed on the interlayer insulating film having the improved topography can improve the halation or the lack of optical margin during exposure, and the loading effect is improved, so that the progress of the subsequent process can be improved. It becomes easy.

Accordingly, in the multilayer wiring according to the present invention, a wiring pattern and a dummy pattern are formed to improve the topography of the interlayer insulating film covering the wiring pattern and the dummy pattern, thereby preventing a short circuit of the upper wiring formed on the interlayer insulating film. The loading effect can also be improved.

Claims (2)

While forming a plurality of first wirings on a predetermined portion on a substrate, a plurality of first dummy patterns are formed in a predetermined portion between the first wirings, and the plurality of first wirings and the plurality of first dummy patterns are formed on the substrate. Forming a first interlayer insulating film so as to cover; Performing the process n-1 (n is a natural number of 2 or more); And forming a plurality of n-th interconnections on the n-th interlayer insulating film. The method of claim 1, wherein the first dummy pattern is formed to have a spacing of 1.5 times or more between the first wiring and the first wiring pattern region.