KR19990070199A - Mask for semiconductor device separation and manufacturing method of semiconductor device using same - Google Patents

Abstract

Top left alignment key (UL), top right alignment key (UR), bottom left alignment key (LL) and bottom right alignment key (LR) at four corners to form a semiconductor device isolation region The mask for semiconductor element isolation | separation which has a square element-shaped isolation | separation area | region in which is formed is dividedly exposed while repeatedly moving up and down or left and right. When the mask is moved downward, the mask is arranged so that the alignment keys UL and UR formed on the upper side of the element isolation region overlap with the alignment keys LL and LR formed on the lower side of the element isolation region during the previous exposure. Sort it. When the mask is moved to the right, the alignment keys UL and LL formed on the left side of the element isolation region are different from the alignment keys UR and LR formed on the right side of the element isolation region during the previous exposure. Arrange to overlap. Therefore, the four alignment keys UR, UL, LL, and LR at positions other than the edges overlap at least once, thereby forming an alignment correction pattern in the semiconductor device isolation region of the wafer. In this case, the shape and size of the alignment correction pattern may be measured to accurately align the mask for semiconductor device separation.

Description

Mask for separating semiconductor elements and method of manufacturing semiconductor device using same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask for semiconductor element separation, and more particularly, to a mask for semiconductor element separation used to separate a region occupied by a plurality of semiconductor elements on a wafer.

Generally, when exposing the photosensitive film | membrane apply | coated to one wafer in the photographic process of a manufacturing method of a semiconductor element, divided exposure is performed, moving the mask in which the pattern is formed up, down, left, and right.

Looking at the electronic circuit formed on the wafer in plan view, it is divided into an active region in which a semiconductor device is located and an isolation region in which an active region is defined and separated from each other. In the active region, a plurality of doped regions doped with N-type or P-type impurities are formed, and the doped regions are connected to the outside through a wiring.

At this time, when performing a photo process, a plurality of doped regions should be exactly aligned with each other, the position of the mask mounted on the alignment exposure machine, and the focus of the lens should be correct. To confirm this, an alignment key is formed on the mask to form an alignment key on the wafer. The plurality of doped regions are formed while being aligned with each other through the alignment key.

As such, when the alignment key is used, the plurality of doping regions are aligned with each other, and the alignment accuracy thereof may be measured through the alignment measuring equipment.

In this case, all the doped regions are aligned based on the device isolation region formed first. Therefore, the device isolation region must be correctly aligned so that the layers or regions formed thereafter are correctly aligned.

However, since there is no alignment key as a reference when forming the device isolation region, the rotation of the mask used to form the device isolation region, the focus of the lens, and the degree of misalignment of the pattern cannot be accurately known.

An object of the present invention is to provide a device separation mask for aligning device isolation regions formed on a wafer.

1 is a plan view showing the structure of a mask for semiconductor device isolation according to an embodiment of the present invention;

2 is a detailed view showing in detail the alignment key for the upper right in Figure 1,

3 is a detailed view showing in detail the alignment key for the upper left in Figure 1,

4 is a detailed view showing in detail the alignment keys for the lower right in Figure 1,

5 is a detailed view showing in detail the alignment key for the lower left in Figure 1,

FIG. 6 is a plan view illustrating an alignment pattern formed in an element isolation region of a wafer through a semiconductor element isolation mask.

In order to solve the above problems, the semiconductor device isolation mask according to the present invention defines an active region, and a plurality of alignment keys are formed in the device isolation region formed around the active region.

In order to form the device isolation region on the wafer by using the semiconductor device isolation mask according to the present invention, the mask is aligned by aligning the alignment keys so as to overlap each other during the split exposure.

In this case, when the active region has a square shape, the device isolation region has a square ring shape, and alignment keys are formed at four corners of the device isolation region, respectively.

The device isolation region is formed on the wafer while the semiconductor device isolation mask according to the present invention is moved up and down or left and right, and overlaps with the alignment key formed on the other side and the alignment key formed on one side of the four alignment keys. Sort it. Then, all four alignment keys are stacked while moving up and down or left and right, and an alignment pattern is formed on the wafer through exposure of alignment keys having patterns of different shapes.

Then, with reference to the accompanying drawings, with respect to the embodiment of the semiconductor device isolation mask according to the present invention and a method for manufacturing a semiconductor device using the same to the extent that can be easily carried out by those of ordinary skill in the art It explains in detail.

1 is a plan view illustrating a structure of a mask for semiconductor device isolation according to an embodiment of the present invention.

As shown in FIG. 1, in the semiconductor device isolation mask according to the embodiment of the present invention, an active region 10 in which a doped layer of a semiconductor device is to be formed is formed in the center of a transparent substrate 100. In the periphery of the active region 10, a square element isolation region 20 defining an active region 10 is formed, and four alignment keys 30 are formed at four corners of the element isolation region 20. have. Here, the four alignment keys 30 are composed of an upper left alignment key (UL), an upper right alignment key (UR), a lower left alignment key (LL), and a lower right alignment key (LR). The hatched portion 40 around the device isolation region 20 is a portion that blocks light when exposed.

In the method of manufacturing a semiconductor device using the semiconductor device isolation mask according to the exemplary embodiment of the present invention, the device isolation region is formed at regular intervals on the upper portion of the wafer while repeatedly moving the mask vertically or horizontally. For example, when the mask is moved downward, the alignment keys UL and UR formed on the upper side of the element isolation region 20 are aligned on the lower side of the element isolation region 20 during the previous exposure. Align the mask so that it overlaps with the keys LL and LR. On the contrary, when the mask is moved downward, the alignment keys LL and LR formed on the lower side of the element isolation region 20 are formed on the upper side of the element isolation region 20 during the previous exposure. UL, UR) and the mask is aligned so as to overlap each other. When the mask is moved to the right, the alignment keys UL and LL formed on the left side of the element isolation region 20 are formed on the right side of the element isolation region 20 during the previous exposure. UR, LR) and overlap each other. Therefore, except for the edge, the four alignment keys UR, UL, LL, and LR overlap at least once.

If a device isolation region is formed on a wafer by using a semiconductor device isolation mask according to an embodiment of the present invention, misalignment may occur, which can be divided into two types as follows.

First, the four alignment keys UR, UL, LL, and LR are completely misaligned with each other. At this time, the four alignment keys (UR, UL, LL, LR) is not completely overlapped.

As such, when the four alignment keys UR, UL, LL, and LR are completely displaced without overlapping with each other, the degree of misalignment may be easily measured by using the alignment measuring equipment.

On the other hand, if a slight misalignment occurs because only some of the four alignment keys (UR, UL, LL, LR) overlap, form a pattern of different shapes on the four alignment keys (UR, UL, LL, LR) The degree of deviation can be measured by measuring the shape or size of the pattern formed by superimposing them on the wafer. Through this process, it is possible to accurately align the mask for semiconductor device separation.

For example, it will be described in detail as follows.

First, the upper left alignment key (UL), the upper right alignment key (UR), the lower left alignment key (LL), and the lower right alignment key (LR) in which patterns of different shapes are formed are described in detail. The explanation is as follows.

FIG. 2 is a detailed view showing the alignment key for the upper right side in FIG. 1 in detail.

As shown in FIG. 2, the four position display regions 51, 52, 53, 54, 55, 56, 57, and 58 that respectively indicate positions on the upper and lower edges are uniformly arranged on the upper right alignment key UR. It is formed horizontally at intervals. In the lower position display regions 52, 54, 56 and 58 and the first and third upper position display regions 51 and 55 from the left, a first blocking layer 60 capable of blocking light is provided in the position display regions 51 and 52. , 54, 55, 56, 58) respectively formed on the front surface. In addition, in the second and fourth upper position display regions 53 and 57 from the left side, letters UR indicating the upper right side are formed of a material capable of blocking light.

In addition, four second blocking layers 70 are formed in two rows in two rows between the upper and lower position display regions 51, 52, 53, 54, 55, 56, 57, and 58. The lower left and right lower second barrier layers 70 adjacent to the lower position display regions 52, 54, 56, and 58 are formed in a square shape having a length L1 on one side, and the upper left and upper right sides adjacent to the UR letters. The second blocking film 70 has the same shape and is formed by being separated into the first portion 71 and the second portion 72, respectively. Here, the first portion 71 is formed in a square shape having a length of one side L2, and the second portion 72 is formed in a rectangular ring shape around the first portion 71, and the second portion ( The outer edges of 72) are L3 and the width is L4.

FIG. 3 is a detailed view illustrating an upper left alignment key in FIG. 1.

As shown in FIG. 3, the overall structure is the same as in FIG.

On the other hand, unlike FIG. 2, letters “UL” indicating the upper left are formed in the fourth lower position display area 58 and the first upper position display area 51 from the left, respectively, and the remaining position display areas 52, 53, 54, 55, 56 and 57, the first blocking film 60 is formed on the entire surface.

In addition, of the four second blocking films 70, the second upper and lower right two second blocking films 70 adjacent to the UL letters are of different shapes and are formed by being separated into the first part 71 and the second part 72. . Here, the second part 72 of the upper left second blocking film 70 is formed in a square annular shape having one side length L1, and an opening having one length L5 is formed at the center of the second part 72. It is. The 1st part 71 is formed in the center of the opening part of the 2nd part 72 in the square shape of the length of one side L6. In addition, the first part 71 and the second part 72 of the lower right second blocking film 70 are the same as the first part 71 and the second part 72 of the second blocking film 70 of FIG. 2. It is shaped in size and shape.

The two second blocking films 70 facing in the remaining diagonal direction are formed in a square shape having one side length L1.

FIG. 4 is a detailed view showing the bottom right alignment key of FIG. 1 in detail.

As shown in Fig. 4, the overall structure is the same as Figs.

On the other hand, unlike FIG. 2 and FIG. 3, the letters LR indicating the bottom right are formed in the third upper position display area 55 from the left and the second lower position display area 54 from the left, respectively. The first blocking layer 60 is formed in the display regions 51, 52, 53, 56, 57, and 58.

In addition, the upper right and lower left two second blocking films 70 adjacent to the letters LR have different shapes and are formed by being separated into the first part 71 and the second part 72, among which the upper right second blocking film ( 70 is formed in the same size and shape as the upper left second blocking film 70 in FIG. 3, and the lower left second blocking film 70 is formed in the same size and shape as the second blocking film 70 in the lower right in FIG. 3. It is.

FIG. 5 is a detailed view illustrating a lower left alignment key in FIG. 1.

As shown in FIG. 5, the overall structure is the same as that of FIGS. 2, 3, and 4.

On the other hand, unlike FIG. 2, FIG. 3, and FIG. 4, in the first lower position display region 52 and the third lower position display region 56 from the left side, letters LL indicating the lower left side are formed, respectively. The first blocking layer 60 is formed in the position display regions 51, 53, 54, 55, 57, and 58.

In addition, the second left and right bottom blocking films 70 adjacent to the letter LL are formed in the same shape as the second blocking film 70 on the upper right side in FIG. 4.

Through the superimposition of the four alignment keys UR, UL, LR, and LL, an alignment pattern is formed in the device isolation region of the wafer, which will be described in detail below.

6 is a plan view illustrating an alignment pattern formed in an element isolation region of a wafer through the semiconductor element isolation mask of FIG. 1, wherein the alignment keys of FIGS. 2 to 5 are aligned at exactly one point.

As shown in FIG. 6, the alignment pattern 300 formed on the wafer is a shape in which the alignment keys UR, UL, LL, and LR shown in FIGS. 2 to 5 are superimposed, and each alignment correction pattern 700 is formed. ) Is a shape in which two second light blocking films 70 having different shapes formed of two parts 71 and 72 overlap each other in FIGS. 2 to 5.

In the four position display regions 500 formed at the upper and lower edges, patterns of UL, UR, LR, and LL letters indicating positions are respectively formed. In addition, four alignment correction patterns 700 are formed in the same shape between the upper position display region 500 and the lower position display region 500.

Here, the first portion 710 of the alignment correction pattern 700 has a square shape having one side length L6. In addition, the opening defined by the second portion 720 of the alignment correction pattern 700 has a square shape having one side length of L3-2 * L4, and the length of one side of the second portion 720 is L3, The width is L4.

At this time, L5 in Figures 2 to 5 should be greater than or equal to L2 and less than L3-2 * L4. If L5 is smaller than L2, another pattern having a rectangular ring shape is further formed between the first portion 710 and the second portion 720 of the alignment correction pattern 700.

If the alignment keys of FIGS. 2 to 5 are misaligned, the shape and size of the alignment correction pattern 700 are different.

Accordingly, the shape and size of the alignment correction pattern 700 may be measured by using the alignment measuring equipment, and the misalignment of the semiconductor device isolation region formed first in the semiconductor device manufacturing process may be corrected through the measured data.

Therefore, in the semiconductor device isolation mask according to the present invention having the alignment key and the method of manufacturing the semiconductor device using the same, the semiconductor device isolation mask is formed to be aligned so as to overlap the alignment key, so that the semiconductor isolation region is accurately aligned first on the wafer. The alignment of the other doped layers formed with respect to the isolation region can be more accurately formed. In particular, the accuracy of alignment can be improved by measuring the shape and size of the alignment correction pattern formed through the pattern of the alignment key.

Claims (15)

Transparent substrate, An active region formed in a central portion of the transparent substrate, The semiconductor device isolation mask is formed around the active area to define the active area, and includes a semiconductor device isolation region in the form of a square ring formed with a plurality of alignment keys. In claim 1, And one alignment key formed on each of four sides of the rectangular ring semiconductor device isolation region. In claim 2, And the alignment keys are formed at four corners of the semiconductor device isolation region. In claim 3, A mask for separating semiconductor elements having different shapes of the alignment keys. An active region in which a unit semiconductor element is formed, An isolation region defining the active region and formed in a square ring shape; And a plurality of alignment correction patterns formed in the device isolation region. In claim 5, The alignment correction pattern is a semiconductor element wafer formed on four sides of the square ring shape. In claim 6, And the alignment correction patterns are formed at four corners of the device isolation region, respectively. In claim 6, The semiconductor device wafer, wherein the alignment correction patterns are all formed in the same shape. Firstly exposing the photoresist film formed on the substrate using a device isolation mask having a plurality of alignment keys formed in the device isolation region; Moving the mask, Aligning the mask such that a part of the alignment key is positioned at a position of the partial alignment key during the first exposure; And secondly exposing the photosensitive film using the mask. In claim 9, The device isolation region is a semiconductor device manufacturing method of the square ring shape. In claim 10, And the alignment keys are formed on four sides of the square ring shape. In claim 11, And the alignment keys are formed at four corners of the semiconductor device isolation region, respectively. In claim 12, When the mask is moved downward in the shifting step, two alignment keys formed on the upper side of the device isolation region are replaced by two alignment keys formed on the lower side of the device isolation region in the first exposure step. A method of manufacturing a semiconductor device aligned in position. In claim 13, When the mask is moved to the right in the shifting step, the two alignment keys formed on the left side of the device isolation region are replaced by the two alignment keys formed on the right side of the device isolation region in the first exposure step. A method of manufacturing a semiconductor device aligned in position. The method of claim 14, Wherein each of the alignment keys has a different shape.