JPH04127551A - Inspection of exposure pattern - Google Patents

Abstract

PURPOSE:To remarkably lessen the inspection operation of an exposure pattern in man-hours by a method wherein the position of an alignment mark is detected before and exposure pattern is exposed to light, the coordinates of exposure pattern data and inspection mark data are corrected, the position of the inspection mark is detected, and the deviation of the inspection mark from the corrected inspection mark data coordinates is obtained by comparing them with each other. CONSTITUTION:The positions of aligning marks 2a-2d are detected. Data coordinates of an exposure pattern and inspection marks 3a-3d are corrected in accordance with the positions of the alignment marks 2a-2d. The exposure pattern is exposed to light in such an order that a light spot is made to scan each of chips starting from its left bottom corner. A chip is, for instance, 100mum square in size. When the inspection marks 3a-3e are scanned by a light spot, the positions of the marks 3a-3e are detected to determine the coordinates of the marks 3a-3e. When the exposure of all the region to light is finished, the obtained coordinates of the inspection marks 3a-3e are compared with the inspection mark data coordinates previously corrected by the positions of the aligning marks 2a-2d to obtain the quantity of deviation. The quantity of deviation concerned is compared with the alignment accuracy reference of an exposure pattern to judge if the exposure pattern concerned is defective or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method of inspecting an exposure pattern, and particularly to a method of inspecting an electron beam exposure pattern.

The purpose of the present invention is to provide a method for inspecting an exposure pattern before developing the exposure pattern.

This is an inspection method for creating an exposure pattern on a resist on a semiconductor substrate by electron beam drawing and inspecting the exposure pattern, in which alignment marks and inspection marks are formed on the semiconductor substrate in advance.

Prior to exposure of the exposure pattern, the alignment mark is scanned with an electron beam to detect the position of the alignment mark, and the exposure pattern data coordinates and inspection mark data coordinates are corrected based on the detected value. Thereafter, an exposure pattern is exposed based on the corrected coordinates, and the inspection mark is scanned with an electron beam to detect the position of the inspection mark, and the detected value is used for the above-mentioned correction. From &q to find the deviation by comparing with the mark data coordinates.

It consists of an exposure pattern inspection method that evaluates the deviation of an exposed exposure pattern.

The present invention also includes an exposure pattern inspection method in which the position of the inspection mark is detected after the exposure pattern is exposed.

Further, the present invention is configured by an exposure pattern inspection method that uses a single alignment mark and an inspection mark in common.

[Industrial application field]

The present invention relates to an exposure pattern inspection method, and more particularly to an electron beam exposure pattern inspection method.

An exposure pattern formed by electron beam writing on a resist coated on a semiconductor substrate is visually inspected using an optical microscope, a scanning electron microscope (SEM), or the like after the resist is developed.

In the case of electron beam exposure, before exposing a block (chip), the alignment mark is scanned with an electron beam, nine positions are detected, and the position is confirmed before exposure.

Superimposition of images may be deviated due to aberrations (distortion) of the electronic lens system or characteristics of the amplifier. Furthermore, as a phenomenon peculiar to electron beam exposure, deviation occurs due to charge accumulation on the substrate.

Although these deviations have some regularity, they vary depending on the pattern to be exposed and the exposure conditions.9 Usually, a vernier pattern is provided to check the alignment, but this does not necessarily guarantee alignment. , Therefore, the actual device pattern must be visually inspected. This test takes a long time and is difficult to produce quantitative data.

Therefore, it is desirable to inspect electron beam exposure patterns reliably in a short time.

[Conventional technology]

FIGS. 3(a) and 3(b) are diagrams for explaining a conventional example.

(a) is a plan view, (b) is an A-A sectional view, ■ is a semiconductor substrate, 2a to 2d are alignment marks, 5 is a concave electron beam resist 35a, 6 is a main scale pattern, and 7 is a sub-scale pattern. 11 represents a chip area, and 12 represents a scribe area.

In this example, an electron beam exposure is performed on a l-chip field, and alignment marks are formed at the chip corners.

The alignment marks 2a to 2d are 9, for example, chip area 1.
In the scribe area 12 approaching the four corners of 1, - side 5 μm
The electron beam resist applied thereon also has depressions 5a corresponding to the alignment marks 2a to 2d.

Furthermore, a main scale pattern 6 is formed on the semiconductor substrate l, for example, at one corner of the chip area 11.

The vernier pattern 7 is a pattern that is exposed together when the device pattern is exposed to the electron beam resist, is adjacent to the main pattern 6, and is used for alignment inspection.

First, prior to pattern exposure, alignment marks are detected.

FIGS. 4(a) to 4(C) are diagrams for explaining a method of detecting alignment marks.

FIG. 4(a) is a cross-sectional view including the alignment mark 2a,
The electron beam resist 5 has a recess 5a corresponding to the alignment mark 2a.

FIG. 4(b) shows a reflected electron signal when the electron beam resist 5 is scanned with an electron beam. A profile reflecting the depression 5a is obtained.

FIG. 4(C) shows a backscattered electron differential signal. The midpoint of the peak of this differential waveform is detected as the center of the alignment mark 2a.

Detection of such alignment marks is performed for the alignment marks 2a to 2d and in the X and Y directions, and from these alignment mark detection values, the gain for correcting the expansion and contraction of the chip and the rotation amount of the chip are calculated. The rotation to be corrected, the offset to correct the chip deviation, etc. are calculated, and corrections are made to the device pattern data coordinates to be exposed. Correcting is also applied to the vernier pattern data coordinates in the same way.

After that, the chip is exposed. In addition to exposing the device pattern, the vernier pattern is also exposed.

FIG. 5 is a schematic diagram showing an example of the exposure order within a chip.

The inside of the chip area 11 is divided into rectangular cells, scanned sequentially from the end, and each cell is exposed to light in a row (.

After exposure and development, the vernier pattern 7 is compared with the main pattern 6 on the substrate, and positional deviations are visually inspected using an optical microscope or a scanning electron microscope.

However, it is difficult to guarantee alignment throughout the entire chip using a vernier pattern at one location. Therefore.

The device pattern itself must be visually inspected, which takes a long time. If a large number of vernier patterns are placed within a chip, it is possible to obtain quantitative data on the entire area within the chip and grasp the overall picture of misalignment.
Their large number is problematic because it reduces the effective area of the device.

[Problem to be solved by the invention]

Therefore, in the past, there was a problem that it took a long time to visually inspect the exposure pattern after it was developed, and there was also a problem that the effective area of the chip was reduced due to the formation of the main pattern and the vernier pattern.

In view of the above problems, the present invention was developed after pattern exposure.

The present invention provides a method for evaluating positional deviation of an exposure pattern without waiting for development and visual inspection, and further includes:
It is an object of the present invention to provide a method for increasing the effective area of a chip by also reducing the area occupied by a test pattern within the chip.

[Means to solve the problem]

The above-mentioned problem is an exposure pattern inspection method for creating an exposure pattern on a resist 5 on a semiconductor substrate 1 by electron beam drawing and inspecting the exposure pattern. 2d and inspection marks 3a to 3e are formed in advance.

Prior to exposure of the exposure pattern, the alignment mark 2
A to 2d are scanned with an electron beam to mark the alignment mark 2a.
Detect the position of ~2d, correct the exposure pattern data coordinates and inspection mark data coordinates based on the detected value, and then perform exposure of the exposure pattern based on the corrected coordinates and remove the inspection mark. 3a to 3e are scanned with an electron beam to detect the positions of the inspection marks 3a to 3e, and the detected values are compared with the corrected inspection mark data coordinates to determine the deviation. The problem is solved by an exposure pattern inspection method that evaluates the deviation of the exposure pattern.

In addition, after the exposure pattern is exposed, the inspection mark 3
A to 3e are scanned with an electron beam to mark the inspection marks 3a to 3.
The problem is solved by an exposure pattern inspection method that detects the position of e.

Also, in parallel with the exposure of the exposure pattern, the inspection mark 3a is
The problem is solved by an exposure pattern inspection method that detects the position of ~3e.

In addition, 9 alignment marks 4a to 4d and inspection mark 4a
This problem can be solved by an exposure pattern inspection method that shares 4d.

[Effect]

In the present invention, the alignment mark 2a is placed on the semiconductor substrate 1 in advance.
2d and inspection marks 3a to 3e are formed, and 9 alignment marks 2a to 2 are formed prior to exposure of the exposure pattern.
d is scanned with an electron beam to detect the positions of the alignment marks 2a to 2d, and based on the detected values, the exposure pattern data coordinates and the inspection mark data coordinates are corrected. After that, the exposure pattern is exposed, and the inspection marks 3a to 3e are scanned with an electron beam to form the inspection marks 3a to 3e.
Detect the position of 3e.

The detected value is compared with the corrected inspection mark data coordinates to determine the deviation.

An inspection mark is formed close to the exposure pattern.

Furthermore, if the exposure of the exposure pattern and the scanning of the electron beam on the inspection mark are performed close to each other in time.

Before development, the positional deviation of the exposure pattern can be accurately evaluated based on the positional deviation of the inspection mark.

Also, in parallel with the exposure of the exposure pattern, the inspection mark 3a is
If the positions .about.3e are detected, the accuracy of detecting the positional deviation of the exposure pattern is good.

Furthermore, since the inspection marks 3a to 3e do not need to be as large as the main scale pattern or the vernier scale pattern, the effective area within the chip is not significantly reduced as in the conventional method.

In addition, after the exposure pattern is exposed, the inspection mark 3
A to 3e are scanned with an electron beam to mark inspection marks 3a to 3e.
By detecting the position of the exposure pattern, it is possible to know the positional shift that occurred during exposure of the exposure pattern.

Also, 1 alignment marks 4a to 4d and inspection mark 4a.
By sharing .about.4d, it is possible to reduce the area occupied by the 9 alignment marks and the inspection marks on the chip.

〔Example〕

FIGS. 1(a) and 1(b) are diagrams for explaining Embodiments I and II, in which (a) is a plan view, (b) is a sectional view taken along line A-A including alignment marks, and 1 is a Semiconductor substrate, 2a
~2d are alignment marks, 3a~3e are inspection marks.

Reference numeral 5 indicates a recess in the electron beam resist 5a, and reference numeral 11 indicates a chip area.

12 represents a scribe area.

Four alignment marks 2a to 2d are formed in the scribe area 12 at the chip corner, and five inspection marks 3a to 3e are formed in the chip area 11. Alignment mark 2
For example, each of inspection marks a to 2d and inspection marks 3a to 3e is 9.

Each recess has a diameter of 5 μm, and the thickness of the electron beam resist 5 is, for example, 1.0 μm.

Example 1 The alignment marks 2a to 2d are scanned in the X and Y directions using an electron beam with a slit width of 0.1 μm and a slit length of 3 μm, for example.
The positions (midpoints) of the nine alignment marks 2a to 2d are determined by scanning in the direction shown in FIGS. 4(a) to 4(c). Using these values, corrections are made to the exposure pattern data coordinates and the inspection mark (3a to 3e) data coordinates.

The exposure order of the exposure pattern is 9. For example, by the method shown in FIG. 5, each cell is scanned from the lower left of the chip. For example, the dimensions of the cell are 9.

It is 100 μm.

When the inspection marks 3a to 3e are scanned, the positions (midpoints) of the inspection marks 3a to 3e are determined by the same method as shown in FIG. 4, and their coordinate values are determined. When the exposure of the entire area is completed, the coordinate values of the inspection marks 38 to 3e just obtained are compared with the inspection mark data coordinates that were previously corrected using the positions of the alignment marks 2a to 2d, and the amount of deviation is calculated. demand.

This amount of deviation is compared with a reference value for alignment accuracy of the exposure pattern to determine whether it is good or bad.

Also, it is not necessary to scan the entire area with the electron beam (
Device pattern to be exposed and inspection marks 3a-3
Any area including e is sufficient.

According to this embodiment I, the deviation of the exposure pattern at a position close to the inspection mark can be determined with high accuracy.

Example■ Positioning is performed in the same manner as in Example I.

The order of exposure of the exposure pattern is that first, all device patterns to be exposed are scanned.

Thereafter, the inspection marks 3a to 3e are scanned with an electron beam to find the positions (midpoints) of the inspection marks 3a to 3e, and their coordinate values are determined. The coordinate values are compared with the previously corrected inspection mark data coordinates to determine the amount of deviation.

This amount of deviation is compared with a reference value for alignment accuracy of the exposure pattern to determine whether it is good or bad.

In this embodiment (2), it is possible to know the positional deviation that occurred during exposure of the exposure pattern.

By combining the method of Example I and the method of Example H, it is possible to obtain quantitative data regarding local positional deviations and temporal positional deviations, and to obtain quantitative data regarding positional deviations caused by equipment and process-induced positional deviations. You can also get information.

Figures (a) and (b) are those of Example 1. 4A is a diagram for explaining IV, (a) is a plan view, (b) is an A-A sectional view including alignment marks, ■ is a semiconductor substrate, 4a
4d represents an alignment mark/inspection mark, 5 represents an electron beam resist, 5a represents a recess, 11 represents a chip area, and 12 represents a scribe area.

Four alignment marks/inspection marks 4a to 4d are formed in the scribe area 12 at the chip corner.

In this example, the inspection mark is not provided in the chip area but in the scribe area, and also serves as both an alignment mark and an inspection mark.
A to 4d are recesses each having a diameter of, for example, 5 μm, and the thickness of the electron beam resist 5 is, for example, 1.0 μm.

Example ■ Similarly to Example ■, the positions of the nine alignment marks and inspection marks 4a to 4d are determined by scanning the electron beam in the X direction and the X direction over the nine alignment marks and inspection marks 4a to 4d.
midpoint). Using those values, we can determine the exposure pattern data coordinates and the alignment marks/inspection marks (4a to 4d).
) Add corrections to own data coordinates.

The exposure order of the exposure pattern is 9. For example, by the method shown in FIG.
The entire area including areas a to 4d is scanned with an electron beam from the lower left of the chip.

When the scanning reaches the alignment marks/inspection marks 4a to 4d, the positions (midpoints) of the alignment marks/inspection marks 4a to 4d are determined in the same manner as in Example I, and their coordinate values are determined. The coordinate values are compared with the previously corrected data coordinates of the alignment mark/inspection mark itself to determine the amount of deviation.

This amount of deviation is compared with a reference value for alignment accuracy of the exposure pattern to determine whether it is good or bad.

Embodiment 2 This is the same as Embodiment 2 until correction is made to the exposure pattern data coordinates and the data coordinates of the positioning marks/inspection marks 4a to 4d themselves.

The order of exposure of the exposure pattern is that first, all device patterns to be exposed are scanned.

After that, 9 alignment marks/inspection marks 4a to 4d are scanned with an electron beam, and 9 alignment marks/inspection marks 4 are scanned with an electron beam.
Find the positions (midpoints) of a to 4d and determine their coordinate values. The coordinate values are compared with the previously corrected data coordinates of the alignment marks/inspection marks 4a to 4d themselves to determine the amount of deviation.

This amount of deviation is compared with a reference value for alignment accuracy of the exposure pattern to determine whether it is good or bad.

In Examples ■ and ■, 1 alignment mark and inspection mark 4
Since the patterns a to 4d are formed in the scribe area, the pattern for inspection does not reduce the effective area of the chip.

Of course, the nine alignment marks/inspection marks 4a to 4d may be formed within the chip area 11 or near the device pattern.

The above embodiment is significantly different from the conventional example in that after the exposure pattern is exposed, the positional deviation of the exposure pattern can be evaluated immediately without waiting for development processing or visual inspection. Therefore, the number of inspection steps is significantly reduced, and defective products can be eliminated at an early stage.

Furthermore, quantitative data regarding one positional deviation can be accumulated, and exposure can be performed in accordance with the specificity of the apparatus and process.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to evaluate the positional shift immediately after exposure without developing the electron beam exposure pattern, compared to the conventional method of visually inspecting the pattern after development. This can significantly reduce inspection man-hours. Moreover, defective products can be eliminated at an early stage.

Also, regarding the positional deviation of the electron beam exposure pattern.

Quantitative data can be accumulated.

Furthermore, the area occupied by the inspection marks on the chip can be reduced.

[Brief explanation of the drawing]

FIGS. 1(a) and 1(b) are diagrams for explaining Example I, (2). FIGS. 2(a) and 2(b) are diagrams for explaining embodiments (1) and (2). FIGS. 3(a) and 3(b) are diagrams for explaining a conventional example. FIGS. 4(a) to 4(C) show alignment mark detection. In fig. ■ is a semiconductor substrate. 2a to 2d are alignment marks. 3a to 3e are inspection marks. 4a to 4d are alignment marks and inspection marks. 5 is a resist, and the electron beam resist 5a is a recess. 6 is the main scale pattern. 7 is a vernier pattern. 11 is a chip area. 12 is outside the chip area and is the scribe area (b) Arrow color A column I, Ia name Menme Tero Ome log 1 figure projection υm[, IIε explanation 1 Rohame room 2nd circle (b) , Conventional A column E theory e [Rq-me figure 3 Concave position alignment) htr mark paper output force stroke E theory 4. Ujiguchi $5
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Claims (1)

[Scope of Claims] [1] An exposure pattern inspection method for creating an exposure pattern on a resist (5) on a semiconductor substrate (1) by electron beam writing and inspecting the exposure pattern, the method comprising: Alignment marks (2a to 2) are placed on the semiconductor substrate (1).
d) and inspection marks (3a to 3e) are formed,
Prior to exposure of the exposure pattern, the alignment mark (
2a to 2d) are scanned with an electron beam to detect the positions of the alignment marks (2a to 2d), and based on the detected values, correction is made to the exposure pattern data coordinates and the inspection mark data coordinates, and then, The exposure pattern is exposed based on the corrected coordinates, and the inspection marks (3a to 3) are
e) Scan the top with an electron beam to mark the inspection marks (3a to 3e).
) and compares the detected value with the corrected inspection mark data coordinates to determine the deviation, thereby evaluating the deviation of the exposed exposure pattern. Method. [2] After exposing the exposure pattern, mark the inspection mark (
3a to 3e) are scanned with an electron beam to mark the inspection mark (3).
Claim 1 characterized in that the positions of a to 3e) are detected.
Exposure pattern inspection method described. [3] In parallel with the exposure of the exposure pattern, mark the inspection mark (3
Claim 1 characterized in that the positions of a to 3e) are detected.
Exposure pattern inspection method described. [4] The exposure pattern inspection method according to claim 1, wherein the alignment marks (4a to 4d) and the inspection marks (4a to 4d) are used in common.