KR19990066806A - How to improve microprocessors using pipeline synchronization - Google Patents

Abstract

The present invention improves out of order support of microprocessor computer systems through register management using synchronization of multiple pipelines, and allows first and second processing elements—each processing element to set general purpose registers and control registers for each processing element. It provides a system and method for providing processing of a sequential instruction stream of a computer system having its own state, which is determined by. At any point in time during which the sequential instruction stream is being processed by the first processing element, if it is advantageous for the second processing element to take over processing of the same sequential instruction stream, the first and second processing An element processes a sequential instruction stream and may execute the same instruction, but only one of the processing elements may change the overall structural state of the computer system, which is determined by a combination of the first and second processing element states. The second processor will have more pipeline stages than the first ordered processor, which will feed to the first processor, reducing finite cache loss and improving performance. Processing and storing the second processor result does not change the structural state of the computer system. The result is stored in the GPR or personal memory buffer of the second processor. Resynchronizing the states with the coprocessor occurs based on an invalid op, delay, or calculated specific gain for processing by the coprocessor used as the speculative coprocessor. In an alternative embodiment, the processing allows two processors to transmit and store structural state changes for future use as required by other processors if a processor that later changes the overall structural state of the computer system is changed. Is generalized to

Description

How to Improve Microprocessors Using Pipeline Synchronization

The present invention relates to a computer system, and more particularly, to a method for improving the performance of a microprocessor computer system incorporating a coprocessor using pipeline synchronization.

The performance of current microprocessors is very limited due to the finite cache effect on most of the critical workloads. The finite cache effect includes all the causes of performance degradation that will be resolved if the microprocessor's first level cache grows infinitely. The amount of time the microprocessor spends waiting for operand data from off-chip storage is in most cases equal to the amount of time spent executing instructions. This is especially true for workloads associated with database and transaction processing.

Many current microprocessor designs aim to reduce the finite cache penalty. Large caches, multi-level caches, fast multichip modules, out of order execution, and instruction prefetch are widely used and are considered the most successful. Operand prefetch has also been used successfully with certain workloads with or without conventional random processing. However, prefetching has no special effect on database and transactional workloads. Large caches reduce the finite cache effect, but further improvements are limited in this area by the cost-performance relationship of increased die size or chip count. Current random execution techniques greatly reduce the finite cache effect, but the losses associated with these techniques appear in the form of reduced processor clock frequencies and increased design complexity. Thus, there is a need to improve the microprocessor design to substantially reduce the cost of implementing the random execution design previously considered desirable.

Glossary of Terms

CPI: Machine cycle per instruction.

SFE means the speculative fetch engine provided by the present invention.

uPCore: Balanced microprocessor design for tradeoff between cycle time, design complexity, and infinite L1 cache CPI.

The present invention is used in a microprocessor computer system design method and more particularly in a computer system having a combined coprocessor, and provides a method for improving system performance using pipeline synchronization. The present invention improves out of order support and provides a computer system and in particular a microprocessor and a coprocessor coupled to the microprocessor, wherein the coprocessor provides an inference engine for achieving a reduction in finite cache loss. Provides the ability to use large caches and multilevel caches for computer systems with achieving system performance improvements.

An improved preferred embodiment provides improved microprocessor support through register management using synchronization of multiple pipelines. These improvements are inferential fetch engines (SFEs) that have multiple execution elements that work with the core microprocessor, which must process instructions in order, fetching them first if necessary and then simultaneously Can handle superscalar techniques such as performing a load), random execution method, synchronization method with multiple microprocessors, and storage layer shared by both SFE and microprocessor core (uPCore) is achieved by providing a register management process that enables the generation of speculative memory references to the storage hierarchy.

Figures 1a and 1b are intended to provide the same description as provided by Patent No. 4,901,233 granted to Liptei of IBM, which patent was developed by IBM, after IBM's conventional mainframe and Intel's Pentium microprocessor, It is intended to illustrate the limitations of the prior art, which is widely used in the Alpha microprocessor of Digital Corp. and the UltraSparse microprocessor of Sun Microsystems.

2 shows a schematic overview of a preferred embodiment.

3 shows the details of the SFE and the interface of the SFE with a memory buffer, a cache, and a uPCore. Also shown is the preferred hardware for routing instructions and operand fetches of SFEs through the cache shared by the SFEs and uPCores.

4 shows in more detail the synchronization unit between the uPCore and SFE.

5 shows a detailed refinement to the invention of register renaming of LipTay for synchronization between uPCore and SFE.

6 illustrates preferred hardware for uPCore.

FIG. 7 illustrates in detail the interaction between the inference engine and the microprocessor uPCore in a data flow diagram to illustrate the methodology employed by the present invention for improving performance.

<Explanation of symbols for main parts of drawing>

10: computer system

12: main memory

14: cache memory system

16: instruction cache

18: data cache

20: instruction buffer unit

22: instruction register unit

24, 26: General Purpose Execution Unit (GPE)

28; Storage buffer unit

30: general purpose register array

31: command queue

32: register management system

36: interrupt control element

The uPCore and the SFE are both processing elements. The system processes a sequential instruction stream in a computer system having a first and a second processing element, each processing element having its own state determined by the setting of its general purpose registers and control registers. If at any point in the process it is advantageous for the second processing element to take over the successive processing of the sequential instruction stream, the first and second processing elements process the sequential instruction stream, both of which may execute the same instruction. However, only one of the processing elements (uPCore in this preferred embodiment) can change the overall architectural state of the computer system determined by the combination of states of the first and second processing elements.

In a preferred embodiment, the second processor has more pipeline stages than the first order processing element, allowing for random execution, thereby reducing finite cache loss and improving performance. In a preferred embodiment, processing and storing the results of the second processing element does not change the structural state of the computer system. The result is stored in a general purpose register or personal storage buffer. Resynchronization of the two processing element states occurs according to an invalid op, stall, or calculated specific gain for processing when using the coprocessor as an out of order coprocessor (SFE).

The SFE interfaces with the uPCore, so the present invention is easily implemented by the SFE and the first processor uPCore on the same silicon chip. Multichip implementations are also possible and compatible with current embodiments of the present invention. The uPCore has a conventional structure and in the preferred embodiment maintains the structural state of the combination system, while in the generalized version of the mirror version the responsibility for maintaining the structural state is changed or shared by both. In a preferred embodiment of the present invention, the action called by the SFE does not directly change the structural state of the uPCore. The SFE is used to generate a storage reference that primes the instruction and operand data in the cache of the combination system prior to the uPCore using the instruction and operand data. These improvements extend system performance that can be achieved by conventional register renaming schemes such as those disclosed in US Pat. Nos. 4,901,233 (hereinafter referred to as Liptay) and 4,574,349.

These and other improvements are disclosed in the following detailed description of the invention. With reference to the detailed description of the invention and the accompanying drawings, it is possible to better understand the advantages and features of the present invention as compared to conventional designs first developed and widely implemented by IBM.

Prior to discussing the preferred embodiment of the present invention in detail, a conventional unordered microprocessor design technique first developed by IBM and described in Ripta Patent No. 4,901,233 will be described. 1 shows a conventional conventional random order microprocessor design technique that is disclosed in US Pat. No. 4,901,233 and teaches the use of a register management system (RMS). RMS is used for precise post-branch recovery and also allows for the use of more general-purpose physical registers than the physical registers named architecture systems. The use of a register management system is essential to enable random execution. It should be appreciated that random execution significantly reduces the finite loss of cache, which is at the heart of the present invention. Preferred embodiments disclosed in US Pat. No. 4,901,233 include modifications to a basic pipeline with prior art processor designs. This modification is necessary to integrate the RMS into the overall system and to create an instruction pipeline that is longer than the instruction pipeline of the ordered design (ie more steps) or contains more logic for each step. The preferred embodiment of US Pat. No. 4,901,233 enables the improvement of both infinite L1 cache CPI and finite cache CPI over conventional ordered design. The present invention does not exclude the use of random order techniques to improve the infinite L1 CPI, and achieves a more desirable balance between design complexity and random order support within the main instruction execution pipeline. To ensure that these random techniques are used in a limited way. The present invention is directed to the use of a random order technique that reduces the finite L1 CPI adder without any increase in the uPCore pipeline length or the length of each step in the pipeline. The overall result is significantly better system performance than US Pat. No. 4,901,233 because of the insignificant improvement in infinite L1 cache CPI achieved in US Pat. No. 4,901,233 in the case of database and transactional workloads. This is because it is improved to provide greater performance. In addition, the present invention isolates the register management system from the main instruction processing pipeline when the uPCore is implemented in a sequential design, greatly reducing the design complexity for all issues related to the sequential instruction processing. You can. 1A and 1B, which are implemented in US Patent No. 4,901,233, will be described based on the above contents.

The RIPTA invention is a register management system for a computer system having a structural design requirement of a plurality of addressable (logical) specific registers, such as general purpose registers (e.g. n general purpose registers). Various elements of the riptain design are used in the system according to the invention to be described below. A register array RA having m registers, where m is greater than n, is provided to perform the function of the n general purpose registers. In an exemplary embodiment, a system having 16 general purpose registers in accordance with the well-known IBM system / 370 architecture is disclosed in US Pat. No. 4,901,233, which is still used in current S / 390 machines to this day. The RA provides dynamic allocation of specific RA locations to perform the function of the structure register. Once a particular register allocation function is completed, the location in the RA can be released and reassigned to the same structure GPR or another structure GPR with appropriate procedures.

The register management system is not dependent on the entire computer architecture and can be implemented under various circumstances as is used in current microprocessor designs. Accordingly, the computer system 10 shown in FIGS. 1A and 1B may include a main memory 12 connected to a cache memory system (CMS) regardless of whether it is a mainframe processor or a microprocessor. Of course you have. The cache memory system 14 may be configured in any suitable manner, but in the present embodiment, the cache memory system 14 is connected to the main memory 12, and each instruction performs a separate operation for an instruction operation and a data operation. Shown as cache 16 and data cache 18. In a dependent arrangement, the hierarchical memory design provides one or more levels in the cache memory to provide both memory speed and memory size advantages, which are not shown in FIGS. 1A and 1B, although As shown in FIG. 2, this does not contradict the present invention.

As shown in FIGS. 1A and 1B, an instruction is transferred from the instruction cache 16 to the instruction register unit 22 through the instruction buffer unit 20. For illustrative purposes, the instruction register unit 22 has one or more individual instruction registers, and the preferred number of such instruction registers is two, three or four.

A general purpose execution unit that functions as an execution unit may be designed according to the field of arithmetic or logic, scalar or vector, scalar or floating point type, etc. to be performed. Since any device having a general purpose register unit all uses a general purpose register (GPR), the present invention can be applied numerically or to many variations in terms of the functional layout and design of the general purpose execution unit of a computer.

For illustrative purposes, the riptain system is shown with general purpose execution units (GPEs) 1 and 2, denoted by reference numerals 24 and 26, respectively. The general purpose execution unit 24 has an output connected to the memory buffer unit 28, and the memory buffer unit 28 has an output connected to the data cache 18. The general purpose execution unit 24 may be a substantially single execution unit or may be a combination of units as shown in this embodiment, and the unit 24 generates a result, which results in a memory buffer (which is held until instruction completion). And then stored in memory. The general purpose execution unit 26 has an output connected to the general purpose register array 30 according to the invention. The general purpose execution unit 26 executes instructions which do not immediately be stored, but which produce the result required to be available in a register. An instruction stack or queue 31 is provided to receive instructions from the instruction register unit 22 and send these received instructions to the appropriate GPE 24 or GPE 26. Various types of multiple execution units may be used with a single RA and register management system. RA 30 includes 32 dynamically assignable physical registers that perform the function of the 16 general purpose registers recognized by the above structure.

The RA 30 is controlled by the register management system 32 (RMS) via the control bus 34 and provides status information to the RMS. The RMS 32 is connected to several different systems to receive and provide various types of status information. Interrupt control element 36 is coupled to instruction register 22, RMS 32, and RA 30 to handle proper handling of interrupts and to preserve required state information.

RMS 32 is coupled to instruction register unit 22 and GPEs 24 and 26 for the purpose of following instructions from issuance through the execution and allocation of registers for input and output operands.

The computers of FIGS. 1A and 1B are connected to receive instructions from the instruction register unit 22 and have an instruction queue 50 with outputs for the instruction address computation element (I-ACE) 52. I-ACE 52 is also coupled to receive input directly from RA 30 and has an output coupled to instruction cache 16. The command queue 50 is connected to provide status information to the RMS 32.

The computer of FIGS. 1A and 1B has an address queue 60 connected to receive output from the instruction register unit 22. The output of the address queue 60 is connected as an input to the data address calculation element (A-ACE) 62. D-ACE 62 is coupled to RMS 32 to provide status information.

The output of the D-ACE 62 is connected to an address fetch queue 64 which, as an input to the first output and address memory queue 66, is connected as an input to the data cache 18. Has a second output connected. Address storage queue 66 has an output coupled to data cache 18 and coupled to RMS 32 to provide status information.

The computer has a floating point arithmetic unit 70, which is also coupled to the RMS 32 to provide status information. As described below, it should be noted that the RMS 32 may work with units and registers that are not associated with the RA 30. For example, one RMS can work with more than one register array. More specifically, one RMS can control two RAs that can in turn be connected to multiple execution elements of the same or different types.

Input to the floating point unit (FPU) 70 is provided by the floating point instruction queue 72 and the floating point data register 74. Floating point instruction queue 72 receives input from instruction register 22. Floating point data register 74 receives input from data cache 18 and FPU 70. The output of the floating point unit 70 (FPU) is connected to a memory buffer unit 76 having an output whose output is connected to the input of the data cache 18.

In more detail, it will be appreciated that the system to be described in the present invention can be used effectively where a large cache and multiple levels of cache can be provided as shown in FIG. The present invention improves the performance of existing caches, and the speculative fetch operation improves the miss rate of each level of cache. The overall performance gain should be measured in comparison with the performance that can be achieved in many cases when the number of on-chip caches is increased by a silicon size SFE. An example where such a comparison is not necessarily valid is in the case of the L1 cache, because in the case of the L1 cache, the cycle time limit is generally the decisive limiting factor. Preliminary experiments have shown that using an SFE of approximately 1/4 to 1/2 of the on-chip second cache size provides a performance improvement of 15 to 20%.

Figure 2-Preferred Embodiment

As in the preferred embodiment of the present invention shown in FIG. 2, the interconnection of the components is a variety of interfaces, such as the interface between the uPCore 200 and the synchronization unit (SU 201), between the SFE and the instruction cache and data cache 203. Provided by The cache memory system may be configured in any suitable manner, but in the present embodiment, cache memory having one or more levels in the cache memory (for example, 203 ', ⃛ 203 '') is shown as a combined instruction and data cache 203 coupled to the main memory 204 of the hierarchical memory providing both memory speed and memory size advantages in a dependent arrangement, This hierarchical memory design does not contradict the present invention. Split instruction and data caches are also inconsistent with the present invention.

Any number of uPCores (200, ⃛ , 200 ', ⃛ , 200 '') represents any number of SFEs (202, ⃛ , 202 ', ⃛ , 202 ''). The SFE may be associated with a single uPCore at any given time, but may only change the association to any other uPCore after the synchronization function has been performed. Each SFE is associated with one memory buffer and one SU. For example, 201 ', 202' and 205 'are used together to provide the required SFE functionality. Any number of SFEs can be associated with a single uPCore at the same time. The preferred embodiment has a single SFE and a plurality of uPCores.

Prior to the detailed hardware description of the preferred embodiment, it can be seen from FIG. 2 that an alternative, generalized embodiment in which uPCore may operate differently. Generalized FIG. 2 performs the same functions as shown and described herein, but also in the present invention even when structural control alternates between 200, 200 ', 200' 'and 202, 202', 202 ''. The exact same function as described in detail is performed.

Thus, the preferred embodiment alternates with alternative generalized embodiments, where the first conventional processing elements uPCore 200, 200 ', 200 &quot; and the second processing elements SFE 202, 202', 202 &quot; It is a particular preferred example of having the machine's structural state control .. In the preferred embodiment shown in Figure 2, the first processing element has the control of the structural state and processes most of the instructions in the sequential instruction stream in order. Thus, a method of processing a sequential instruction stream in a computer system having a first and a second processing element, wherein each processing element has a state determined by the setting of a respective general purpose register and a control register, is described in detail. Begin by sending an initial instruction to one of the processing elements, the first processing element (eg, reference numeral 200.) Computer System Architecture Status Processing of the sequential instruction stream is continued using a first processing element that sends any change in the second processing element, but during the processing of the sequential instruction stream by the first processing element (e.g. uPCore 200). At any point in time, for example, if it is beneficial for a second processing element, such as SFE 202, to begin successive processing of the same sequential instruction stream, the second processing element of the computer system may recover the transmitted state and The processing of the sequential instruction stream with a second processing element starts a continuous process of the same sequential instruction stream.

The second processing element then sends all changes in the structural state of the computer system required by the first processing element to the first processing element.

In both the alternative embodiment for alternating control and the preferred embodiment of the present invention, the first and second processors may execute the same instruction, but only one of the processing elements is the first and second processing. It is possible to change the overall architectural state of the computer system, which is determined by the combination of element states. In a preferred embodiment of the invention, the combination is determined by the first processing element. Although in an alternative embodiment the structural state of the system may be determined in whole or in part by the state of the second processing element, in a preferred embodiment of the present invention the operation of the second processing element SFE does not change the structural state of the system. . In a preferred embodiment of the present invention, the uPCore pipeline handles most of all sequential instructions in order, while the SFE primes the cache shared by uPCore and SFE, and has uPCore with control of the structure state. The finite cache loss is reduced if the SFE preprocesses the instructions as the result of the SFE is stored in a separate private memory buffer while preprocessing the instructions used to perform resynchronization as often as possible.

Switching of the rescued state does not occur in the above preferred embodiment, while control of the rescued state is switched in the alternate control embodiment.

In a generalized method, each of the first and second processing elements has a state determined by the setting of its own general purpose register and a control register, and may execute the same instruction while processing the sequential instruction stream, but among the processing elements Only one can change the overall structural state of the computer system, which is determined by some combination of the first and second processing element states, wherein the processing element controlling the structural state is changed from the first processing element to the second processing element and It may be changed from the second processing element to the first processing element. This process sends to the second processing element any change in the structural state of the computer system required by the second processing element and, at a given point in time, for the structural state for the second processing element. Accumulating for use, the first processing element is used to process the sequential instruction stream for processing initiation. Then, if it is determined by the first processing element that it is beneficial for the second processing element to take over the continuous processing of the same sequential instruction stream at any point in the processing of the sequential instruction stream, then the second processing element Recovers the cumulative structural state previously transmitted from the first processing element, and processes the sequential instruction stream to take over processing of the same sequential instruction stream. While the second processing element controls the processing of the sequential instruction stream, the second processing element may use any change to the structural state of the computer system required by the first processing element at a predetermined point in time to be used in the future. And transmit the change to the first processing element for accumulation and use. Control may change again, wherein at any point during the processing of the sequential instruction stream by the second processing element, the first processing element resumes control and takes over the continuous processing of the same sequential instruction stream. If so, the first processing element recovers the cumulative structural state previously transmitted from the second processing element, and processes the sequential instruction stream to take over the subsequent processing of the same sequential instruction stream.

The first processing element and the second processing element may function as multiple processors. The first processor may also include a plurality of first processing elements capable of functioning as a multiprocessor with a single SFE or multiple SFEs as shown at 200, 200 'and 200' '. However, multiple SFEs are not used with a single uPCore. In other words, the multiprocessor may function with a combination of sets of one or more first processing elements and at least one second processing element. In a preferred embodiment, synchronization capabilities in the form of one synchronization unit SU 201, 201 ′, 201 ″ are provided for each of the second processing elements. The SU processes the instruction stream by determining when the second processing element SFEs 202, 202 ′ and 202 ″ start processing the same instruction as the instruction being processed by the first processing element uPCore. Therefore, one sync unit is provided for each SFE, and the SU determines when the SFE starts processing the same instruction or the next instruction of the processing stream being processed by uPCore. The SU determines when instruction processing by the SFE processing element should be stopped or ignored. This determination is made by a calculated benefit determination for the entire computer system having inputs provided from the first and second processing elements to the synchronization unit. The input may be provided immediately to the synchronization unit or from information stored in a system in which the counters 407 and 408 provide the information, as in FIG.

If there is a stall determination while processing the instruction by the first processing element as in step 709 of FIG. 7, the sync unit determines when the second processing element starts processing the same instruction as the instruction being processed. do. When there is an operation when the second processing element is not designed to handle, i.e., when there is no valid op available (707), the synchronization unit during the processing of the instruction processing element may cause the synchronization unit to resynchronize the SFE and uPCore states. Determine whether to resynchronize the structural state of the computer system with the state of the second processing element. If it is determined that the second processing element does not provide any gain (specific gain determination 208) to the computer system during processing of the instruction stream, then the synchronization unit resynchronizes the state of the second processing element with the structural state of the computer system. Decide if you want to. All of the decisions illustrated by 707, 708, and 709 of FIG. 7 are not only a determination as to when resynchronization is performed by the synchronization unit, but also as to which processing element resynchronizes the state. The processor SFE, which preprocesses the instructions, stores its results in a private general purpose register or memory buffer 205, 205 'or 205 &quot; associated with it. Since this memory does not affect the structural state of the other processing elements, these separate synchronizations allow the SFE to improve the performance of the processor handling most of the instructions in the sequential stream, which is processed by the first processing element. The same or next instruction of the stream being processed may be processed, and the SU may determine when instruction processing of the second processing element should be stopped or ignored. The first processing element fetches data from the data cache and the instruction cache shared by both the first and second processing elements for fetching purposes.

The method of the preferred embodiment of the present invention allows the SFE to be used to prime the cache for the first processing element and to preprocess the sequential instruction stream to handle the preprocessing as an out of order processor. During resynchronization and when instruction processing by the second processing element is to be stopped or ignored, the second processing element purges the results of some and all of the preprocessing of the instruction stream for the first processing element before resynchronization. do.

Thus, in the preferred embodiment it can be seen that the SFE, synchronization unit and two uPCores (meaning plural) as well as the personal memory buffer 205 for the SFE 202 are used in the method described above and illustrated in FIG. . The synchronization unit 201 includes the state of the SFE 202, as shown in FIG. Possible states are A, running, B, purging, resynchronization C with uPCore 200 of SFE, and resynchronization D with uPCore 200 'of SFE. The initial SFE state is C. In state C, the SFE receives the most recently retired instruction address from uPCore 200 and prepares to begin random execution at that address. The synchronization unit 201 continuously monitors the interface of the SU to the uPCore for indicating that the uPCore has been delayed by a cache miss using each uPCore functioning with the SFE. uPCore is running and continues to reference cache memory and main memory via interface 210. Instruction and operand data is returned from the instruction and data cache 203 to uPCore via an interface.

When the register management system of the SFE loads the contents of the SRAL associated with the uPCore into the DRAL of the SFE, a state change occurs from resynchronization to execution of the SFE (state A). Upon entering the SFE execution state, the SFE initiates instruction fetch and execution at the most recently received instruction address from the uPCore via the interface 206. When the instruction designated by the same instruction address is evicted, the GPR state of the SFE reflects the same state as that of the uPCore. While the SFE is running, the results of the GPR received through the interface 206 continue to be written to the general register array, but the register management system associates these results with a Synchronization Register Assignment List (SRAL). The result of the GPR is used only by instructions executed in the SFE after synchronization occurs. In this way, the SFE holds a separate image of the GPR state of each uPCore associated with it, which can be accessed later. Meanwhile, the RMS of the SFE updates the image of the GPR used for the SFE execution of the instruction stream using only the result of the SFE execution.

Immediately after the SFE enters the execution state, when random instruction execution begins, uPCore continues to fetch its instruction from its data cache 203 at its own pace, where the data cache 203 Includes the inference engine processing element SFE storage reference supplied to the cache storage 203 of instructions and operand data prior to use by the conventional uPCore processing element. In a preferred embodiment, exclusively designed as an ordered processor or a processor optimized for ordered processing, or substantially less than 95% of all instructions can handle the processing of instructions that do not yield a predicted gain. Can be a processor. Therefore, pipeline delay may occur in case of L1 cache miss. Since the SFE can perform random execution, the SFE can continue to execute past instructions that cause delays. During the time that the SFE is running, a fetch reference is generated that is sent to the instruction and data cache via interface 207 and to a memory buffer through interface 208. If the cache and storage buffer do not have the desired data, a cache miss occurs. The instruction and operand are returned via interface 207 if there is no associated entry in the memory buffer, and if there is an associated entry in the memory buffer, then returned to the SFE via interface 208. In this way, the result of the instruction stored by the SFE can be used in subsequent instructions executed on the SFE without changing the structure state of the uPCore and cache. All memories of the SFE are stored in the memory buffer.

The synchronization unit monitors the operation of the SFE via the interface 209. If the SFE encounters an interrupt or exception that is not designed to execute, handle or otherwise handle random support instructions, then it is indicated on interface 209. Thereafter, the synchronization unit causes the SFE to be in the erased state B of FIG. The sync unit also monitors instruction decode of uPCore and instruction retirement of SFE. If there is no longer a valid operation 707 or it is determined that the SFE does not provide a speculative prefetch gain 708, it is assumed that the SFE is far behind the uPCore implementation, in which case it is also in erased state (B). If the uPCore currently associated with the SFE is still being delayed at decision point 709, it is prevented from being erased, and the SFE remains running. Many other methods of indicating the SFE gain can be used to determine when the SFE should enter the erased state and are not inconsistent with the present invention.

Once the SFE enters the erased state B, it remains in this state until all instructions, some and part of the instructions, are erased from the SFE's data path and control structure. During this time no request is sent to the instruction and data caches. The SFE may leave the erased state and move to either the C or D state once the condition is achieved (706). The SFE may be resynchronized with the uPCore 200 or the uPCore 200 ′. The choice 704 between these two operations, determined by the SFE, can be made based on all the various factors that do not contradict the invention. The preferred embodiment of the present invention uses a simple representation of uPCore most recently synchronized with the SFE, in which case the SFE uses another uPCore to perform synchronization. The same uPCore may be selected multiple times through decision point 704 using different algorithms. Once resynchronization is complete, the state changes back to the running state and the cycle begins again.

Inferential Fetch Engine (SFE)

SFE uses conventional random processing and also uses a specific function or specific technique called superscalar technique to generate speculative operands and instruction fetches. Such techniques include register renaming, instruction reordering, completion scoreboarding, and the like. SFE can be implemented in a wide variety of ways. Criteria for optimal design include cycle time and area constraints that are very different from the random generation design of the current generation. 3 details the interface of the SFE to the SFE and other elements of the system. A very simplified diagram is intended to highlight the interaction of the new register management system (RMS) with a generic register array and instruction processing pipeline. This is similar to FIGS. 1A and 1B but with significant differences. First, there is an additional interface 306 that forms part of the interface 206 between GPR and uPCore. This interface 306 is used to convey the update of uPCore GPR to the SFE. Secondly, the RMS 301 of the present invention has been modified to include the use of Sync Register Allocation List (SRAL). Third, memory for the memory hierarchy is transferred to the memory buffer 205 instead of to the instruction and data caches, as disclosed in US Pat. No. 4,901,233 to Ripta et al. In the SFE, the data stream is continuously sent to the memory buffer 205 from the U.S. Patent No. 4,901,233 granted to Ripta et al as illustrated in FIG.

Interfaces 302, 303, 304, and 305 form part of interface 209 and carry a sync address, a purge indicator, a resynchronization indication, and a decoded instruction indication, respectively. The synchronization address is used by the SFE as a starting point for instruction fetch and execution immediately after the SFE is resynchronized with the structure state of the uPCore. The erase SFE indication causes the SFE to discard all command results and partial results and to clear the contents of the memory buffer of the SFE. The resynchronization indication is used by the SFE to determine which uPCore the SFE should be synchronized with and when the resynchronization should occur. The SFE uses an instruction completed interface to indicate to the SU that the instruction was successfully decoded. The SU uses this information to determine whether the SFE is providing speculative fetch gain. The SFE sends an instruction and operand fetch request to the instruction and data cache via interface 307 and to a storage buffer via interface 308. The speculative fetch sent over interface 307 is made by the SFE before the point where uPCore requires the same fetch when restarting execution after a delay. In this way, uPCore achieves the improvement in latency required for these fetch requests because the desired line is recently accessed and installed at the closest level of cache.

Since SFE is independent of the structure state of uPCore, the implementation of random order processing is free from many structural concerns. This improves the schedule and reduces the impact on the cycle time of the overall design. The implementation risk associated with SFE is now completely separate from uPCore. SFE can be optimized for the generation of inferential fetches that are not possible with uPCore needed to meet the needs of a large and diverse instruction set. SFE need not implement any instructions, exception handling operations, or recovery algorithms that are not frequently used. In case of any of these infrequent events, the SFE stops executing the instruction stream and marks it in the sync unit. uPCore eventually gets out of delay and handles this in a much simpler way of ordered design if an infrequent event continues.

The SFE design is fast, but must be optimized to decode and issue a large number of instructions that are not necessarily true for infinite CPI. The SFE can be designed with a long instruction pipeline without having to consider the effects of infinite L1 cache performance significantly compared to the conventional design. With both SFE and uPCore, the performance of the entire system's infinite L1 cache depends only on the uPCore pipeline, not SFE.

According to the design of the present invention, operand prefetching does not need to be performed by uPCore, and the SFE system, if necessary, eliminates the above described features of the present invention and the associated complexity emerging from uPCore. In some cases operand prefetch may need to be maintained within uPCore, which is not inconsistent with the present invention.

Details of the innovative change to RMS are illustrated in FIG. 5 in which the SFE maintains a Sync Register Allocation List (SRAL) for each uPCore associated with it in accordance with a preferred embodiment of the present invention. The RMS of the present invention, including extensions for the use of SRALs, is not dependent on the overall computer architecture and may be implemented under various circumstances. Thus, without limiting the scope of the present invention, the SFE shown in FIG. 3 in accordance with the present invention is described as conforming to IBM's System 390 architecture with 16 general purpose registers (GPR). In conjunction with the RMS, the GPR register array dynamically allocates specific register allocations at specific RA locations to meet the functionality of the structured registers. Once the function of a particular register is complete, that location in the RA can be released and reassigned as the same or another GPR through appropriate procedures.

In an embodiment of the present invention, the RA includes 48 dynamically assignable physical (physical) registers to satisfy the 16 GPR functions recognized by the structure. A decode register assignment list (DRAL) is used when an instruction is decoded to translate a GPR assignment into an RA assignment. As each instruction is decoded, the GPR referenced by the instruction is retrieved from the DRAL to determine which of the RA positions are assigned to the GPR, and when a new RA position is assigned to receive the result, the DRAL is updated to reflect this assignment. do. In this way, each instruction that uses a GPR is specified by DRAL to find the RA location assigned to the most recent instruction to refer to that GPR.

The back-up register assignment list (BRAL) allows you to process each of one, two or three conditional branches without waiting. It has the same structure as DRAL and is connected to DRAL so that all contents of DRAL are copied to BRAL or vice versa during one cycle. This transmission is controlled by the logic unit 505. For example, it is used when a conditional branch for storing the contents of a DRAL is encountered, when it is confirmed that the guesses about whether a branch has been taken are wrong.

The array control list (ACL) is coupled to receive status information from the rest of the RA and SFE and to transmit control information. The logical unit 505 controls the ACL and coordinates the operation of the ACL, DRAL and BRAL. For each RA that supports GPR, there is an ACL register that stores status information associated with the RA. There is one entry for each register position in the array.

Adding SRAL to the RMS is very important to the function of the SFE and therefore also very important to the present invention. SRAL has the same structure as DRAL, and SRAL is connected to DRAL so that all contents of SRAL are copied to DRAL during one cycle.

One SRAL is provided for each uPCore associated with the SFE. If uPCore generates GPR and CR updates, these GPR and CR updates are sent to the SFE via interface 206. The result may be delayed for one cycle to minimize cycle time impact on uPCore. The GPR update is recorded in the RA, and the SRAL associated with the uPCore source is updated to specify the RA location. In the embodiment of the present invention, since uPCore normally functions as a sequential execution design, the GPR update on interface 206 reflects the GPR update for the retirement instruction and can therefore always be written to the same RA currently indicated by SRAL. . During resynchronization operation, 16 new RA entries must be supplied to SRAL to ensure that successive updates from uPCore can be accepted. In the current embodiment, this is not a problem because SFE erasure that releases all other RA entries not associated with SRAL always precedes the resynchronization operation. The uPCore GPR state of the SFE copy in SRAL is always delayed by at least one cycle. If the SFE needs to be synchronized with the uPCore, then simply moving the SRAL contents to the DRAL accomplishes this. This behavior is similar to the BRAL used by Liptei to recover microprocessor state in the case of a mis-predicted branch.

The function of the SRAL of the present invention is very different from the BRAL of Liptei. First, because it can be used for uPCore, SRALs are written to GPR updates from other instruction processing pipelines.

Secondly, the trigger for moving the contents of the SRAL to the DRAL is very different from the trigger for moving the contents of the BRAL of the RIPTA to the DRAL. In the case of RIPTA, a misprediction branch is triggered. In the present invention, it will be understood that an indication that there is no prefetch gain is used as a trigger and that US patent 4,901,233 and its commercial embodiment are completely distinct from the present invention in the function of SRAL. BRAL cannot be used for this purpose, and in the present invention, it is used for the same function that was introduced by RIPTA to recover the processor state after a decision was made that the branch guess direction was wrong. The third important distinction is that when the contents of an SRAL are moved to a DRAL, all entries in the SRAL are immediately translated to specify 16 new RA locations. In RIPTA, when decoding an unresolved branch, BRAL is loaded directly from DRAL.

One or more SRALs can be used to ensure that the SFE is synchronized to one or more uPCores. More than one uPCore can use the same SFE to provide prefetch gain, but it is not possible for more than one uPCore to use SFE at the same time. Each additional SRAL must be accompanied by an associated uPCore GPR result bus and an associated storage buffer for synchronization.

uPCore

The uPCore design of the preferred embodiment of the present invention is a conventional microprocessor (a superscalar design such as the PowerPC 601 sold by Motorola and IBM is preferred, but more outdated designs such as the Intel 286 are possible). ). It is known in the computer design art that the system has one or more general purpose execution units. For example, the general purpose execution unit may be designed according to the field of function type to be performed. Although only two general purpose execution units are shown in the uPCore, the use of any number of general purpose execution units does not contradict the present invention. The uPCore portion of the present invention does not require any specific modification except for the portion shown in FIG. 6 with respect to the conventional microprocessor. 6 shows how the address of the most recently retired instruction is latched 604 and then sent to the SFE via interface 604 '. The results of the GPR carried from the universal execution units 601, 602 are latched 603 and then sent to the SFE via the interface 603 ′. Although the uPCore shown in FIG. 6 corresponds to a sequential design, the use of an sequential design element, such as a microprocessor that is currently in commercial use, does not contradict this design.

Sync unit

The synchronization unit 201, SU includes all the logic functions required to control the interaction between the uPCore and the SFE. The SU includes a state machine and associated registers 404, 405, and 406. The output of the state machine includes an interface 209 to the SFE, which controls the erase function and input to the RMS. The line to RMS controls loading SRAL into DRAL in case of synchronous operation.

The sync unit includes a logic function used to determine whether the SFE provides a prefetch gain for the entire system. This embodiment uses two instruction counters 407 and 408 to provide the functionality. The first counter 408 is incremented each time uPCore retires the instruction. The second counter 407 is incremented each time the SFE decodes an instruction. Both counters are reset to zero during resynchronization. After resynchronization, a comparison of counters is used to determine whether the SFE has had a chance to generate a speculative fetch reference that is helpful to uPCore. If the SFE does not decode the instructions much earlier than the execution of uPCore, there is no potential for gain. Comparing the two counters may provide an incomplete but sufficient indication of the likelihood of gain as input to the particular gain determination point 708 of FIG. 7. This embodiment uses a threshold of 10 for this use. If the SFE decode count is not at least 10 greater than the uPCore retirement count, the sync unit does not indicate a gain.

The sync unit also holds an indication of which uPCore the SFE is currently associated with. Each SFE has a single sync unit, but each SFE can be associated with any number of uPCores. This embodiment has one SFE associated with two uPCores.

Alternative extension to the interaction between CP and SE

Other extensions to the interaction between CP and SE are possible. One example may include a case in which the SE updates a branch prediction table shared by both the SE and the CP. The SE may also provide CP hints for other conditions or potential instruction exceptions to allow the CP to avoid pipeline disruption. Fetched instruction and operand data in response to the SFE fetch request is sent directly to uPCore. Thus, the data is in close proximity to the uPCore general purpose execution unit and instruction decode logic when the speculative needs are correct. This may further reduce finite cache loss in certain implementations.

Having described the preferred embodiments of the present invention, those skilled in the art, both now and in the future, can make various improvements and improvements to the present invention within the scope of the present invention.

Various improvements to the present invention have shown that performance analysis of the present invention indicates that random (or random) execution provides more benefits in finite L1 cache CPI reduction compared to infinite L1 cache CPI reduction. Can be. The current technology trend shows that the finite cache effect is growing rapidly, which allows the finite L1 CPI gain to be much larger than the infinite L1 CPI gain.

Inferential fetch engine (SFE) supporting the above-described core microprocessor, and inferential memory reference to the storage hierarchy shared by both the SFE and the microprocessor core while maintaining structure state during matching operation By providing a consistent interaction with the core microprocessor, which is intended to achieve significant simplification for prior art designs using random execution or to achieve significant performance improvements over prior art designs that do not use random execution. It is helpful to people. Ideally, the present invention allows for better optimization in the pursuit of system performance improvements due to design tradeoffs associated with the use of random execution. In contrast to the increased number of stages used in some recent designs, the present invention does not add very large random execution complexity to the main pipeline, making the microprocessor design high frequency, low complexity, and low infinite. (low infinite) Can be optimized for L1 cache CPI.

At the same time, the coprocessor can use a random execution technique over a much wider range in seeking to reduce the finite cache effect on both the microprocessor and the coprocessor. The coprocessor does not need to support a full set of structured instructions or a full set of exceptions and interrupts associated with instruction execution, thereby alleviating the complexity of random execution within the coprocessor. The claims set forth below should be construed to encompass further improvements and to maintain appropriate protection for the first disclosed invention.

The present invention has the effect of improving the performance of the microprocessor by the above-described configuration.

Claims (27)

10. A method for processing a sequential instruction stream of a computer system having a first and a second processing element, each processing element having its own state determined by the setting of its general purpose registers and control registers. a) sending a start instruction of a sequential instruction stream to a first of said processing elements; b) continuing processing of the sequential instruction stream using the first processing element and sending any change in state of the computer system architecture to a second processing element; And c) if it is beneficial for the second processing element to take over the continuous processing of the same sequential instruction stream at any point during the processing of the sequential instruction stream by the first processing element, the Recovering to a second processing element, and taking over the continuous processing of the same sequential instruction stream by processing the sequential instruction stream with the second processing element. Including, The second processing element transmits any change in the state of the computer system structure to the first processing element while it is processing the sequential instruction stream, This allows the first and second processing elements to execute the same instruction during processing of the sequential instruction stream, but only one of the processing elements is determined by the combination of states of the first and second processing elements. Can change the overall structural status of How to process sequential instruction streams. 2. The method of claim 1, wherein the first processing element comprises a plurality of first processing elements functioning as a multiprocessor. 2. The method of claim 1, wherein the combination of states is determined by the first processing element. The method of claim 1, wherein the combination of states of the first and second processing elements is determined by the first processing element and a set of at least one second processing element that functions as a multiprocessor with at least one first processing element. How the sequential instruction stream is determined. 5. The method of claim 4, wherein one sync unit is provided for each of the second processing elements. 5. The synchronizing apparatus according to claim 4, wherein one synchronizing unit is provided for each of the second processing elements, and wherein the synchronizing unit is configured to process the same instruction as the instruction being processed by the first processing element when the second processing element is processed. How to process a sequential instruction stream to determine if it starts. 5. A synchronization unit as claimed in claim 4, wherein one synchronization unit is provided for each of the second processing elements, wherein the synchronization unit is configured to execute the same instruction as the instruction of the processing stream being processed by the first processing element or the next instruction. 2 A method of processing a sequential instruction stream that determines when processing elements begin processing. 5. A synchronization unit as claimed in claim 4, wherein one synchronization unit is provided for each of the second processing elements, wherein the synchronization unit is configured to execute the same instruction as the instruction of the processing stream being processed by the first processing element or the next instruction. 2 A method of processing a sequential instruction stream that determines when a processing element begins to process and also when the instruction processing of the second processing element should be interrupted or ignored. 9. The method of claim 8, wherein the determination as to when the instruction processing of the second processing element should be interrupted or ignored is calculated for the entire computer system having an input provided from the first and second processing elements to the synchronization unit. A method of processing a sequential instruction stream based on a gained benefit determination. 10. The method of claim 9, wherein the input provided to the synchronization unit is information determined immediately or includes information stored in the system. 11. The method of claim 10, wherein the information is information stored in an instruction counter of a synchronization unit. 7. The method of claim 6, wherein when there is a delay in the instruction processing by the first processing element, the sync unit causes the second processing element to process the same instruction as the instruction being processed by the first processing element. How to process a sequential instruction stream to determine if it starts. 7. The synchronization unit of claim 6, wherein when there is an operation that the second processing element is not designed to be handled during the processing of the instruction processing element, when the synchronization unit resynchronizes the state of the second processing element with the rescue state. How to process sequential instruction streams. 7. The synchronization unit of claim 6, wherein when it is determined that the second processing element provides no benefit to the computer system when processing the instruction stream, the sync unit resynchronizes the state of the second processing element with the structural state. How to process sequential instruction streams. 7. The method of claim 6, wherein when there is a delay in processing an instruction by the first processing element, the sync unit is configured to send the same instruction as the instruction being processed by the first processing element and when the second processing element is used. 1 A method of processing a sequential instruction stream that determines which of the processing elements to begin processing with. 7. The synchronization unit of claim 6, wherein when there is an operation in which the second processing element is not designed to be handled during the processing of the instruction processing element, the synchronization unit is configured to change the state of the second processing element from the structural state and the first processing. A method of processing a sequential instruction stream that determines which of the elements to resynchronize. 7. The synchronization unit of claim 6, wherein when there is a determination that the second processing element provides no benefit to the computer system in processing the instruction stream, the sync unit determines the state of the second processing element and the structural state. A method of processing a sequential instruction stream that determines which of the first processing elements to resynchronize with. 7. The method of claim 6, wherein the result of the second processing element is stored in a private general purpose register or a memory buffer. 2. The synchronizing apparatus as claimed in claim 1, wherein one synchronizing unit is provided for the second processing element, and the synchronizing unit outputs the same instruction as the instruction of the processing stream being processed by the first processing element or the next instruction. Determining when a processing element begins processing, and also determining when instruction processing of the second processing element should be interrupted or ignored. 2. The method of claim 1, wherein the second processing element stores the result of the instruction processing of the sequential instruction stream in a personal general purpose register or personal storage buffer coupled to the second processing element, the first processing element performing a fetch operation. Fetching data from the instruction cache and the data shared by both the first and second processing elements. 21. The method of claim 20, wherein the second processing element is used to process some of the same instructions in the instruction stream processed by the first processing element. 22. The method of claim 21, wherein the second processing element is a random processor. 16. The system of claim 15, wherein the first and second processors are synchronized after a predetermined delay has occurred, and during resynchronization, the second processing element is a total result of preprocessing the instruction stream for the first processing element before resynchronization; A method of processing a sequential instruction stream that erases some results. 17. The method of claim 16, wherein during resynchronization the second processing element erases all and some results of preprocessing the instruction stream for the first processing element prior to resynchronization. 18. The method of claim 17, wherein during resynchronization the second processing element erases all and some results of preprocessing the instruction stream for the first processing element prior to resynchronization. 10. A method for processing a sequential instruction stream of a computer system having a first and a second processing element, each having its own state determined by the setting of its general purpose registers and control registers. a) sending a start instruction of a sequential instruction stream to a first of said processing elements; b) continue processing of the sequential instruction stream using the first processing element, sending any change in the state of the computer system structure required by the second processing element to a second processing element, and the transmitted change Accumulating to use for the structural state for the second processing element at a predetermined point in time; And c) from the first processing element if it is advantageous for the second processing element to take over processing of the same sequential instruction stream at any point during the processing of the sequential instruction stream by the first processing element. Restoring successive processing of the same sequential instruction stream by recovering the cumulative structural state previously transmitted to the second processing element and processing the sequential instruction stream with the second processing element. Including, The second processing element accumulates the change to the structural state to be used at a given point in time in the future by using any change in the state of the computer system structure required by the first processing element while processing the sequential instruction stream. To the first processing element for This allows the first and second processing elements to execute the same instruction during processing of the sequential instruction stream, but only one of the processing elements is determined by the combination of some states of the first and second processing elements. To change the overall structural state of the system. How to process sequential instruction streams. 27. The method of claim 26, wherein if it is advantageous for the first processing element to take over processing of the same sequential instruction stream at any point during the processing of the sequential instruction stream by the second processing element, Recovering the accumulated structural state previously transmitted from the second processing element to the first processing element, and taking over the continuous processing of the same sequential instruction stream by processing the sequential instruction stream with the first processing element, 1 The processing element comprises a plurality of first processing elements that function as multiprocessors.