US7395418B1 - Using a transactional execution mechanism to free up processor resources used by a busy-waiting thread - Google Patents
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Definitions
- the present invention relates to techniques for improving performance in computer systems. More specifically, the present invention relates to a method and an apparatus for using a transactional execution mechanism to free up processor resources used by a busy-waiting thread.
- FIG. 1 illustrates two threads executing simultaneously in two different pipelines of a processor.
- instructions from thread 102 execute in ALU pipeline 106 while instructions from thread 104 simultaneously execute in memory pipeline 108 .
- processors that support SMT generally utilize processor resources efficiently, in some situations, they still waste processor resources. For example, suppose that thread 102 is executing a program that performs useful work. At the same time, if thread 104 is in the idle loop (waiting for an event to occur), thread 104 is continually using processor resources to check to see if the event has occurred. These resources could otherwise be used by thread 102 to perform useful work. Note that the code block that causes a thread to wait for an event is referred to as “spin-wait loop,” or a “busy-wait loop.”
- a spin-wait loop is also useful in a high-performance computing (HPC) code, which partitions a complex problem into smaller sub-problems to be solved in parallel.
- HPC high-performance computing
- each sub-problem periodically communicates its results to other sub-problems. Some sub-problems complete more quickly than others.
- the threads that execute these sub-problems often have to wait for the other threads to complete their sub-problems.
- spin-wait loop As each thread completes its assigned sub-problem, it enters a spin-wait loop which continually checks to see if all other sub-problems have completed. This is a performance problem because these spin-wait loops can waste processor resources that could otherwise be used to perform useful work.
- One embodiment of the present invention improves performance of a system that supports simultaneous multi-threading (SMT).
- SMT simultaneous multi-threading
- the system starts a transactional memory operation by generating a checkpoint and entering a transactional-execution mode, wherein instructions are speculatively executed but results are not committed to the architectural state of the processor until the transaction completes without interference.
- the system loads from a mailbox address associated with the halt sequence. The system then stalls execution of the first thread, so that the first thread does not execute instructions within the halt sequence, thereby freeing up processor resources for other threads.
- a second thread stores to the mailbox address, which causes a transactional-memory mechanism within the processor to detect an interference with the previous load from the mailbox address by the first thread and which causes the first thread to exit from the halt sequence.
- the system then continues executing instructions following the halt sequence.
- stalling execution of the first thread involves executing a speculation-barrier instruction, wherein during transactional-execution mode, the speculation-barrier instruction prevents the first thread from executing subsequent instructions.
- the speculation-barrier instruction prevents the halt sequence from committing the transactional-memory operation.
- the halt sequence is implemented as a system call, a library function, or a macro.
- the second thread terminates the halt sequence (by writing to the mailbox) after calculating a result required by the first thread.
- FIG. 1 illustrates two threads executing simultaneously in two different pipelines.
- FIG. 2 presents a code block for a halt sequence in accordance with an embodiment of the present invention.
- FIG. 3 presents a flow chart illustrating the process of executing a halt sequence in accordance with an embodiment of the present invention.
- FIG. 4 presents a flow chart illustrating the process of exiting a halt sequence in accordance with an embodiment of the present invention.
- a computer-readable storage medium which may be any device or medium that can store code and/or data for use by a computer system.
- the transmission medium may include a communications network, such as the Internet.
- the present invention uses a transactional-memory mechanism to free up processor resources when a processor encounters a halt sequence.
- Transactional memory is described in more detail in U.S. Pat. No. 6,862,664, entitled “Method and Apparatus for Avoiding Locks by Speculatively Executing Critical Sections,” by inventors Shailender Chaudhry, Marc Tremblay, and Quinn Jacobson.
- the above-listed application is hereby incorporated by reference to provide details on how transactional memory operates and is herein referred to as “[Chaudhry].”
- the transactional memory system in [Chaudhry] makes a critical section of code appear to execute atomically.
- the processor executes a checkpoint instruction, to generate a checkpoint, which the processor can use to return execution to the point where the checkpoint was taken.
- the processor performs a commit operation, to commit changes made during the speculative-execution mode.
- the term “thread” is used to refer to a thread and a process within this specification.
- the thread aborts the transaction and discards the changes made during the speculative-execution mode. In other words, the critical section of code completes or fails as a single unit.
- the system speculatively executes code within the critical section, without committing results of the speculative execution to the architectural state of the processor.
- the system also continually monitors data references made by other threads to determine if an interfering data access occurs during speculative-execution mode. If not, the system commits changes made during speculative-execution mode and then resumes execution of the first thread past the critical section in normal-execution mode.
- the system aborts the transaction and discards changes made during the speculative-execution mode.
- an interfering data access can include a store by another thread to a cache line that has been load marked by the thread. It can also include a load or a store by another thread to a cache line that has been store marked by the thread.
- FIG. 2 presents a code block that implements a halt sequence in accordance with an embodiment of the present invention.
- a first thread can invoke the halt sequence to wait for a condition to occur, such as waiting for a second thread to calculate a result needed by the first thread.
- the halt sequence code uses the transactional memory system to handle halt sequences without requiring the processor to continually execute code in the halt sequence to check to see if a condition is satisfied.
- the halt sequence code first generates a checkpoint which has a corresponding fail_pc address.
- the first thread jumps to this fail_pc address when the transactional-memory operation fails.
- the halt sequence then loads from a “mailbox address.”
- the halt sequence code then stalls the execution of the first thread.
- the mailbox address is a location in memory which the second thread uses to notify the first thread that a condition is satisfied. When the condition is satisfied, the second thread stores to the mailbox address, thereby interfering with the previous load from the mailbox address by the first thread.
- the first thread stalls, the first thread no longer executes instructions, which frees up processor resources.
- the first thread resumes execution of subsequent instructions only when another thread interferes with the transaction initiated by the first thread.
- other events can cause a transaction to fail (such as certain system events). Therefore, once the first thread resumes execution, it needs to verify that the waited-for condition has actually occurred by checking the mailbox to ensure that it contains the expected value.
- a programmer can use the halt sequence code to stop execution of a thread to wait for a condition to occur.
- the halt sequence can be implemented as a system call, a library function, or a macro.
- a processor that supports scout mode
- the processor speculatively executes instructions to prefetch future loads, but the processor does not commit the results to the architectural state of the processor.
- U.S. patent application Ser. No. 10/741,944 entitled “Generating Prefetches by Speculatively Executing Code Through Hardware Scout Threading,” by inventors Shailender Chaudhry and Marc Tremblay, filed on 19 Dec. 2003, and published on 8 Jul. 2004. This patent application is hereby incorporated by reference herein to provide details on how scout mode operates.
- a processor that supports scout mode simply launches into scout mode upon encountering a conventional stall instruction, a conventional stall instruction will not stop a thread from executing subsequent instructions. Hence, a different type of stall instruction is needed to prevent execution of subsequent instructions during scout mode.
- This new type of stall instruction is referred to as a “speculation-barrier” instruction.
- a thread when a thread encounters the checkpoint instruction of the halt sequence, it enters into a speculative-execution mode, such as scout mode.
- speculative-execution mode the processor first loads from the mailbox address and then executes the speculation-barrier instruction which prevents the thread from executing subsequent instructions.
- the speculation-barrier instruction does not prevent the thread from executing instructions after the speculation-barrier instruction.
- the speculation-barrier will be encountered while the thread is in speculative-execution mode. Therefore, it has the effect of stopping instruction execution until an event external to the thread causes speculative-execution mode to be terminated.
- FIG. 3 presents a flow chart illustrating the process of executing a halt sequence in accordance with an embodiment of the present invention.
- the system starts a transactional memory operation by generating a checkpoint and entering transactional-execution mode (step 302 ).
- the thread executes a load from a mailbox address associated with the halt sequence (step 304 ).
- the thread then executes a stall instruction (or a speculation-barrier instruction) (step 306 ).
- FIG. 4 presents a flow chart illustrating the process of exiting a halt sequence in accordance with an embodiment of the present invention.
- the process begins when a second thread stores to the mailbox address to terminate the halt sequence (step 402 ).
- the process continues when the first thread detects the interference caused by second thread with the previous load from the mailbox address issued by the first thread (step 404 ).
- the first thread then exits the halt sequence (step 406 ) and continues executing instructions following the halt sequence (step 408 ).
- the second thread terminates the halt sequence for the first thread after calculating a result required by the first thread.
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Cited By (11)
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US20070143755A1 (en) * | 2005-12-16 | 2007-06-21 | Intel Corporation | Speculative execution past a barrier |
US20080162886A1 (en) * | 2006-12-28 | 2008-07-03 | Bratin Saha | Handling precompiled binaries in a hardware accelerated software transactional memory system |
US20100186015A1 (en) * | 2009-01-22 | 2010-07-22 | International Business Machines Corporation | Method and apparatus for implementing a transactional store system using a helper thread |
US20110047362A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | Version Pressure Feedback Mechanisms for Speculative Versioning Caches |
US20110047334A1 (en) * | 2009-08-20 | 2011-02-24 | International Business Machines Corporation | Checkpointing in Speculative Versioning Caches |
US20110179254A1 (en) * | 2010-01-15 | 2011-07-21 | Sun Microsystems, Inc. | Limiting speculative instruction fetching in a processor |
US20150205586A1 (en) * | 2014-01-17 | 2015-07-23 | Nvidia Corporation | System, method, and computer program product for bulk synchronous binary program translation and optimization |
US9128750B1 (en) * | 2008-03-03 | 2015-09-08 | Parakinetics Inc. | System and method for supporting multi-threaded transactions |
US9684537B2 (en) | 2015-11-06 | 2017-06-20 | International Business Machines Corporation | Regulating hardware speculative processing around a transaction |
US10275254B2 (en) | 2017-03-08 | 2019-04-30 | International Business Machines Corporation | Spin loop delay instruction |
CN114629748A (en) * | 2022-04-01 | 2022-06-14 | 日立楼宇技术(广州)有限公司 | Building data processing method, edge gateway of building and storage medium |
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Cited By (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070143755A1 (en) * | 2005-12-16 | 2007-06-21 | Intel Corporation | Speculative execution past a barrier |
US8719807B2 (en) * | 2006-12-28 | 2014-05-06 | Intel Corporation | Handling precompiled binaries in a hardware accelerated software transactional memory system |
US20080162886A1 (en) * | 2006-12-28 | 2008-07-03 | Bratin Saha | Handling precompiled binaries in a hardware accelerated software transactional memory system |
US9304769B2 (en) | 2006-12-28 | 2016-04-05 | Intel Corporation | Handling precompiled binaries in a hardware accelerated software transactional memory system |
US9128750B1 (en) * | 2008-03-03 | 2015-09-08 | Parakinetics Inc. | System and method for supporting multi-threaded transactions |
US20100186015A1 (en) * | 2009-01-22 | 2010-07-22 | International Business Machines Corporation | Method and apparatus for implementing a transactional store system using a helper thread |
US9098327B2 (en) * | 2009-01-22 | 2015-08-04 | International Business Machines Corporation | Method and apparatus for implementing a transactional store system using a helper thread |
US8448173B2 (en) * | 2009-01-22 | 2013-05-21 | International Business Machines Corporation | Method and apparatus for implementing a transactional store system using a helper thread |
US20130219121A1 (en) * | 2009-01-22 | 2013-08-22 | International Business Machines Corporation | Method and apparatus for implementing a transactional store system using a helper thread |
US8397052B2 (en) | 2009-08-19 | 2013-03-12 | International Business Machines Corporation | Version pressure feedback mechanisms for speculative versioning caches |
US20110047362A1 (en) * | 2009-08-19 | 2011-02-24 | International Business Machines Corporation | Version Pressure Feedback Mechanisms for Speculative Versioning Caches |
US8521961B2 (en) | 2009-08-20 | 2013-08-27 | International Business Machines Corporation | Checkpointing in speculative versioning caches |
US20110047334A1 (en) * | 2009-08-20 | 2011-02-24 | International Business Machines Corporation | Checkpointing in Speculative Versioning Caches |
US20110179254A1 (en) * | 2010-01-15 | 2011-07-21 | Sun Microsystems, Inc. | Limiting speculative instruction fetching in a processor |
US20150205586A1 (en) * | 2014-01-17 | 2015-07-23 | Nvidia Corporation | System, method, and computer program product for bulk synchronous binary program translation and optimization |
US9207919B2 (en) * | 2014-01-17 | 2015-12-08 | Nvidia Corporation | System, method, and computer program product for bulk synchronous binary program translation and optimization |
US9684537B2 (en) | 2015-11-06 | 2017-06-20 | International Business Machines Corporation | Regulating hardware speculative processing around a transaction |
US9690623B2 (en) | 2015-11-06 | 2017-06-27 | International Business Machines Corporation | Regulating hardware speculative processing around a transaction |
US10606638B2 (en) | 2015-11-06 | 2020-03-31 | International Business Machines Corporation | Regulating hardware speculative processing around a transaction |
US10996982B2 (en) | 2015-11-06 | 2021-05-04 | International Business Machines Corporation | Regulating hardware speculative processing around a transaction |
US10275254B2 (en) | 2017-03-08 | 2019-04-30 | International Business Machines Corporation | Spin loop delay instruction |
US10365929B2 (en) | 2017-03-08 | 2019-07-30 | International Business Machines Corporation | Spin loop delay instruction |
US10656950B2 (en) | 2017-03-08 | 2020-05-19 | International Business Machines Corporation | Spin loop delay instruction |
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