KR19990065713A - Method of manufacturing silicide - Google Patents
Method of manufacturing silicide Download PDFInfo
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- KR19990065713A KR19990065713A KR1019980001138A KR19980001138A KR19990065713A KR 19990065713 A KR19990065713 A KR 19990065713A KR 1019980001138 A KR1019980001138 A KR 1019980001138A KR 19980001138 A KR19980001138 A KR 19980001138A KR 19990065713 A KR19990065713 A KR 19990065713A
- Authority
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- South Korea
- Prior art keywords
- silicide
- nitrogen ions
- gate
- layer
- source
- Prior art date
Links
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 54
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 25
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 24
- -1 nitrogen ions Chemical class 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000010438 heat treatment Methods 0.000 claims abstract description 19
- 238000000151 deposition Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 4
- 239000013078 crystal Substances 0.000 abstract description 8
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 238000007796 conventional method Methods 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 2
- 229910008484 TiSi Inorganic materials 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910019001 CoSi Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000009257 reactivity Effects 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Abstract
본 발명은 실리사이드 제조방법에 관한 것으로, 종래에는 형성된 실리사이드가 후속공정에서 열에너지를 얻으면 결정경계가 감소되고, 이에 따라 결정경계의 과잉에너지가 줄어들어 실리사이드 전체의 에너지가 줄어들게 되므로, 후속 열공정에 의해 실리사이드의 덩어리가 형성되고, 그 덩어리들로 인해 실리사이드의 저항이 급격히 증가되는 문제점이 있었다. 이와같은 문제점을 감안한 본 발명은 게이트 및 소스/드레인영역이 형성된 반도체기판상에 질소이온을 소정깊이로 주입하는 단계와; 상기 질소이온이 주입된 반도체기판의 상부전면에 금속층을 증착하고, 1차 및 2차 열처리를 통해 게이트 및 소스/드레인영역의 상부에 실리사이드층을 형성하는 단계로 이루어지는 실리사이드 제조방법을 통해 게이트 및 고농도 소스/드레인영역에 주입된 질소이온이 금속과 반응하여 실리사이드층의 결정경계에 주로 분포하거나, 또는 질소이온 자체가 실리사이드의 결정경계에 주로 분포하여 후속 열공정에 의해 실리사이드의 덩어리가 형성되지 않도록 하여 저항의 증가를 방지함으로써, 실리사이드층의 열적안정성을 도모할 수 있는 효과와; 질소이온이 금속과 반응함으로써, 실리사이드층의 형성을 억제하여 질소이온의 주입깊이에 따라 실리사이드층의 두께를 조절할 수 있는 효과가 있다.The present invention relates to a method of manufacturing a silicide. In the conventional method, when a heat generated in a subsequent process is applied to a silicide, the crystal boundary is reduced, and the energy of the entire silicide is reduced by reducing the excess energy of the crystal boundary. And the resistance of the silicide is rapidly increased due to the lumps. SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device, the method comprising: injecting nitrogen ions to a predetermined depth on a semiconductor substrate having gate and source / Depositing a metal layer on the upper surface of the semiconductor substrate into which the nitrogen ions are implanted, and forming a silicide layer on the gate and the source / drain regions through a primary and secondary heat treatment, The nitrogen ions injected into the source / drain regions react with the metal and are mainly distributed at the crystal boundaries of the silicide layer or the nitrogen ions themselves are mainly distributed at the crystal boundaries of the silicide so that a lump of silicide is not formed by a subsequent thermal process An effect of preventing thermal expansion of the silicide layer by preventing an increase in resistance; The nitrogen ion reacts with the metal to suppress the formation of the silicide layer and to control the thickness of the silicide layer according to the depth of implantation of nitrogen ions.
Description
본 발명은 실리사이드 제조방법에 관한 것으로, 특히 후속 고온 열처리에서 열적 안정성을 갖는 실리사이드를 원하는 두께로 제조하기에 적당하도록 한 실리사이드 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a silicide, and more particularly, to a method for manufacturing a silicide that is suitable for manufacturing a silicide having thermal stability in a subsequent high-temperature heat treatment to a desired thickness.
반도체소자의 디자인 룰(design rule)이 엄격해지고, 감소하면서 접합의 면저항 및 금속과 반도체의 접촉저항에 따른 기생저항이 소자의 안정적인 동작에 큰 영향을 미치고 있다. 이러한 기생저항을 감소시키기 위한 기술로 살리사이드(self-aligned silicide) 공정에 대한 연구가 활발히 진행되어 왔다. 살리사이드 공정이란 실리콘과 금속의 반응성과 산화막과 금속의 비반응성을 이용한 자기정렬방식을 통해 실리사이드를 제조하는 공정법을 지칭하며, 내열성의 금속 실리사이드중에서 Ti 및 Co-실리사이드는 비저항이 낮고, 열적 안정성이 다른 실리사이드에 비해 뛰어나므로, 살리사이드공정에 가장 널리 이용되고 있다. 이와같은 종래 실리사이드 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Parasitic resistance due to the contact resistance between the metal and the semiconductor greatly affects the stable operation of the device while the design rule of the semiconductor device is becoming strict and decreasing. Studies on the self-aligned silicide process have been actively pursued as a technique for reducing such parasitic resistance. The salicide process refers to a process for producing a silicide by a self-aligning method using the reactivity of silicon and metal and the non-reactivity of an oxide film and a metal. Among the heat-resistant metal silicides, Ti and Co-silicide have low resistivity, Is superior to other silicides and is therefore most widely used in salicide processes. The conventional silicide manufacturing method will be described in detail with reference to the accompanying drawings.
도1a 내지 도1d는 종래의 실리사이드 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 폴리실리콘으로 이루어진 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조(lightly doped drain:LDD)의 저농도 및 고농도 소스/드레인영역(4)을 형성하는 단계(도1a)와; 그 반도체기판(1)의 상부 전면에 금속층(5)을 증착하는 단계(도1b)와; 그 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성하는 단계(도1c)와; 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행하는 단계(도1d)로 이루어진다. 이하, 상기한 바와같은 일반적인 실리사이드 제조방법을 좀더 상세히 설명한다.1A to 1D are cross-sectional views illustrating a conventional method for producing a silicide. As shown in FIG. 1A, a gate 2 made of polysilicon is formed on a semiconductor substrate 1, Forming side walls 3 to form low and high concentration source / drain regions 4 of lightly doped drain (LDD) (Figure 1A); Depositing a metal layer 5 on the entire upper surface of the semiconductor substrate 1 (Fig. 1B); 1C) of forming a silicide layer 6 on the gate 2 and the high concentration source / drain region 4 by performing a first heat treatment on the semiconductor substrate 1 on which the metal layer 5 is deposited; Removing the remaining metal layer 5 through a wet etching method, and performing a second heat treatment (FIG. 1D). Hereinafter, a general method for producing a silicide as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 폴리실리콘으로 이루어진 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성한다. 이때, 엘디디구조를 형성하는 공정은 게이트(2)가 형성된 반도체기판(1)에 저농도의 불순물이온을 주입한 후, 그 게이트(2)의 측면에 측벽(3)을 형성하고, 그 측벽(3)이 형성된 반도체기판(1)에 고농도의 불순물이온을 주입하여 저농도 및 고농도 소스/드레인영역을 형성하는 공정으로, 열전자효과를 감소시켜 반도체소자의 신뢰성을 향상시키기 위해 통상적으로 행해지고 있다.First, as shown in FIG. 1A, a gate 2 made of polysilicon is formed on a semiconductor substrate 1, and a side wall 3 is formed on a side surface of the gate 2, Thereby forming a heavily doped source / drain region 4. At this time, in the step of forming the LDD structure, the impurity ions of a low concentration are injected into the semiconductor substrate 1 on which the gate 2 is formed, the side wall 3 is formed on the side surface of the gate 2, 3 is formed by implanting high-concentration impurity ions into the semiconductor substrate 1 on which the source and drain regions 3 are formed to form a source / drain region having a low concentration and a high concentration. In order to improve the reliability of the semiconductor device,
그리고, 도1b에 도시한 바와같이 반도체기판(1)의 상부 전면에 금속층(5)을 증착한다. 이때, 금속층(5)으로는 다른 금속에 비해 열처리 후 상대적으로 저항이 낮은 Co,Ti 등을 증착한다.Then, as shown in FIG. 1B, a metal layer 5 is deposited on the entire upper surface of the semiconductor substrate 1. At this time, as the metal layer 5, Co and Ti, which have relatively low resistance after heat treatment, are deposited compared to other metals.
그리고, 도1c에 도시한 바와같이 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성한다. 이때, 1차 열처리는 금속층(5)이 Ti인 경우는 600℃∼750℃, 금속층(5)이 Co인 경우는 450℃∼550℃로 수행한다.Then, as shown in FIG. 1C, the semiconductor substrate 1 on which the metal layer 5 is deposited is subjected to a first heat treatment to form the silicide layer 6 on the gate 2 and the high concentration source / drain region 4 . In this case, the first heat treatment is performed at 600 ° C. to 750 ° C. when the metal layer 5 is Ti, and 450 ° C. to 550 ° C. when the metal layer 5 is Co.
그리고, 도1d에 도시한 바와같이 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행한다. 이때, 2차 열처리는 형성된 실리사이드층(6)이 C49 TiSi2인 경우는 800℃∼900℃로 열처리하여 저항이 낮은 물질인 C54 TiSi2로 상변이 시키며, CoSi인 경우는 600℃∼750℃로 열처리하여 저항이 낮은 물질인 CoSi2로 상변이 시킨다.Then, as shown in FIG. 1D, the residual metal layer 5 is removed through a wet etching method, and then a secondary heat treatment is performed. When the formed silicide layer (6) is C49 TiSi 2 , the second heat treatment is performed at a temperature of 800 ° C to 900 ° C to transform the material into C54 TiSi 2 , which is a low resistance material. In the case of CoSi, the second heat treatment is performed at 600 ° C to 750 ° C Heat treatment is performed and the phase is changed to CoSi 2 , which is a low resistance material.
그러나, 상기한 바와같은 종래의 실리사이드 제조방법은 형성된 실리사이드가 후속공정에서 열에너지를 얻으면 결정경계(grain boundary)가 감소되고, 이에 따라 결정경계의 과잉에너지가 줄어들어 실리사이드 전체의 에너지가 줄어들게 되므로, 후속 열공정에 의해 실리사이드의 덩어리(agglomeration)가 형성되고, 그 덩어리들로 인해 실리사이드의 저항이 급격히 증가되는 문제점이 있었다.However, in the conventional method of producing a silicide as described above, when the formed silicide obtains thermal energy in a subsequent process, the grain boundary is reduced, and thus the excess energy of the crystal boundary is reduced and the energy of the entire silicide is reduced. There is a problem that the agglomeration of the silicide is formed by the process and the resistance of the silicide is rapidly increased due to the lumps.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 고온에서 열적안정성을 갖으며, 원하는 두께의 실리사이드를 제조할 수 있는 실리사이드 제조방법을 제공하는 데 있다.It is an object of the present invention to provide a method of manufacturing a silicide having a thermal stability at a high temperature and capable of producing a silicide having a desired thickness.
도1은 종래의 실리사이드 제조방법을 보인 수순단면도.1 is a cross-sectional view of a conventional silicide manufacturing method.
도2는 본 발명의 일 실시예를 보인 수순단면도.2 is a cross-sectional view of a first embodiment of the present invention.
도3은 도2에 있어서, 실리사이드층의 상세단면도.Figure 3 is a detailed cross-sectional view of the silicide layer in Figure 2;
도4는 본 발명을 적용한 실리사이드층의 열적안정성을 보인 그래프도.4 is a graph showing the thermal stability of a silicide layer to which the present invention is applied.
***도면의 주요 부분에 대한 부호의 설명***DESCRIPTION OF THE REFERENCE SYMBOLS
1:반도체기판 2:게이트1: semiconductor substrate 2: gate
3:측벽 4:소스/드레인영역3: side wall 4: source / drain region
5:금속층 6:실리사이드층5: metal layer 6: silicide layer
상기한 바와같은 본 발명의 목적은 게이트 및 소스/드레인영역이 형성된 반도체기판상에 질소이온을 소정깊이로 주입하는 단계와; 상기 질소이온이 주입된 반도체기판의 상부전면에 금속층을 증착하고, 1차 및 2차 열처리를 통해 게이트 및 소스/드레인영역의 상부에 실리사이드층을 형성하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 실리사이드 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: injecting nitrogen ions to a predetermined depth on a semiconductor substrate having gate and source / drain regions formed therein; Depositing a metal layer on the entire upper surface of the semiconductor substrate into which the nitrogen ions are implanted, and forming a silicide layer on the gate and the source / drain regions through the first and second heat treatments. Will now be described in detail with reference to the accompanying drawings.
도2a 내지 도2e는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성하는 단계(도2a)와; 그 게이트(2) 및 소스/드레인영역(4)에 소정깊이로 질소이온을 주입하는 단계(도2b)와; 질소이온이 주입된 반도체기판(1)의 상부 전면에 금속층(5)을 증착하는 단계(도2c)와; 그 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성하는 단계(도2d)와; 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행하는 단계(도2e)로 이루어진다. 이하, 상기한 바와같은 본 발명의 일 실시예를 좀더 상세히 설명한다.2A to 2E are cross-sectional views illustrating an embodiment of the present invention in which a gate 2 is formed on an upper portion of a semiconductor substrate 1 and side walls 3 ) To form low and high concentration source / drain regions 4 of the LD structure (FIG. 2A); Injecting nitrogen ions into the gate 2 and the source / drain region 4 to a predetermined depth (Fig. 2B); (FIG. 2C) depositing a metal layer 5 on the entire upper surface of the semiconductor substrate 1 into which the nitrogen ions are implanted; A step (FIG. 2d) of forming a silicide layer 6 on the gate 2 and the high concentration source / drain region 4 by performing a first heat treatment on the semiconductor substrate 1 on which the metal layer 5 is deposited; Removing the residual metal layer 5 through a wet etching method, and performing a second heat treatment (FIG. 2E). Hereinafter, an embodiment of the present invention will be described in detail.
먼저, 도2a에 도시한 바와같이 반도체기판(1)의 상부에 게이트(2)를 형성하고, 그 게이트(2)의 측면에 측벽(3)을 형성하여 엘디디구조의 저농도 및 고농도 소스/드레인영역(4)을 형성한다. 이때, 엘디디구조를 형성하는 공정은 종래와 동일하게 수행된다.2A, a gate 2 is formed on an upper portion of a semiconductor substrate 1 and a side wall 3 is formed on a side surface of the gate 2 to form a low concentration and high concentration source / Regions 4 are formed. At this time, the process of forming the LDD structure is performed in the same manner as in the related art.
그리고, 도2b에 도시한 바와같이 게이트(2) 및 소스/드레인영역(4)에 소정깊이로 질소이온을 주입한다. 이때, 질소이온은 30keV∼100keV의 에너지로 1015∼1016개/㎠를 주입한다.Then, nitrogen ions are implanted into the gate 2 and the source / drain region 4 to a predetermined depth as shown in FIG. 2B. At this time, nitrogen ions are implanted at 10 15 to 10 16 ions / cm 2 at an energy of 30 keV to 100 keV.
그리고, 도2c에 도시한 바와같이 질소이온이 주입된 반도체기판(1)의 상부 전면에 금속층(5)을 증착한다. 이때, 금속층(5)은 Ti 또는 Co를 증착한다.Then, as shown in FIG. 2C, the metal layer 5 is deposited on the entire upper surface of the semiconductor substrate 1 into which the nitrogen ions are implanted. At this time, the metal layer 5 deposits Ti or Co.
그리고, 도2d에 도시한 바와같이 금속층(5)이 증착된 반도체기판(1)을 1차 열처리하여 게이트(2) 및 고농도 소스/드레인영역(4)의 상부에 실리사이드층(6)을 형성한다. 이때, 1차 열처리의 온도조건은 종래와 동일하며, 게이트(2) 및 고농도 소스/드레인영역(4)에 주입된 질소이온은 금속층(5)이 Ti일 경우는 Ti와 반응하여 도3에 도시한 바와같이 TiN이 실리사이드층(6)의 결정경계에 주로 분포함으로써, 후속 열공정에 의해 실리사이드의 덩어리가 형성되는 것을 방지하며, 금속층(5)이 Co일 경우는 CoN은 존재하지 않지만, 질소이온이 CoSi2의 결정경계에 주로 분포하여 상기와 동일하게 실리사이드의 덩어리가 형성되는 것을 방지한다. 한편, 질소이온이 금속과 반응함으로써, 실리사이드층(6)의 형성을 억제하여 질소이온의 주입깊이에 따라 실리사이드층(6)의 두께를 조절할 수 있다.2D, the semiconductor substrate 1 on which the metal layer 5 is deposited is subjected to a first heat treatment to form a silicide layer 6 on the gate 2 and the heavily doped source / drain region 4 . The nitrogen ions implanted into the gate 2 and the high concentration source / drain region 4 react with Ti when the metal layer 5 is Ti, As described above, since TiN is mainly distributed at the crystal boundary of the silicide layer 6, it prevents the formation of a lump of silicide by the subsequent thermal process. When the metal layer 5 is Co, CoN does not exist, Is mainly distributed at crystal boundaries of CoSi 2 and prevents the formation of a lump of silicide as described above. On the other hand, by reacting the nitrogen ions with the metal, the formation of the silicide layer 6 can be suppressed and the thickness of the silicide layer 6 can be controlled according to the depth of implantation of the nitrogen ions.
그리고, 도2e에 도시한 바와같이 습식식각방법을 통해 잔여 금속층(5)을 제거한 후, 2차 열처리를 수행한다. 이때, 2차 열처리도 종래와 동일한 온도조건으로 수행하여 보다 저항이 낮은 물질로 실리사이드층(6)을 상변이 시킨다.Then, as shown in FIG. 2E, the remaining metal layer 5 is removed by a wet etching method, and then a secondary heat treatment is performed. At this time, the second heat treatment is also performed under the same temperature condition as the prior art, and the silicide layer 6 is phase-transformed with a material having a lower resistance.
한편, 도4는 이와같은 질소이온을 통한 실리사이드층(6)의 열적안정성을 보인 그래프도로서, 1차 열처리를 N2분위기와 NH3분위기에서 각각 진행한 TiSi2의 저항변화를 나타내며, NH3분위기에서 열처리하여 TiSi2에 질소이온의 주입이 많은 것의 열적 특성이 보다 안정되어 있음을 알수 있다.On the other hand, Figure 4 is such as a graph showing the thermal stability of the silicide layer 6 through a nitrogen ion, represents the respective progress a resistance change of the TiSi 2 the primary heat treatment in the N 2 atmosphere with NH 3 atmosphere, NH 3 It can be seen that the thermal properties of TiSi 2 with many nitrogen ion implantation are more stable.
상기한 바와같은 본 발명에 의한 실리사이드 제조방법은 게이트 및 고농도 소스/드레인영역에 주입된 질소이온이 금속과 반응하여 실리사이드층의 결정경계에 주로 분포하거나, 또는 질소이온 자체가 실리사이드의 결정경계에 주로 분포하여 후속 열공정에 의해 실리사이드의 덩어리가 형성되지 않도록 하여 저항의 증가를 방지함으로써, 실리사이드층의 열적안정성을 도모할 수 있는 효과와; 질소이온이 금속과 반응함으로써, 실리사이드층의 형성을 억제하여 질소이온의 주입깊이에 따라 실리사이드층의 두께를 조절할 수 있는 효과가 있다.In the method for producing a silicide according to the present invention as described above, nitrogen ions implanted into the gate and the high concentration source / drain regions react with the metal and are mainly distributed at the crystal boundary of the silicide layer, An effect of preventing the formation of a lump of silicide by a subsequent thermal process so as to prevent an increase in resistance, thereby achieving thermal stability of the silicide layer; The nitrogen ion reacts with the metal to suppress the formation of the silicide layer and to control the thickness of the silicide layer according to the depth of implantation of nitrogen ions.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100433054B1 (en) * | 2001-12-22 | 2004-05-27 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR101004811B1 (en) * | 2003-07-25 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing Transistor |
| KR20140063644A (en) * | 2011-07-27 | 2014-05-27 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods of forming a metal silicide region in an integrated circuit |
| CN112864240A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and two semiconductor structures |
| US11887854B2 (en) | 2021-01-14 | 2024-01-30 | Changxin Memory Technologies, Inc. | Semiconductor structure manufacturing method and two semiconductor structures |
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| JPH09223677A (en) * | 1996-02-14 | 1997-08-26 | Sony Corp | Manufacturing method of semiconductor device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100433054B1 (en) * | 2001-12-22 | 2004-05-27 | 동부전자 주식회사 | Method For Manufacturing Semiconductor Devices |
| KR101004811B1 (en) * | 2003-07-25 | 2011-01-04 | 매그나칩 반도체 유한회사 | Method for manufacturing Transistor |
| KR20140063644A (en) * | 2011-07-27 | 2014-05-27 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods of forming a metal silicide region in an integrated circuit |
| CN112864240A (en) * | 2021-01-14 | 2021-05-28 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and two semiconductor structures |
| CN112864240B (en) * | 2021-01-14 | 2022-05-31 | 长鑫存储技术有限公司 | Method for manufacturing semiconductor structure and two semiconductor structures |
| US11887854B2 (en) | 2021-01-14 | 2024-01-30 | Changxin Memory Technologies, Inc. | Semiconductor structure manufacturing method and two semiconductor structures |
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