KR19990065166A - 5-processor pipelined microprocessor - Google Patents

Abstract

The microprocessor using the pipeline method of the present invention includes a first instruction register for decoding a prefetched instruction from a memory, a multiplexer for outputting a first instruction register and a predetermined internal code and selectively outputting the first instruction register; A second instruction register used to input instructions output from the multiplexer, decode the instructions, and use them in the instruction execution phase, and instructions output from the second instruction register, and a third instruction used for memory access operations. Registers and instructions output from a third instruction register, and the first instruction register and the fourth instruction register and pipeline stall for generating a fourth instruction register for decoding and using the writeback operation. And control circuitry for decoding the instruction code of the instruction register of 2 to generate the internal code for multicycle processing and to control the multiplexer.

Description

MICRO PROCESSOR USING 5 STAGE PIPELINE

The present invention relates to a microprocessor, and more particularly to a microprocessor using a five-stage pipeline.

Existing Scalable Processor Architecture (SPARC) Reduced Instruction Set Computers (RISCs) using the existing 32-bit four-stage pipeline have no stages for memory access, so there is usually no fetch, decode, The pipeline is built using the steps of Execute and Writeback.

Normally, the data is input in the next pipeline stage when the address is read after the address is output in the execution stage of the pipeline in the cache, and the write is performed after the tag check of the cache is performed. Since the data is written after the step, a pipeline stall of one cycle at the time of read and usually two cycles at the time of write is required when accessing the cache. )

For this reason, we do not use separate caches, use unified caches, and fetch instructions because of the monopoly of the bus that occurs when reading or writing data. In this case, instructions that were previously fetched beforehand cannot be entered into the instruction register of the pipeline, but instead of being fetched during data read / write by entering the prefetch buffer. To complement them.

Referring to FIG. 1, a four-stage pipeline microprocessor includes a first prefetch buffer 10, a first multiplexer 20, a second prefetch buffer 30, a second multiplexer 40, and a first instruction register ( 50), the second instruction register 60, the third instruction register 70, and the control circuit 80. As shown in FIG.

The prefetch buffers 10, 30, the multiplexers 20, 40, and the instruction registers 50, 60, 70 operate in synchronization with a clock signal.

The first instruction register 50 of the decode stage is used to decode the instructions fetched from the second multiplexer 40 to separate the instructions, and is used to generate the control signal of the stage, and executes ( The second instruction register 60 in the Execute step is used to generate a signal that receives the instruction fetched from the first instruction register 50 and removes circuits to be operated in the execute step. The third instruction register 70 in the writeback stage is used to generate a signal for controlling the writeback performing circuit.

The first prefetch buffer 10 and the second prefetch buffer 20 serve to compensate for a situation in which an instruction cannot be fetched when data is written / read into the first instruction register 50. The multiplexer 20 and the second multiplexer 40 are essentially used to control the instructions.

In this case, a bus for fetch should be connected to both the two prefetch buffers and the first instruction register 50, and also to the first prefetch buffer 10 and the second prefetch buffer 30. The control of the instruction using the multiplexers 20 and 40 is also essentially entered between the first instruction register 50. Therefore, the bus becomes complicated, and the control circuit 80 also becomes complicated.

Accordingly, it is an object of the present invention to provide a microprocessor that is small in size and suitable for an embedded controller using an instruction fetch simple but effective structure.

1 is a circuit diagram showing the configuration of a four stage pipeline according to the prior art;

2 is a circuit diagram showing the configuration of a five-stage pipeline in a microprocessor according to an embodiment of the present invention;

* Explanation of symbols on the main parts of the drawings

10: first prefetch buffer 20: first multiplexer

30: second prefetch buffer 40: second multiplexer

50: first instruction register 60: second instruction register

70: third instruction register 50: control circuit

110: first instruction register 120: multiplexer

130: second instruction register 140: third instruction register

150: fourth instruction register 160: control circuit

(Configuration)

According to one aspect of the present invention, there is provided a microprocessor using a pipeline method, comprising: a first instruction register for decoding a prefetched instruction from a memory; A multiplexer for selectively outputting the output of the first instruction register and a predetermined internal code; A second instruction register for inputting an instruction output from the multiplexer and for executing the instruction; A third instruction register for storing instructions output from said second instruction register; A third instruction register for inputting an instruction output from the third instruction register and writing back the instruction using the instruction; And control means for decoding the instruction codes of the first and second instruction registers to generate the internal code for multicycle processing and to control the multiplexer when a pipeline stall occurs.

In this embodiment, the memory means utilizes a five stage pipeline scheme, characterized in that it is operated with a separate cache.

(Action)

With such a device, the pipeline can be simplified in five stages by eliminating unnecessary circuits such as two prefetch buffers and a multiplexer.

(Example)

Hereinafter, a description will be given with reference to FIG. 2 according to a preferred embodiment of the present invention.

Referring to FIG. 2, the microprocessor using the five-stage pipeline method assumed as a separate cache includes a first instruction register 110, a multiplexer 120, a second instruction register 130, and a third instruction register 140. And the fourth instruction register 150 and the control circuit 160.

The instruction registers 110, 130, 140, and 150 and the multiplexer 120 operate in synchronization with a clock signal.

The first instruction register 110 in a decode step is a device for decoding an instruction fetched from a memory, and the multiplexer 120 outputs the first instruction register 110 and the control circuit. One of predetermined internal codes input from 160 is selectively outputted.

The second instruction register 130 of the execute stage is used to generate the control signal required in the instruction execution stage by storing the instruction output from the multiplexer, and the third instruction register 140 of the memory stage. ) Stores instructions output from the second instruction register 130 and is used when the instruction requires memory access.

The fourth instruction register 150 in the writeback stage is used to store an instruction output from the third instruction register 140 and generate a corresponding control signal when a writeback operation is required.

The control circuit 160 decodes the instruction codes of the first instruction register 110 and the second instruction register 130 when a pipeline stall occurs to generate an internal code for multicycle processing and to control the multiplexer. It is a circuit for generating control signals for executing instructions of each step at the same time.

Since it is assumed to be a separate cache, bus collisions do not occur at the time of instruction fetch and data read / write. So you can fetch instructions whenever you need them.

An instruction is input to the first instruction register 110 to begin decoding. At this time, when a pipeline stall occurs, the multiplexer 120 must prevent the instruction of the first instruction register 110 from entering and prevent the instruction of the first instruction register 110 from generating an incorrect control signal in the control circuit 160. In this case, the control circuit decodes the instruction codes of the first instruction register 110 and the second instruction register 130 to detect the pipeline stall, and generates a control signal generated by the instruction of the first instruction register 110. Deactivate using an internal masking circuit.

When an instruction does not come due to a pipeline stall, new internal code of the control circuit 160 is applied to the multiplexer 120 to enter the second instruction register to execute, store, and write back in each instruction register. (writeback) through the pipeline.

Although the configuration and operation of the circuit according to the present invention are illustrated in accordance with the above description and the drawings, this is merely an example, and various changes and modifications are possible without departing from the technical spirit of the present invention.

As mentioned above, by extending the pipeline in five steps and using a separate cache, the fetch and decoding circuits can be simplified by eliminating unnecessary circuits such as two prefetch buffers, one multiplexer and routing circuitry therefor.

Claims (2)

In a microprocessor using a pipeline method, A first instruction register for receiving an instruction fetched from the memory and outputting the instruction; A multiplexer for selectively outputting the output of the first instruction register and a predetermined internal code; A second instruction register for inputting an instruction output from the multiplexer and outputting the instruction; A third instruction register which receives an instruction output from the second instruction register and outputs the instruction; A fourth instruction register that receives an instruction output from the third instruction register and outputs the instruction; And When a pipeline stall occurs, the instruction codes of the first and second instruction registers are decoded to perform generation of the internal code and control of the multiplexer for multicycle processing, and output the instruction registers of each stage. And control means for generating a corresponding control signal by using the microprocessor. The method of claim 1, And the memory means is operated with a separate cache.