KR19990063059A - Nonvolatile semiconductor memory device and IC memory card using the same - Google Patents

Abstract

The present invention provides a nonvolatile semiconductor memory device having a high reliability and an IC memory card using the nonvolatile semiconductor memory device, which can change the method of use according to the use.

The IC memory card 10 has multilevel flash memory chips 11a, 11b, 11c and 11d and a controller 12 as main components and has a large storage capacity, A plurality of operation modes can be arbitrarily selected depending on an application such as a use or a storage capacity with a decrease in the speed or the number of times of repeated rewrite assurance lowering but with no decrease in the write / erase speed or the number of times of repeated rewrite assurance.

Description

Nonvolatile semiconductor memory device and IC memory card using the same

The present invention relates to a nonvolatile semiconductor memory device capable of writing binary data or three or more data to a memory cell and an IC memory card using the same.

In a nonvolatile semiconductor memory device such as a flash memory, a binary memory cell structure in which data taking two values of "0" and "1" are recorded in one memory cell transistor is typical.

A so-called multilevel nonvolatile semiconductor memory device has been proposed in which at least three or more data are stored in one memory cell transistor in accordance with the recent demand for increasing the capacity of the semiconductor memory device (for example, " A Multi -Level 32 Mb Flash Memory '95 ISSCC p132).

A nonvolatile semiconductor memory device capable of recording multi-value data including binary data is generally used as a so-called data storage device.

As the data storage device uses flash memory, a large-capacity memory such as a 64M-bit NAND type flash memory has started to appear, and a market for a large-capacity product such as a digital still camera is also being activated.

Therefore, an IC (Integrated Circuit) memory card using a flash memory as a storage medium has been proposed and put into the market, and some digital still cameras have been adopted.

In recent years, although a flash memory card is used for storage of still pictures in a digital still camera, it is expected that the use of the flash memory card will be extended to music recording and moving picture storage in the future.

In order to increase the capacity of the flash memory card, it is necessary to increase the capacity of the flash memory chip. However, in order to increase the capacity of the flash memory, in addition to the scaling of the semiconductor, there is a memory cell that stores a plurality of data It is also realized by compassion.

In general, if the memory cell is multi-valued, the memory capacity is increased, but on the other hand, the writing speed and the reading speed are lowered and the number of repeated rewrite assurance times is lowered.

That is, in a flash memory card using a multilevel flash memory, the write / read speed is lowered and the number of repeated rewrite assurance times is lowered compared with a flash memory card using a non-multivalued flash memory.

In an information device represented by a portable personal computer or a portable information terminal, since the number of times of repeated rewriting to the flash memory card used in these devices is large, the use of a flash memory card equipped with a non-multivalued flash memory is suitable .

The number of repeated rewrite guarantees is about 100,000 times.

However, in general consumer apparatuses, particularly AV (Audio Video) apparatuses for recording static or music or moving pictures, the number of times of repeated rewriting of data in the flash memory card is small and a flash memory card loaded with a multi- Is expected.

The number of such repeated rewrite assurance is 10,000 or less.

It should be noted that a flash memory card loaded with a multi-value flash memory has a smaller storage capacity of the card, that is, a lower unit price than a flash memory card loaded with a flash memory, rather than a multi-value flash memory card.

As described above, the flash memory card equipped with the multi-value flash memory is suitable for use in consumer electronic devices.

As described above, it is presumed that the flash memory card will be divided into two types, one in which the writing / reading speed is fast and the number of times of repeated rewrite guarantee is large, and the one in which the writing / reading speed is slow and the number of repeated rewriting is small.

Therefore, the user is faced with the problem of selecting a product limited to one of them depending on the application.

Therefore, it is necessary to develop dedicated flash memory cards and dedicated flash memory chips and dedicated controllers for controlling them.

The present invention has been made in view of such circumstances, and an object thereof is to provide a highly reliable nonvolatile semiconductor memory device capable of changing the method of use according to the use and an IC memory card using the same.

1 is a block diagram showing an embodiment of an IC memory card (flash memory card) system using a nonvolatile semiconductor memory device according to the present invention.

2 is a diagram for explaining a mode in which the entire data storage area of the IC memory card is set to the LP mode or SP mode.

Fig. 3 is a diagram for explaining a mode in which the LP mode or the SP mode is set for each part of the storage area of the IC memory card. Fig.

4 is a block diagram showing a configuration example of a flash memory chip according to the present invention;

FIG. 5 is a circuit diagram showing a specific configuration example of the memory array and the main decoder of FIG. 4;

6 is a circuit diagram showing a concrete configuration example of a binary (value) / multi-value latch and a sense amplifier circuit;

FIG. 7 is a timing chart for explaining the operation of the circuit of FIG. 6 at the time of four-value reading. FIG.

8 is a timing chart for explaining the operation in the four-value program of the circuit of Fig.

Fig. 9 is a timing chart for explaining the operation of releasing the binary value of the circuit of Fig. 6; Fig.

10 is a timing chart for explaining the operation in the binary programming of the circuit of Fig.

11 is a diagram for explaining a method of recording mode data.

Fig. 12 is a view for explaining a method of making a card dedicated to the LP mode or a card dedicated to the SP mode by giving a feature to a part of the external appearance of the card.

13 is a flowchart showing an LP / SP mode switching process based on the number of times of rewrite guarantee.

DESCRIPTION OF THE REFERENCE NUMERALS

A main memory and a main memory are connected to the main memory and the main memory, respectively.

113: sub-decoder, 114: binary / multi-value latch and sense amplifier circuit (LS).

In order to achieve the above object, the present invention provides a nonvolatile semiconductor memory device having a memory array region in which a plurality of memory cell transistors capable of storing binary data or three or more-value multivalue data are arranged, And means for changing and storing the storage capacity of the area.

The present invention also provides a nonvolatile semiconductor memory device having a memory array region in which a plurality of memory cell transistors capable of storing binary or tertiary multi-valued data are arranged, And means for storing data by changing the number of levels of multi-value data to change the storage capacity.

In the present invention, the means for changing the number of levels of the multivalued data changes the number of levels of the multivalued data according to an operation mode signal from the outside.

In the present invention, the operation mode is a first mode having a large storage capacity and a second mode having a small storage capacity, and the means capable of changing the number of levels of the multivalued data is set to a number of levels of multivalued data in the first mode Is set higher than the number of levels of the second multivalued data.

In the present invention, the means for changing the number of levels of the multivalued data can change the maximum storage capacity in accordance with an operation mode signal from the outside, and changes the number of levels of the multivalued data according to the maximum storage capacity.

In the present invention, the means for changing the number of levels of the multivalued data is such that, when the storage capacity is changed for each part of the storage area, the corresponding change is made for each block which is a write / erase unit.

The nonvolatile semiconductor memory device of the present invention writes and reads data in page units.

Further, in the present invention, when the number of levels of the multivalued data is reduced so that the page size is kept constant even if the number of levels of the multivalued data is changed, the page has a plurality of columns accessed as one page when the number of levels of the multivalued data is high .

Further, the present invention has a counter for counting the number of times of writing / erasing in the mode in at least one of the plurality of operation modes.

In the present invention, the means for changing the number of levels of the multilevel data is such that, when the storage capacity is changed for each part of the recording area, the change is made for each block which is a write / erase unit, And a counter for counting the number of times of writing / erasing in the corresponding mode in the at least one storage capacity mode among the modes.

In the present invention, the means for changing the number of levels of the multilevel data is a means for changing the number of levels of the multilevel data so that the minimum storage capacity of at least a part of the recording area becomes small when the counter exceeds the number of guaranteed rewrite times in the mode. To a lower setting.

Further, in the present invention, when the number of levels of the multivalued data is set to be low so that the maximum storage capacity is reduced, it has means for notifying the outside that such change has occurred.

According to another aspect of the present invention, there is provided an IC memory card capable of recording / reproducing data with an external device, comprising: a memory array region in which a plurality of memory cell transistors capable of storing binary or tri- And a nonvolatile semiconductor memory device having means for changing and storing the storage capacity of a certain area.

According to another aspect of the present invention, there is provided an IC memory card capable of recording / reproducing data with an external device, comprising: a memory array region in which a plurality of memory cell transistors capable of storing binary or tri- Volatile semiconductor memory device having a means capable of storing by changing the number of levels of multi-value data to be stored in a certain area and changing the storage capacity.

In the present invention, the means for changing the storage capacity changes the storage capacity in accordance with an external signal.

In the present invention, the operation mode is a first mode having a large storage capacity and a second mode having a small storage capacity, and the means capable of changing the number of levels of the multivalued data is a means for changing the number of levels of multivalued data in the first mode to Is set higher than the number of levels of the second multivalued data.

In the present invention, a characteristic section for setting a storage capacity is formed on the card, the external device identifies the storage capacity according to the characteristic section of the card, and the means for changing the storage capacity is a The memory capacity is changed accordingly.

In the present invention, the means for changing the number of levels of the multilevel data is such that, when the storage capacity is changed for each part of the recording area, the corresponding change is made for each block which is a write / erase unit.

In the IC memory card of the present invention, the nonvolatile semiconductor memory device writes and reads data in page units.

In the present invention, when the number of levels of multiple-value data is reduced so that the page size is kept constant even if the number of levels of multiple-value data is changed, I have.

Further, the present invention has a counter for counting the number of times of writing / erasing in the mode in at least one of the plurality of operation modes.

In the present invention, the means for changing the number of levels of the multi-valued data is such that, when the storage capacity is changed for each part of the recording area, the change is made for each block which is a write / erase unit, And a counter for counting the number of repetitions of writing / erasing in the mode in at least one storage capacity mode.

According to the present invention, the means for changing the number of levels of the multivalued data is a means for changing the number of levels of the multivalued data so that the minimum storage capacity of at least a part of the memory area is reduced when the counter exceeds the number of guaranteed rewrite in the mode. Change the number of levels to a lower setting.

Further, in the present invention, when the number of levels of the multivalued data is set to be low so as to reduce the maximum storage capacity, it has means for notifying the outside that such change has occurred.

According to the present invention, the storage capacity is identified by an external device based on designation of an external signal or a feature formed on the IC memory card. The storage capacity is changed in accordance with the signal from the external device by the means capable of changing the storage capacity.

As a characteristic portion of the IC memory card, it is possible to change the mode of the maximum storage capacity by an electric switch, or to indicate the notch position and size of the card, the position and size of the hole shape of the card, And identification by a slide switch that can freely change the external shape.

When changing the maximum capacity, the number of levels of the multilevel of the flash memory mounted on the card is changed in accordance with the maximum memory capacity.

When the storage capacity is changed for each part of the recording, the mode is set for each block, which is a unit for writing / erasing the memory, as the minimum unit of the change. A function of making a plurality of pages as one page is provided so that the page size (for example, 512 bytes) is not changed when the storage capacity is changed.

In addition, for example, in the mode of at least one storage capacity by the count, the number of repetitions of writing / erasing in the mode is counted and the number of times of writing / erasing is recorded. When the number of times of repeated rewrite assurance in the mode is exceeded, the signal is sent to the external device, and after that, all or a part of the memory setting mode is used by reducing the maximum memory capacity.

Next, embodiments of the present invention will be described with reference to the drawings.

1 is a block diagram showing an embodiment of an IC memory card (flash memory card) system using a nonvolatile semiconductor memory device according to the present invention.

As shown in Fig. 1, the IC memory card system is constituted by a host device 20 capable of recording / reproducing data with the IC memory card 10 and the IC memory card 10.

The IC memory card 10 is provided with the multilevel flash memory chips 11a, 11b, 11c and 11d and the controller 12 as main components and has a large storage capacity, A plurality of operation modes can be arbitrarily selected in accordance with an application such as a use with a reduced number of guarantees or a use of which the storage capacity is small but the write / erase speed or the number of times of repeated rewrite assurance does not decrease.

The IC memory card 10 can be applied to the information device as the host device 20 and also to the general consumer device only by changing the mode setting.

Next, for ease of understanding, it is assumed that the use of a memory having a large storage capacity and a decrease in the write / erase speed or the guaranteed number of times of repeated rewrite is set to the LP (Long Play) mode, The use without a decrease in the number of times of guaranteed writing will be described as an SP (Short Play) mode.

The mode setting in the IC memory card 10 according to the present embodiment is such that the entire data storage area of the IC memory card 10 is set to the LP mode or SP mode as shown in Figs. As shown in Figs. 3 (A) and 3 (B), it is possible to take a form in which the LP mode or the SP mode is set for each storage area portion of the IC memory card 10. [

In the case of setting the LP mode or the SP mode for each part of the storage capacity, as shown in Fig. 3A, the write / erase unit (block) of the flash memory (for example, (In the case of a two-value 64-Mbit flash memory, an erase unit of 8 Kbytes), and a mode in which a mode is set for each mounted flash memory chip as shown in FIG. 3 (B).

In the example shown in Fig. 3B, the flash memory chip is mounted on four chips.

The multilevel flash memory chips 11a to 11d receive the control signals S12a to S12d including the operation mode command from the controller 12 and change the number of levels of the multilevel data to store the data from the host device 20. [ Or reads out the data.

The number of levels of the multivalued data may be changed by, for example, 2 bits (4 values) / cells 1 bit (2 values) / cells, 3 bits (8 values) / cells 2 bits 8 value) / cell? 1 bit (binary value) / cell or the like can be changed.

Under the control of the controller 12, in the LP mode, the number of multi-valued data is controlled to be increased to increase the storage capacity. In the SP mode, the number of multi-valued data is decreased to control the storage capacity to be decreased .

Next, the case of changing the 2-bit (4-value) / cell / 1-bit (2-value) / cell is explained as an example in the present embodiment.

4 is a block diagram showing a configuration example of the flash memory chips 11a (11d) according to the present invention.

4, the flash memory chip 11 is constituted by a memory array 111, a main decoder 112, a sub-decoder 113 and a multi-value latch and a sense amplifier circuit (LS) 114 have.

The memory array 111 is constituted by a data area 111a and a spare area 111b. In the spare area 111b, for example, management information of data stored in the data area 111a is stored.

The data area 111a and the spare area 111b are driven by one main decoder 112. [

5 is a circuit diagram showing a specific configuration example of the memory array 111 and the memory decoder 112. As shown in FIG. In Fig. 5, a NAND type flash memory is shown as an example.

As shown in FIG. 5, the memory array 111 includes memory strings STRG0, STRG1, ..., STM, STM, STM, STM, STM, STM, STM, Are arranged in a matrix form.

Then, for example, the string STRG1 is allocated as the data area 111a, and the string STRG1 is allocated as the spare area 111b.

The selection transistor ST0 connected to the drain of the memory transistor M0 of the memory string STRG0 is connected to the bit line BL0 and the selection transistor ST0 connected to the drain of the memory transistor M0 of the memory transistor STRG1 is connected to the bit line BL1.

In addition, the selection transistor ST1 to which the memory transistor M7 of each memory string STRG0, STRG1 is connected is connected to the common source line SL.

The gate electrodes of the memory transistors of the memory strings STRG0 and STRG1 arranged in the same row are connected to the common word lines WL0 to WL7, the gate electrode of the selection transistor ST0 is connected to the common selection gate line DSG0, Are connected to a common select gate line SSG0.

The main decoder 112 includes a main row decoder 120 and a group of transfer gates 130 whose conduction state is controlled by the main column decoder 120, And the supply line Vpp1 of the program voltage Vpp connected to the main column decoder 120. The driving voltage supply lines VCG0 to VCG7, VDSG, and VSSG for the word line and the selection gate line,

The transfer gate group 130 is composed of transfer gates TW0 to TW7, TD0, TS0 and TF0.

Specifically, each of the transfer gates TW0 to TW7 operatively connects the word lines WL0 to WL7 and the drive voltage supply lines VCG0 to VCG7 according to the output signal BSEL of the main column decoder 120, and the transfer gates TD0 and TS0 are the same SSG0 and the driving voltage supply lines VDSG and VSSG in accordance with the output signal BSEL of the main column decoder 120. [

The transfer gate TF0 is provided to prevent the selection gate line DSG0 from becoming a floating state in the case of non-selection, and connects the selection gate line DSG0 to the ground line in non-selection.

The main column decoder 120 includes a three-input NAND circuit NA 121, inverters INV 121 and INV 122, a two-input NAND circuit NA 122, a depletion type NMOS transistor NT 121, an enhancement type NMOS transistor NT 122 (low- A threshold voltage), NT123, and a capacitor C121 formed by coupling the source and the drain of the MOS.

Input terminals of the NAND circuit NA 121 are connected to the input lines of the address decode signals X 1, X 2 and X 3, respectively, and the output terminal is connected to the input terminal of the inverter INV 121.

The output terminal of the inverter INV121 is connected to one input terminal of the NAND circuit NA122 and the input terminal of the inverter INV122 and also receives the source of the NMOS transistor NT122 through the NMOS transistor NT121 whose gate is connected to the supply terminal SEP of the control signal, And is connected to the gate electrode of the transistor NT123.

The other input terminal of the NAND circuit NA122 is connected to the input line of the clock signal CLK and the output terminal is connected to one electrode of the capacitor C121. The other electrode of the capacitor C121 is connected to the drain and gate electrodes of the NMOS transistor NT122 and the connection point between the drain and the gate electrode is connected to the program voltage supply line Vpp1 through the NMOS transistor NT123.

The output terminal of the inverter INV122 is connected to the gate of the transfer gate TFD0 of the transfer gate group (group) 130. [

In such a configuration, data reading of the memory transistor M3 of the memory strings STRG0 and STRG1 and data writing into the memory transistor M3 are performed as follows.

At the time of reading, the ground voltage GND (0V) is supplied to the driving voltage supply line VCG3 by a sub-decoder (not shown), and P5V (for example, 4.5V) is applied to the driving voltage supply lines VCG0 to VCG2, VCG4 to VCG7 and driving voltage supply lines VDSG and VSSG V is supplied, and P5V is supplied to the program voltage supply line Vpp1, and the ground voltage 0V is supplied to the source line SL.

Active address signals X1, X2 and X3 are inputted to the main column decoder 120 and the output signal BSEL of the main column decoder 120 is outputted at a level of P5V + alpha.

As a result, the transfer gates TW0 to TW7, TD0 and TS0 of the transfer gate group 130 become conductive. At this time, the transfer gate TF0 is held in a non-conductive state.

As a result, the select transistors ST0 and ST1 of the memory strings STRG0 and STRG1 are turned on, and data is read out to the bit lines BLO and BL1.

A high voltage, for example, 20 V is supplied to the drive voltage supply line VCG3 selected by the sub-decoder 13 and an intermediate voltage (for example, 10 V) is applied to the drive voltage supply lines VCG0 to VCG2 and VCG4 to VCG7, The power supply voltage _Vcc (for example, 3.3 V) is supplied to the VDSG, the ground voltage GND is supplied to the driving voltage supply line VSSG, and 20 V, for example, is supplied to the program voltage supply line Vpp1.

A ground voltage GND is connected to a bit line BL0 to which a memory string STRG0 having a memory transistor M3 to be written is connected and a power supply voltage _Vcc is applied to a bit line BL1 to which a memory string STRG1 having a memory transistor M3 to be inhibited from writing is connected .

The active address signals X1, X2 and X3 are inputted to the main column decoder 120 and the output signal BSEL of the main column decoder 120 is outputted at a level of 20 V + α.

As a result, the transfer gates TW0 to TW7, TD0 and TS0 of the transfer gate group 130 become conductive.

As a result, a write voltage 20V is applied to the selected word line WL3, and a pass voltage (intermediate voltage) Vpass (for example, 10V) is applied to the unselected word lines WL0 to WL2 and WL4 to WL7.

Thereby, the selection transistor ST0 of the memory string STRG1 is put in a cut-off state, and the channel portion of the memory string STRG1 to which the memory transistor to be inhibited from writing is connected becomes a floating state. As a result, the potentials of these channel portions are boosted by the capacitor coupling with the pass voltage Vpass applied to the unselected word lines, rise to the write prohibition voltage, and writing of data to the memory transistor M3 of the memory string STRG1 is prohibited do.

On the other hand, the channel portion of the memory string STRG0 to which the memory transistor to be written is connected is set at the ground voltage GND (0V), and data is written to the memory transistor M3 by the potential difference with the writing voltage 20V applied to the selected word line WL3 And the threshold voltage shifts in the positive direction, for example, from -3V to 2V in the erase state.

The sub decoder 113 outputs control signals SLP (S12a to S12d) indicating the LP mode operation from the controller 12 in the case of using a device having a large storage capacity but a decrease in the write / erase speed or the number of guaranteed rewrite times ), Or as a multi-value latch and sense amplifier circuit. When the memory 12 is used and the memory capacity is small but the write / erase speed or the number of guaranteed times of repeated rewriting are not reduced, the controller 12 instructs the SP mode operation Receives the control signals SSP (S12a to S12d), and supplies a drive voltage according to the operation mode to the main decoder 112. [

The dual-purpose / multi-value-added latch and sense amplifier circuit (LS) 114 receives the LP mode operation from the controller 12 when the storage capacity is large but the write / erase speed or the number of repeated re- (S12a to S12d) indicating the effect of the latching operation and operates as a latch circuit for latching and latching, and when the latch circuit is used for a latch circuit having a small storage capacity but without a decrease in the write / And receives control signals SSP (S12a to S12d) indicating that the SP mode operation is being performed from the control circuit 12, and operates as a latch circuit for two-way and a sense amplifier circuit.

Fig. 6 is a circuit diagram showing a concrete configuration example of the two-value / multi-value latch and the sense amplifier circuit (LS) 114. As shown in Fig. In Fig. 6, a NAND type flash memory is shown as an example.

6, the two-value / multiple-value latch and sense amplifier circuit 114 includes NMOS transistors NT1401 to NT1422, PMOS transistors PT1401 and PT1402, an inverter INV1401, and latch circuits Q141 and Q142 .

The NMOS transistor NT1401 is connected between the supply line and the bit line BLD0 of the power source voltage V _CC, the gate electrode is connected to the supply line of the disable signal IHB1. The NMOS transistor NT1402 is connected between the supply line and the bit line BLD1 in the power supply voltage V _CC, is connected to the supply line of the gate electrode is prohibited IHB2 signal.

A depletion-type NMOS transistor NT1423 is connected between the connection point of the bit line BLD0 and the NMOS transistor NT1401 and the connection point of the memory string STRGD0 and the bit line BLD0. The connection point of the bit line BLD1 and the NMOS transistor NT1402, the memory string STRGD1, And a depletion type NMOS transistor NT1424 is connected between the node and the connection point with BLD1. The gates of the NMOS transistors NT1423 and NT1424 are connected to a decoupling signal supply line DCPL.

The NMOS transistors NT1403, NT1405 and NT1419 are connected in series between the connection point of the bit line BLD0 and the NMOS transistor NT1401 and the bus line IO _i and the connection point between the bit line BLD1 and the NMOS transistor NT1402 and the bus line IO _{i +} NMOS transistors NT1404, NT1406, and NT1420 are connected in series.

The node SA1 comprising the connection point between the NMOS transistors NT1403 and NT1405 is grounded through the NMOS transistor NT1407, connected to the drain of the PMOS transistor PT1401, and also connected to the gate electrode of the NMOS transistor NT1408 via the NMOS transistor NT1418.

A node SA2, which is a node between the NMOS transistors NT1404 and NT1406, is connected to the drain of the PMOS transistor PT1402 and the gate electrode of the NMOS transistor NT1413.

The node SA1 and the node SA2 are connected through the NMOS transistor NT1416, and the gate electrode of the NMOS transistor NT1413 and the gate electrode of the NMOS transistor NT1408 are connected through the NMOS transistor NT1417.

Then, the gate of the NMOS transistor NT1407 is connected to the supply line of a reset (reset) signal RST, the source of the PMOS transistor PT1401 is connected to the supply line of the power supply voltage V _CC, the supply of the gate of the PMOS transistor PT1401 signal Vref1 line Respectively.

In addition, the source of the PMOS transistor PT1402 is connected to the supply line of the power supply voltage V _CC, the gate of the PMOS transistor PT1402 is connected to the supply line of the signal Vref2.

Further, the gate electrodes of the NMOS transistors NT1416 and NT1417 are connected to the supply line of the LP mode signal (multiple value) signal SLP, and the gate electrode of the NMOS transistor NT2418 is connected to the supply line of the SP mode signal SSP.

The first memory node N141a of the latch circuit Q141 is connected to the connection point between the NMOS transistors NT1405 and NT1419 and the second memory node N141b is grounded through the NMOS transistors NT1408 to NT1410 connected in series.

The first memory node N142a of the latch circuit Q142 is connected to the connection point between the NMOS transistors NT1406 and NT1420 and the second memory node N142b is grounded through the NMOS transistors NT1413 to NT1415 connected in series.

In addition, the connection point of the NMOS transistors NT1408 and NT1409 is grounded through the NMOS transistors NT1411 and NT1412 connected in series.

The gate of the NMOS transistor NT1409 is connected to the first memory node N142a of the latch circuit Q142, the gate of the NMOS transistor NT1410 is connected to the supply line of the latch signal øLAT2, the gate of the NMOS transistor NT1411 is connected to the second memory node N142b, The gate of the NMOS transistor NT1412 is connected to the supply line of the latch signal øLAT1, and the gates of the NMOS transistors NT1414 and NT1415 are connected to the supply line of the latch signal øLAT3.

The gate of the NMOS transistor NT1419 serving as the column gate is connected to the supply line of the signal Yi, and the gate of the NMOS transistor NT1420 is connected to the supply line of the signal Yi + 1.

Also, the input terminal of the inverter INV1401 is grounded. And the output terminal is connected to the self-determination circuit 141. In addition, the NMOS transistors NT1421 and NT1422 are connected in parallel between the output terminal of the inverter INV1401 and the ground line. The gate electrode of the NMOS transistor NT1421 is connected to the second memory node N141b of the first latch circuit Q141 and the gate electrode of the NMOS transistor NT1422 is connected to the second memory node N142b of the second latch circuit Q142.

The determination circuit 141 determines whether or not the writing to all the memory cell transistors has been completed with the potential of the output line of the inverter INV1401 at the time of the writing operation. And outputs a signal S _END .

Specifically, when the writing is completed, the first memory nodes N141a and 142a of the latch circuits Q141 and Q142 are at the power supply voltage _Vcc level, and the second memory nodes N141b and 142b are at the ground level. As a result, the NMOS transistors NT1421 and NT1422 are maintained in the non-conductive state, and the potential of the output line of the inverter INV2401 becomes the power supply voltage _Vcc level, thereby judging that the writing is completed.

On the other hand, when there is a cell which is not sufficiently written, either or both of the first memory nodes N141a and 142a of the latch circuits Q141 and Q142 are at the ground level and the second memory nodes N141b and 142b are at the ground voltage, Level. As a result, it is determined that the NMOS transistor NT1421 or NT1422, or both transistors, are kept conductive and the potential of the output line of the inverter INV1401 is at the ground level, whereby there is an insufficient cell.

Here, an example of the operation of reading and writing (programming) the binary / multi-value latch and the sense amplifier circuit 114 will be described with reference to Figs. 7, 8, 9, and 10. Fig.

Fig. 7 shows a timing chart at the time of four-value writing (program), and Fig. 8 shows a timing chart at the time of four-value writing (program). Fig. 9 shows a timing chart at the time of binary reading, and Fig. 10 shows a timing chart at the time of binary writing (program).

As can be seen from Fig. 8, the four-value writing in this example is performed in three steps, and the steps are shifted to the next step at the stage where all the cells which are to be written in page by page in each step are judged to be sufficient for writing. However, the present invention is not limited to this writing method.

First, when reading or writing four-level data, the LP mode signal SLP is input at an active high level, and the SP mode signal SSP is input at a low level (Figs. 7 and 8 Not shown).

As a result, the NMOS transistors NT1416 and NT1417 are turned on, the NMOS transistor NT1418 is kept in a non-conductive state, the nodes SA1 and SA2 are electrically connected, and the potential of the node SA1 is connected to the gate electrode of the NMOS transistor NT1408 by the NMOS transistor NT1418 Lt; / RTI >

The quaternion read operation will be described.

First, the reset signal RST and the signals PGM1 and PGM2 are set to the high level. As a result, the first memory nodes N141a and N142a of the latch circuits Q141 and Q142 are pulled to the ground level. As a result, the latch circuits Q141 and Q142 are cleared.

Next, the word line voltage is set to, for example, 2.4 V, and reading is performed. When the threshold voltage Vth is higher than the word line voltage (2.4V), the cell current does not flow, so that the bit line voltage maintains the precharge voltage and the high is sensed. On the other hand, if the threshold voltage Vth is lower than the word line voltage (2.4V), the cell current flows and the bit line voltage drops and the row is sensed.

Next, for example, a read operation is performed at a word line voltage of 1.2 V, and finally, a read operation is performed at a word line voltage of 0 V. Then, the data is read out three times, converted into 2-bit data, and then output to the IO.

Specifically, when the cell data is 0, since no current flows in all the word lines, (1, 1) is output to the buses IO _{i + 1} and IO _i . First, when the word line voltage is read as 2.4 V, the latch signal? LAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT1408 is maintained in the conduction state, and the second memory node N142b of the latch circuit Q142 is maintained at the high level So that the NMOS transistor NT1411 is maintained in a conductive state. Therefore, the NMOS transistors NT1408, NT1411, and NT1412 are maintained in the conductive state, the second memory node N141b of the latch circuit Q141 is pulled to the ground level, and the first memory node N141a of the latch circuit Q141 transitions to the high level .

Next, for example, when the word line voltage is read as 1.2 V, the latch signal? LAT3 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT1413 is maintained in the conduction state, the second memory node N142b of the latch circuit Q142 is pulled to the ground level, The node N142a transits to the high level. Finally, when the word line voltage is read as 0 V, the latch signal? LAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT1408 is maintained in the conduction state. However, since the second memory node N142b of the latch circuit Q142 is at the low level, the NMOS transistor NT1411 becomes non- The first memory node N141a of the latch circuit Q141 maintains the high level.

When the cell data is 1, a current flows only in the case of a predetermined word line voltage, and ( ₁ , 0) is output to the buses IO _{i + 1} and IO _i . First, when the word line voltage is read as 2.4 V, the latch signal? LAT1 is set to the high level. At this time, since the cell current flows, the bit line is maintained at the low level, so that the NMOS transistor NT1408 is kept in the non-conductive state and the first memory node N141a of the latch circuit Q141 is kept at the low level.

Next, when the word line voltage is read as 1.2 V, the latch signal? LAT3 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT1413 is maintained in the conduction state, the second memory node N142a of the latch circuit Q142 is pulled to the ground level, The node N142a transits to the high level. Finally, when the word line voltage is read as 0 V, the latch signal? LAT1 is set to the high level. At this time, since the cell current does not flow, the bit line is maintained at the high level, so that the NMOS transistor NT1408 is maintained in the conduction state. However, since the second memory node N142b of the latch circuit Q142 is at the low level, the NMOS transistor NT1411 becomes non- The first memory node N141a of the latch circuit Q141 maintains a low level.

Similarly, when the cell data is 10 and 11, (0, 1) and (0, 0) are read out to the buses IO _{i + 1} and IO _i , respectively.

Next, the write operation will be described.

In the circuit of Fig. 6, the data is first written by the data stored in the latch circuit Q141, and then by the data of the latch circuit Q142 and finally the latch circuit Q141.

If the write data is (Q2, Q1) = (1, 0), the latch circuit Q141 inverts from 0 to 1 when the write becomes sufficient, but when (Q2, Q1) = It is necessary to use it also as the write data of the third step. Therefore, even if the write is sufficient in the first step, it is not inverted from 0 to 1.

The write completion determination in each step is made when the latched data is in mode 1 and the writing of that step is determined to be completed.

In the cell of the write data (Q2, Q1) = (0, 0), the inversion of the latch circuit Q141 does not occur in the first step, and thus the end determination by the wired OR is not performed.

In the case of reading or writing binary data, the SP mode signal SSP is input at the active high level and the LP mode signal SLP is input at the low level (not shown in FIGS. 7 and 8).

As a result, the NMOS transistor NT1418 is maintained in the conduction state, the NMOS transistors NT1416 and NT1417 are brought into the non-conduction state, and the nodes SA1 and SA2 are electrically disconnected. The potential of the node SA1 is directly transferred to the gate electrode of the NMOS transistor NT1408 through the NMOS transistor NT1418.

In addition, both Ai and / Ai are selected (all V _CC ) and IHB1 and IHB2 are all fixed to GND, so that the bit line and the data latch are in a one-to-one relationship, and binary operation becomes possible.

Here, a detailed description of the reading and writing at binary is omitted.

In the read / identify control, the potential of the node SA2 is reflected in the latch circuit Q142 by setting the signal? LAT3 to the high level, and the signals? LAT1 and? LAT2 are set to the high level at the same time so that either the NMOS transistor NT1411 or the NMOS transistor NT1409 conducts State, and the potential of the node SA1 is reflected in the latch circuit Q141.

As described above, for example, when the nonvolatile semiconductor memory device of the present embodiment is applied to an IC memory card, a multi-value flash memory capable of replacing (replacing) the two-value flash memory is realized without changing the specifications of the IC memory card do.

The controller 12 receives the mode switching signal S20 for switching to the LP / SP mode transmitted from the host device 20, for example, and outputs the control signals S12a to S12d according to the LP mode or the SP mode to the flash memory chips 12a- 12d to carry out the transfer (reception) of data between the host apparatus 20 and each of the flash memory chips 12a to 12d, that is, the writing (and erasing) operation or the reading operation.

The controller 12 outputs a mode identification signal S12 to the host apparatus 20 to notify which mode of the LP / SP the IC memory card 10 is currently set to.

The LP / SP mode switching signal S20 can be sent to the IC memory card 10 as a command from time to time by the user of the host device 20, if the host device 20 is in the mode of both.

If the host apparatus 20 is limited to either mode, the mode switching signal S20 is automatically sent from the host apparatus 20 to the IC memory card 10 and used only in a specific mode.

Then, the mode identification signal S12 is outputted from the IC memory card 10 to the host apparatus, so that the host apparatus 20 performs processing (read operation, etc.) of data in accordance with the mode.

The controller 12 performs processing for switching the binary / multi-value data latches and for making the page size constant at all times by the control signals S12a to S12d for controlling the number of levels of the multilevel data in the multilevel flash memory .

The mode set in the IC memory card 10 of the controller 12 must be stored in any one of the IC memory cards. However, the storage of the mode data can be performed, for example, As shown in Fig.

The method shown in Fig. 11 (A) is a method for storing a mode for each page unit, which is a unit for writing / reading a flash memory.

Specifically, a spare area (a management area) in a page (in the NAND flash memory, one byte of a spare area (redundant area) 111b) is allocated to this memory.

The method shown in Fig. 11 (B) is a method for concentrating and storing mode data in a specific area (block) of the flash memory.

The method shown in Fig. 11 (C) is a method for making a nonvolatile memory such as an EEPROM on-chip to the controller 12 and storing the setting mode on the EEPROM.

The stored mode data is stored intensively in the mode data of the entire IC memory card 10 or in the minimum unit (block) of the flash memory.

The nonvolatile memory such as the EEPROM may be formed in a separate chip configuration from the controller 12. [

By adopting the above method, the IC memory card 10 can be mixed with the LP / SP mode as described with reference to Fig.

When the number of levels of the multivalued data is made low so that the page size is kept constant even when the number of levels of the multivalued data is changed when the storage capacity is changed, Write / read) to one page.

More specifically, the controller 12 controls, for example, to make two lines of two values accessed in four values be one page in binary when the four values are binary values.

Next, the operation of the system shown in Fig. 1 will be described.

When the IC memory card 10 is set in the host apparatus 20, for example, the mode data stored in the controller 12 of the IC memory card 10 by the method shown in Fig. 11 is read out, And the mode identification signal S12 indicating the set mode is output to the host device 20. [

The mode switching signal S20 is supplied from the host apparatus 20 side to the IC memory card 10 so as to record the data in the LP mode or SP mode desired by the user of the host apparatus 20 by receiving the mode identification signal S12, .

The mode switching signal S20 also indicates whether all or part of the IC memory card 10 is used in the LP / SP mode.

Then, in the IC memory card 10 receiving the mode switching signal S20, mode data is recorded by a predetermined method under the control of the controller 12. [

The LP / SP mode switching signal S20 is sent to the IC memory card 10 as a command from time to time by the user of the host device 20 if the host device 20 supports both modes.

If the host device 20 is limited to either mode, the mode switching signal S20 is automatically sent from the host device 20 to the IC memory card 10 and used only in the specific mode.

In the IC memory card 10, data processing (read operation, etc.) according to the mode specified by the mode identification signal S12 is performed.

The write and read operations in the flash memory chips 11a to 11d according to the LP / SP mode are performed as described with reference to FIGS. 4 to 10 (detailed description thereof is omitted here).

As described above, according to the present embodiment, it is possible to change the maximum storage capacity of the whole or part of the IC memory card 10, and in applications where the write / read speed is fast or the number of repeated rewrite assurance is required, Is set to be a small mode and the maximum memory capacity is set to a large mode in applications where the writing / reading speed is slow or the number of repeated rewrite assurance is not required, the same IC memory card 10 is used There is an advantage that a change can be made.

In the present embodiment, the modes are switched by the number of commands to the host apparatus 20. However, in the case where the entire IC memory card 10 is used only in the LP mode or the SP mode, for example, It is also possible to use a card dedicated to the LP mode or a card dedicated to the SP mode by imparting a characteristic to a part of the external appearance of the card using the method shown in Fig.

In this case, the host device 20 does not perform the mode identification based on the mode identification signal S12 sent from the IC memory card 10, but performs the mode identification on the IC memory card 10.

The method shown in Fig. 12A is a method in which a slide switch 10a is provided on the periphery of the IC memory card 10 and the LP mode dedicated card or SP mode dedicated card is identified by the position of the slide switch 10a to be.

The method shown in Fig. 12 (B) is a method in which a hole or a hollow 10b is formed in the periphery of the IC memory card 10, and the position of the hole or the hole 10b, Or whether it is a dedicated SP mode mode card.

The method shown in Fig. 12C is a method in which a notch 10c is formed in the peripheral portion of the IC memory card 10 and whether or not the notch 10c is present or not is discriminated from the LP mode dedicated card or the SP mode dedicated card to be.

The method shown in Fig. 12 (D) is a method in which an electric on / off switch 10d is provided in the peripheral portion of the IC memory card 10 and, in accordance with the on / off signal according to the setting of the on / off switch 10d, It is a method of identifying whether it is a card for LP mode only or a card for SP mode only.

The number of times of repeated rewriting in the LP mode is smaller than that in the SP mode, and when the number of rewrite assurance times (for example, 10,000 times) in the LP mode is exceeded, the function to be used only in the SP mode thereafter It is possible.

More specifically, a counter for the number of times of rewriting is provided on the on-chip or another chip of the controller 12 of the IC memory card 10, and this count value is set in advance in the LP mode If the value is exceeded, it is used in the SP mode thereafter.

FIG. 13 is a flowchart showing the LP / SP mode switching process based on the number of rewrite assurance times.

In this example, an erasing command is received and a switching determination process is performed.

13 is used in the LP mode having a large storage capacity at the beginning (S1), receives the erase command from the host device 20, and the count value of the counter is read by the controller 12 (S2, S3) . =

In the controller 12, it is determined whether or not the read count value exceeds the preset number of rewrite assurance (S4)

When it is determined in step S4 that the count value does not exceed the rewrite guarantee number, the flash memory chip is erased (S5), the counter is incremented by +1 (S6) , The operation proceeds to the next operation (S7).

On the other hand, if it is determined in step S4 that the count value exceeds the rewrite guarantee number, the host apparatus 20 sends out a warning signal to the host apparatus 20 at the same time that it can be written only in the SP mode (S8).

In step S8, when the erase is performed, the erase operation is performed, the erased block is fixed to the SP mode, and the operation proceeds to the next operation (S9 to S11).

On the other hand, in the case where the erasing is not carried out in the step S8, the erasing operation is not performed and the operation proceeds to the next operation (S12, S13).

As described above, when the number of times of repeated rewriting in the LP mode is smaller than that in the SP mode and the number of times of rewrite assurance in the LP mode is exceeded, by having the function used only in the SP mode thereafter, There is an advantage that a highly reliable IC memory card can be realized.

When the mode is set for each block which is a write / erase unit, the counter is provided for each block.

In the above description, the LP / SP mode used in the so-called AV (Audio Video) apparatus is described as an example, but it goes without saying that the present invention is applicable to other apparatuses and other modes.

For example, not only can you switch between two LP / SP modes, but you can also switch between three or more modes.

Specifically, when the flash memory is 3 bits (8 values), the first mode is used in 3 bits (8 values) / cells, the second mode is used in 2 bits (4 values) / cells, It is also possible to configure it to be used in 1 bit (binary) / cell.

It goes without saying that the present invention is also applicable to other types of IC memory cards.

INDUSTRIAL APPLICABILITY As described above, according to the present invention, there is an advantage that the use method can be changed for the purpose of use.

When the number of levels of the multiple value data exceeds the number of rewrite assurance in the high mode, the number of levels of the multiple value data can be used again in a low number of modes. The usage method can be changed depending on the use, can do.

In addition, the product can be set with the mode fixed by changing the part of the external appearance of the card with the same IC memory card.

Claims (31)

A nonvolatile semiconductor memory device having a memory array region in which a plurality of memory cell transistors capable of storing binary data or multi-value data of a triple or higher value are arranged, Means for changing the storage capacity of at least a part of the memory array area and storing the data Volatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1, wherein the means capable of changing the storage capacity and storing data changes the storage capacity in accordance with an external signal. 1. A nonvolatile semiconductor memory device having a memory array region in which a plurality of memory cell transistors capable of storing binary data or multi-valued data of more than three values are arranged, Means for storing data by changing the number of levels of multi-value data to be recorded in at least a part of the area of the memory array area to change the storage capacity Volatile semiconductor memory device. 4. The nonvolatile semiconductor memory according to claim 3, wherein the means for changing the number of levels of the multivalued data changes the number of levels of multivalued data in accordance with an operation mode signal from the outside. The method of claim 3, The operation mode includes a first mode having a large storage capacity and a second mode having a small storage capacity, Wherein the means for changing the number of levels of the multivalued data sets the number of multivalued data levels in the first mode to be higher than the multivalued data levels in the second mode. 4. The nonvolatile semiconductor memory device according to claim 3, wherein the means capable of changing the number of levels of the multi-value data is capable of changing the maximum storage capacity in accordance with an operation mode signal from the outside, A semiconductor memory device. The nonvolatile semiconductor memory device according to claim 3, further comprising a counter for counting the number of repeated write / erase operations in at least one of the plurality of operation modes. 8. The memory according to claim 7, wherein the means for changing the number of levels of the multi-valued data comprises means for, when the counter exceeds the number of rewrite assurance times repeated in the corresponding mode, To a low set value. A nonvolatile semiconductor memory device having a memory array region in which a plurality of memory cell transistors capable of storing binary data or multi-value data of a triple or higher value are arranged, Means for storing data by changing the number of levels of multi-valued data to be stored in at least a part of the area of the memory array area to change the storage capacity / RTI > The means for storing data by changing the number of levels of the multi-valued data and changing the storage capacity is characterized in that when the storage capacity for the parts of the storage area is changed, the block which is the write / A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 9, wherein said nonvolatile semiconductor memory device performs writing and reading of data in page units. 11. The method according to claim 10, wherein when a number of levels of the multivalued data is high and a plurality of columns to be accessed are set low in a number of levels of the multivalued data, The nonvolatile semiconductor memory device further comprising: The nonvolatile semiconductor memory device according to claim 9, further comprising a counter for counting the number of repeated write / erase operations in at least one of the operation modes. 13. The memory device according to claim 12, wherein the means for changing the number of levels of the multi-valued data includes means for changing at least one of the multi-valued data To a low set value. 13. The nonvolatile semiconductor memory device according to claim 12, further comprising means for informing that external change has occurred when the number of levels of the multivalued data is changed to a lower set value so that the maximum storage capacity is reduced. 14. The nonvolatile semiconductor memory device according to claim 13, further comprising means for informing that external change has occurred when the number of levels of multiple-value data is changed to a low setting value so that the maximum storage capacity is reduced. 1. An IC memory card capable of recording / reproducing data with an external device, A semiconductor memory device comprising: a memory array region in which a plurality of memory cell transistors capable of storing binary data of a binary value or a triple or more are arranged; and means for storing data by changing a storage capacity of at least a partial region of the memory array region Nonvolatile semiconductor memory device ≪ / RTI > 17. The IC memory card according to claim 16, wherein the means for changing the storage capacity changes the storage capacity in accordance with an external signal. 17. The method of claim 16, A feature section for setting a storage capacity is formed in the IC memory card, Wherein the external device identifies a storage capacity according to a characteristic portion of the IC memory card, The means for changing the storage capacity may change the storage capacity in accordance with a signal from the external device IC memory card. 1. An IC memory card capable of recording / reproducing data with an external device, A memory array region in which a plurality of memory cell transistors capable of storing multi-valued data having a binary value or a triple or more value are arranged; and a control means for changing the number of levels of multi-value data to be stored in at least a part of the memory array region, Volatile semiconductor memory device having means for storing data by changing ≪ / RTI > 20. The IC memory card according to claim 19, wherein the means for changing the storage capacity changes the storage capacity in accordance with an external signal. 21. The method of claim 20, The operation mode includes a first mode having a large storage capacity and a second mode having a small storage capacity, The means capable of changing the number of levels of the multivalued data sets the number of multivalued data levels in the first mode to be higher than the multivalued data levels in the second mode IC memory card. 20. The method of claim 19, A feature section for setting a storage capacity is formed in the IC memory card, Wherein the external device identifies a storage capacity according to a characteristic portion of the IC memory card, The means for changing the storage capacity may change the storage capacity in accordance with a signal from the external device IC memory card. 20. The method of claim 19, Further comprising a counter for counting the number of repeated write / erase operations in at least one of the plurality of operation modes. The memory device according to claim 23, wherein the means for changing the number of levels of the multi-valued data includes means for changing the number of levels of the multi-valued data so that when the counter exceeds the number of rewrite assurance times repeated in the corresponding mode, To a lower set value. 25. The IC memory card according to claim 24, further comprising means for informing that the change has been made to the outside when the number of levels of multi-valued data is changed to a low set value so that the maximum storage capacity is reduced. 1. An IC memory card capable of recording / reproducing data with an external device, A memory array region in which a plurality of memory cell transistors capable of storing multi-valued data having a binary value or a triple or more value are arranged; and a control means for changing the number of levels of multi-value data to be stored in at least a part of the memory array region, Volatile semiconductor memory device having means for storing data by changing Lt; / RTI > The means for storing data by changing the number of levels of the multi-valued data and changing the storage capacity is characterized in that when the storage capacity for the parts of the storage area is changed, the block which is the write / IC memory card. The IC memory card according to claim 26, wherein said nonvolatile semiconductor memory device performs writing and reading of data in page units. 28. The method of claim 27, wherein when a number of levels of the multivalued data is high and a plurality of columns to be accessed are set to a low level of the multivalued data, Gt; IC < / RTI > 27. The IC memory card of claim 26, further comprising a counter for counting the number of repeated write / erase operations in at least one of the plurality of operation modes. The memory device according to claim 29, wherein the means for changing the number of levels of the multilevel data includes means for changing the number of levels of the multilevel data so that when the counter exceeds the number of rewrite assurance times repeated in the mode, To a lower set value. The IC memory card according to claim 30, further comprising means for notifying the outside that such change has occurred when the number of levels of the multivalued data is changed to a lower set value so that the maximum storage capacity is reduced.