JP4916504B2 - Data storage system - Google Patents

Description

This invention relates to data storage systems, and more particularly, to a structure using an electrically writing / erasable nonvolatile semiconductor memory cell.

  Non-volatile semiconductor memory (flash memory) that can be electrically written and erased is widely used as an alternative to EPROM and mask ROM as a program code storage memory, taking advantage of the fact that it can be rewritten on the substrate. did.

  In recent years, as semiconductor processing technology has been miniaturized, a large-capacity flash memory capable of storing image data and audio data has appeared, and its application to digital still cameras and portable audio is rapidly progressing.

  However, the flash memory is required to have a larger capacity in order to enable recording of moving image data.

  As an important technology for realizing a larger capacity of the flash memory, there is a multi-value technology in addition to the miniaturization of the semiconductor processing technology. A flash memory generally stores data by changing a threshold value of a memory cell by applying a high electric field to a floating gate insulated from the surroundings by an insulating film and injecting or discharging electric charges.

  In the case of a normal flash memory (binary flash memory), the high threshold value of the memory is “1” (or “0”), and the low threshold value of the memory cell is “0” (or “1”). ).

  In the case of a flash memory using a multi-value technology (multi-value flash memory), the threshold value of the memory cell is set to a plurality of states of 3 or more. For example, in a flash memory capable of storing four values, the threshold value of the memory cell is set to four states, and “11” (the lowest threshold state), “10”, “00”, Correspond to “01” (the state with the highest threshold). Thereby, 2-bit data can be stored in one memory cell. Needless to say, the correspondence between the physical state of the memory cell and the logical data can be arbitrarily determined as in the binary flash memory.

  By the way, when realizing a multi-value flash memory, if “1” (or “0”) is stored in a memory cell and the data is read after being left for a long time, it becomes “0” (or “1”). There is an important problem of becoming.

  This problem is physically caused by electrons injected into the floating gate being emitted to the semiconductor substrate or gate through the energy barrier to the insulating film or by being injected from the semiconductor substrate or gate. This happens because the threshold of changes.

  Referring to FIG. 44, in the case of a binary flash memory, for example, the threshold value in the “1” state is set to 1 V to 1.7 V, the threshold value in the “0” state is set to 4.3 V or more, and determination at the time of reading is performed. The threshold is 3V. In this case, there is a read margin of 1.3 V in both the “1” state and the “0” state. In this case, erroneous reading occurs when electrons corresponding to 1.3 V are injected / released.

  On the other hand, in the case of a multi-level flash memory, for example, the threshold value in the “11” state is 1 V to 1.7 V, the threshold value in the “10” state is 2.3 V to 2.7 V, and the “00” state is The threshold value is set to 3.3 V to 3.7 V, and the threshold value in the “01” state is set to 4.3 V or more. If the determination threshold value at the time of reading is 2V, 3V, and 4V, the reading margin in each state is only 0.3V. Therefore, when electrons corresponding to 0.3 V are injected / released, erroneous reading occurs.

  When the memory cell having the Vgs-Ids characteristic represented by F1 in FIG. 44 is brought into the same state as the memory cell having the Vgs-Ids characteristic represented by F2 due to the emission of electrons from the floating gate, the multi-value is obtained. In the flash memory, the written data “01” is erroneously read as “00”.

  Similarly, when the memory cell having the Vgs-Ids characteristic represented by F3 is in the same state as the memory cell having the Vgs-Ids characteristic represented by F4, in the multilevel flash memory, “11” written is written. Is erroneously read as “10”.

  On the other hand, in the binary flash memory, even when the memory cell in the F1 state is in the F2 state or the memory cell in the F3 state is in the F4 state, data is read correctly. .

  As described above, the multilevel flash memory and the binary flash memory have data retention characteristics that are physically equivalent to each other, but the data reliability of the binary flash memory is superior to that of the multilevel flash memory. Yes. In terms of data transfer speed, the binary flash memory is superior. On the other hand, as described above, the multilevel flash memory is superior in terms of cost and capacity increase. Therefore, in the future, it will be required to develop devices that effectively utilize all these characteristics.

The present invention has been made to solve such problems, and its object is to realize a large capacity of memory, and the reliability of the data, to enable high speed operation provides to Lud over data storage system There is to do.

A data storage system according to one aspect of the present invention includes a plurality of first nonvolatile semiconductor memories having a first characteristic, and at least one second nonvolatile semiconductor memory having a second characteristic different from the first characteristic. An area and a controller for exchanging data with the outside and writing data in the memory area and reading data from the memory area are provided . In the first state in which at least one of the plurality of first non-volatile semiconductor memories can receive a command from the control device, the control device is based on stored data for writing to the memory area received from the outside. , it is determined whether writing which matches the second characteristic or write that match the first characteristic is the first case that is required is a case where the second being requested, if it is the first case the determined when writing data stored in the first nonvolatile semiconductor memory, when it is determined that the case of the second viewing write data stored in the second nonvolatile semiconductor memory, a plurality of first nonvolatile semiconductor memory in the second state is impossible to receive commands from all the control device, the write-free stored data when the second non-volatile semiconductor memory is capable receiving a command to the second nonvolatile semiconductor memory.

  Preferably, the first characteristic is a characteristic capable of storing data with predetermined reliability and operating at a predetermined processing speed, and is relatively higher than the first characteristic. It is a characteristic that can store data with reliability and can operate at a higher speed than the first characteristic.

  Preferably, the first nonvolatile semiconductor memory includes a plurality of multi-value data memory cells each storing data of 2 bits or more, and the second nonvolatile semiconductor memory includes a plurality of data each storing 1-bit data. Memory cells.

Preferably, the control device, within a certain period of time, further comprising a measuring circuit for measuring the magnitude of the stored data received from the outside, based on the measurement result of the measurement circuit, when the magnitude of the stored data is equal to or smaller than the reference value Is determined to be the first case, the stored data is written to the first nonvolatile semiconductor memory, and when the size of the stored data exceeds the reference value, the second case is determined to be the second case. write non-stored data in the memory.

Preferably, the control device transfers data already written in the second nonvolatile semiconductor memory in the second state to the first nonvolatile semiconductor memory in response to the absence of data exchange with the outside.

Preferably, the control device determines that it is the second case when the stored data is management data for managing the memory area, and writes the management data to the second nonvolatile semiconductor memory.

Preferably, the control device further includes an error correction circuit for adding an error detection code to the data, and when the stored data is written to the first nonvolatile semiconductor memory, the error detection code is added to the stored data for writing. When writing stored data to the second nonvolatile semiconductor memory, writing is performed without adding an error detection code to the stored data.

One by that data storage system to an aspect of the invention, it is possible to store data in a nonvolatile semiconductor memory having the appropriate characteristics according to at least two comprise, store data having different non-volatile semiconductor memory characteristics from each other . In particular, a first nonvolatile semiconductor memory capable of storing data with a predetermined reliability and operating at a predetermined processing speed, and storing data with a relatively higher reliability than the first nonvolatile semiconductor memory. it can either Tsu by using the second non-volatile semiconductor memory capable of operating at a higher speed than the first characteristic, a large capacity, it is possible to perform a reliable and high-speed data processing.

Preferably , a second nonvolatile semiconductor memory that stores binary data and a first nonvolatile semiconductor memory that stores multi-value data can be used.

Preferably, within a certain time period, by providing a measuring circuit for measuring the magnitude of the stored data received from external, write at high speed is required when the size of the store data exceeds the standard values Therefore, the stored data can be written in the nonvolatile semiconductor memory corresponding to binary data.

Preferably , the binary data written in the non-volatile semiconductor memory corresponding to binary data is converted into multi-value data in the non-volatile semiconductor memory corresponding to multi-value data in response to the absence of data exchange with the outside. It can be memorized.

Preferably , management data for managing the memory area is stored as binary data in a nonvolatile semiconductor memory corresponding to binary data. As a result, the probability of erroneous reading of the management data is reduced, so that the possibility of causing a fatal error in the system is reduced.

Preferably , error correction processing is not executed for binary data. Thereby, high-speed data processing is realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
A flash memory 1000 according to the first embodiment of the present invention will be described. The first embodiment of the present invention relates to a flash memory capable of mixing an area for storing multi-value data and an area for storing binary data.

  Referring to FIG. 1, flash memory 1000 is output from a plurality of pins for exchanging signals with the outside, input / output buffer 11 provided corresponding to the plurality of pins, and input / output buffer 11. An address decoder 12 for decoding an internal address signal, a command decoder 13 for decoding an internal control signal output from the input / output buffer 11 and issuing a command, and a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix With MA and MB.

  The plurality of pins are an R / B pin P1 that outputs a signal R / B indicating whether the memory is operating (Busy state) or is operable (Ready state), and data for inputting and outputting data It includes an input / output pin group P2 and a control pin group P3 that receives an external control signal for controlling internal operations. Control pin group P3 includes a / CE pin that receives a chip enable / CE signal.

  Memory cells included in memory cell arrays MA and MB can be set in a plurality of states, and store binary data or multi-value data (three or more values). In the following description, “01”, “00”, “10”, “11” will be used as an example of multi-value data. The correspondence shown in FIG. 44 is applied to the relationship between the multi-value data / binary data and the threshold value. In the first embodiment, when there is a write request for binary data “0”, the memory cell is brought into a state of multi-value data “01”.

  The flash memory 1000 further includes a control CPU 16 for controlling data writing, reading, erasing, and the like, and a verify circuit 17 for controlling a verify operation. The control CPU 16 includes a status register 18 that holds the internal status of the device. Information held in the status register 18 can be output to the outside.

  A command received from the outside controls whether data is stored in binary or multi-value in the memory cell. The command decoder 13 recognizes which of the binary write command / multi-value write command is input. The control CPU 16 performs control for writing data into the memory cell in accordance with a binary write sequence or a multi-value write sequence in accordance with the output of the command decoder 13.

  Reading / writing is performed in units of sectors (or pages) composed of memory cells connected to one word line.

  The flash memory 1000 further receives an output from the address decoder 12 to select the memory cell array MA in the row direction, and receives an output from the address decoder 12 to select the memory cell array MB in the row direction. Multi-level flag unit 15A provided for memory cell array MA, multi-level flag unit 15B provided for memory cell array MB, Y decoder / data latch that operates in accordance with the output of address decoder 12 and the output of control CPU 16 19 and 20, a Y decoder / sense latch 21 that operates according to the output of the address decoder 12 and the output of the control CPU 16, and a multi-value flag sense latch unit 22. The Y decoder performs selection in the column direction of the memory cell array.

  As will be described later, the multi-value flag sections 15A and 15B store values indicating whether binary data or multi-value data is stored in the memory cell. The control CPU 16 controls writing of data to the multi-value flag sections 15A and 15B ("0" for multi-value and "1" for 2-value) and reading of data from the multi-value flag sections 15A and 15B. The data of the multilevel flag portions 15A and 5B is read in the same procedure as the reading of data from the memory cell as will be described later.

  Referring to FIG. 2, memory cell array MA includes a plurality of nonvolatile memory cells M and word lines WL00 and WL01 arranged in the row direction. Memory cell array MB includes a plurality of nonvolatile memory cells M and word lines WL10 and WL11 arranged in the row direction. Bit lines BL1 and BL2 are arranged in common corresponding to the columns of memory cell arrays MA and MB.

  The control gate layer of the memory cell M is connected to the word line, the drain region is connected to the bit line, and the source region receives the source voltage VSL.

  X decoders 14A and 14B include a plurality of NAND circuits receiving a decode signal output from address decoder 12 and a plurality of inverters. The inverter V1a included in the X decoder 14A inverts the output of the NAND circuit N1a to drive the word line WL00, and the inverter V1b inverts the output of the NAND circuit N1b to drive the word line WL01. The inverter V1c included in the X decoder 14B inverts the output of the NAND circuit N1c to drive the word line WL10, and the inverter V1d inverts the output of the NAND circuit N1d to drive the word line WL11.

  Each of the multi-value flag units 15A and 15B includes a multi-value flag MF. The multi-value flag MF has the same structure as the memory cell M (nonvolatile memory cell). In the figure, four multi-value flags MF connected to word lines WL00, WL01, WL10 and WL11, respectively, are shown. The multi-level flag MF is arranged in units of sectors or pages. The multi-level flag MF is connected to the multi-level flag sense latch unit 22 by wiring (referred to as bit line BL0) arranged in the bit line direction. The multi-value flag MF stores a value indicating whether data is written in binary or multi-value in the memory cell M connected to the same word line.

  Y decoder / data latch 21 includes sense latch 3 # 1 provided corresponding to the bit line. Sense latch 3 # 1 includes inverter V2a and inverter V2b.

  Y decoder / data latch 19 includes data latch 1 arranged corresponding to the bit line. The data latch 1 includes an inverter V3a and an inverter V3b. Y decoder / data latch 20 includes data latch 2 arranged corresponding to the bit line. The data latch 2 includes an inverter V4a and an inverter V4b.

  Each of the drains of the memory cells connected to one word line is electrically connected to a different sense latch and data latch.

  During the read operation, a read voltage is applied to the word line, and it is determined whether or not a current flows through the memory cell via the sense latch. The data latches 1 and 2 are used for saving the read result. In the first embodiment of the present invention, data latches 1 and 2 are arranged to read a 2-bit signal from one memory cell. Data is output to the outside using the values of the data latches 1 and 2.

  In the write operation, first, data is input to data latches 1 and 2, and then a value is set in sense latch 3 # 1, thereby changing the threshold value of the memory cell.

  Multi-level flag sense latch unit 22 includes a sense latch 3 # 2 formed of inverters V5a and V5b. Sense latches 3 # 1 and 3 # 2 are collectively referred to as sense latch 3.

  A signal processing circuit 25 is disposed between each latch (data latch, sense latch) and the bit line.

  As shown in FIG. 3, the signal processing circuit 25 includes NMOS transistors T1, T2, and T3. In FIG. 3, the latch L indicates either a data latch or a sense latch.

  The transistor T1 is arranged between the bit line and the input / output node Z1 of the latch L. Transistor T2 is connected between nodes Z2 and Z3, and has a gate connected to node Z1. Transistor T3 is connected between node Z3 and the bit line.

  The signal processing circuit 25 performs selective precharge processing / selective discharge processing / sense processing. The control CPU 16 gives signals to the node Z2, the gate of the transistor T1, and the gate of the transistor T3 in accordance with the processing.

  In the selective precharge process, as shown in FIG. 4A, an L level signal is applied to the gate of the transistor T1, an H level signal is applied to the node Z2, and an H level signal is applied to the gate of the transistor T3. If the value latched in the latch L is “1”, the bit line is held at “H” by the transistors T 2 and T 3, and if it is “0”, the bit line keeps the voltage level as it is.

  In the selective discharge process, as shown in FIG. 4B, an L level signal is applied to the gate of the transistor T1, an L level signal is applied to the node Z2, and an H level signal is applied to the gate of the transistor T3. If the value latched in the latch L is “1”, the bit line is held at “L”, and if “0”, the bit line holds the voltage level as it is.

  Further, in the sense processing, as shown in FIG. 4C, an H level signal is applied to the gate of the transistor T1, an H or L level signal is applied to the node Z2, and an L level signal is applied to the gate of the transistor T3. To do. The latch L becomes “1” or “0” depending on the potential of the bit line.

  The data transfer process from latch to latch shown below is realized by performing a selective precharge process based on the transfer source latch and performing a sense process in the transfer destination latch.

  An outline of writing / reading / erasing of the flash memory 1000 will be described with reference to FIGS. Memory cell M includes a source region 6 formed on a substrate 10 and a drain region 7 connected to a bit line, a floating gate layer 8, and a control gate layer 9 connected to a word line.

  At the time of data writing, as shown in FIG. 27A, a positive high voltage (for example, 18 V) is applied to control gate layer 9 through the word line for the memory cell to be written. To do. At this time, the corresponding sense latch is set to “0” (0 V), and 0 V is applied to the drain region 7. Note that the source region 6 is in an open state.

  As shown in FIG. 27B, for a memory cell that is not a write target, the corresponding sense latch is set to “1” (6 V) and 6 V is applied to the drain region 7.

  At the time of batch erasing of data, a negative high voltage (for example, −16 V) is applied to the control gate layer 9 as shown in FIG. At this time, 0 V is applied to the source region 6 and the drain region 7. The threshold value of the memory cell becomes the lowest state (corresponding to multi-value data “11” and binary data “1”).

  When data is read, a positive voltage (for example, 3 V) is applied to control gate layer 9 and 0 V is applied to source region 6 and drain region 7 through a word line, as shown in FIG. Then, it is determined using a sense latch whether or not a current flows through the memory cell.

  Next, details of the data reading sequence in the flash memory 1000 will be described in comparison with a multi-value flash memory that stores only multi-value data.

  In the multilevel flash memory, the read sequence shown in FIGS. 5 to 7 is executed. Note that multi-value data (“01”, “00”, “10” or “11”) is read using the data latches 1 and 2 and the sense latch 3 as in the present application.

  Referring to FIG. 5, three read operations (READ1, READ2, and READ3) are executed. In READ1, the word line voltage is set to 3.0V, in READ2, the word line voltage is set to 4.0V, and in READ3, the word line voltage is set to 2.0V.

  In READ 1 (see FIG. 6A), data is read from the memory cell array, and the read data (“1”, “1”, “0”, “0”) is latched by the sense latch 3. Next, data is transferred from the sense latch 3 to the data latch 2 (transfer processing).

  In READ 2 (see FIG. 6B), data is read from the memory cell array, and the read data (“1”, “0”, “0”, “0”) is latched by the sense latch 3. Next, data is transferred from the sense latch 3 to the data latch 1 (transfer processing).

  In READ 3 (see FIG. 6C), data is read from the memory cell array, and the read data (“1”, “1”, “1”, “0”) is latched by the sense latch 3.

  Next, arithmetic processing is performed (see FIG. 7A). In the arithmetic processing, data is transferred from the sense latch 3 to the data latch 1 (transfer processing), and data is transferred from the data latch 1 to the sense latch 3 (transfer inversion processing). As a result, XOR processing of the data in the sense latch 3 and the data in the data latch 1 is performed.

  Next, an output process is performed (FIG. 7B). Specifically, data is transferred from the sense latch 3 to the data latch 1 (transfer process). Then, the data in data latch 2 (“0”, “0”, “1”, “1”) and the data in data latch 1 (“0”, “1”, “1”, “0”) are inverted. Output the data. As a result, multi-value data (“01”, “00”, “10”, “11”) is read out.

  The relationship between the data (value of the data latch after three readings) and the value latched in the sense latch 3 by each operation is as shown in FIG.

  On the other hand, the flash memory 1000 executes the multi-value data reading sequence shown in FIGS. First, the control CPU 16 reads the data of the multi-value flag MF in the first read operation (READ1), and determines whether or not the second and third read operations are performed based on this value. If the data of the multilevel flag MF is “0”, that is, indicates that multilevel data is stored in the memory cell M of the same sector (or the same page), the second and third read operations READ2 and READ3 are executed. To do. In READ1, the word line voltage is set to 3.0V, in READ2, the word line voltage is set to 4.0V, and in READ3, the word line voltage is set to 2.0V.

  In READ1 (see FIG. 10A), data of the memory cell M of the memory cell array MA and the multilevel flag MF corresponding to the memory cell M are read. The data (“1”, “1”, “0”, “0”) of the memory cell M is latched by the sense latch 3 # 1, and the data (“0”) of the multilevel flag MF is latched by the sense latch 3 # 2. .

  Since the data of the multi-value flag MF is “0”, the control CPU 16 executes a multi-value data read sequence. Inverted data of memory cell M is transferred from sense latch 3 # 1 to data latch 2 (transfer process).

  In READ2 (see FIG. 10B), data is read from the memory cell M. Data (“1”, “0”, “0”, “0”) of the memory cell M is latched by the sense latch 3 # 1. Data in memory cell M is transferred from sense latch 3 # 1 to data latch 1 (transfer process).

  In READ3 (see FIG. 10C), data is read from the memory cell M. Data (“1”, “1”, “1”, “0”) of memory cell M is latched by sense latch 3 # 1.

  Next, arithmetic processing is performed (see FIG. 11A). In the arithmetic processing, selective precharge processing is performed on the bit lines of the memory cell array MA based on the sense latch 3 # 1, and selective discharge processing is performed based on the data latch 1. Thus, XOR processing of data in data latch 1 and data in sense latch 3 # 1 is performed.

  Next, an output process is performed (see FIG. 11B). Specifically, the data latch 1 performs a sensing process. Data corresponding to the potential of the bit line of the memory cell array MA is latched in the data latch 1 (“0”, “1”, “1”, “0”). Then, data (“0”, “0”, “1”, “1”) in the data latch 2 and data obtained by inverting the data in the data latch 1 are output. As a result, multi-value data (“01”, “00”, “10”, “11”) is read out.

  The relationship between the data (value of the data latch after three read operations) and the value latched in the sense latch 3 by each operation is as shown in FIG.

  At the time of reading binary data, the flash memory 1000 executes the binary data reading sequence shown in FIGS. If the data of the multi-value flag MF read in the first read operation (READ1) is “1”, the control CPU 16 ends the read operation in READ1 as shown in FIG.

  In READ1 (see FIG. 14A), data of the memory cell M of the memory cell array MA and the multilevel flag MF corresponding to the memory cell M are read. The data (“1”, “1”, “0”, “0”) of the memory cell M is latched by the sense latch 3 # 1, and the data (“1”) of the multilevel flag MF is latched by the sense latch 3 # 2. .

  Since the data of the multilevel flag MF is “1”, the control CPU 16 performs control so as to execute a binary data read sequence. Data is transferred from sense latch 3 # 1 to data latch 2 (transfer process). The inverted data of the read data is latched in the data latch 2.

  Next, an output process is performed (see FIG. 14B). Specifically, data (“0”, “0”, “1”, “1”) of the data latch 2 is output. As a result, binary data (“0”, “0”, “1”, “1”) is read out.

  Note that the relationship between the data (value of the data latch after one read operation) and the value latched in the sense latch 3 in one read operation is as shown in FIG. In this way, the read operation can be completed once based on the value of the multilevel flag.

  Next, a data write sequence to the flash memory 1000 will be described in comparison with a multi-value flash memory that stores only multi-value data.

  In the multilevel flash memory, the write sequence shown in FIGS. 16 to 19 is executed. It is assumed that multi-value data (“01”, “00”, “10” or “11”) is written using data latches 1 and 2 and sense latch 3 # 1 as in the present application.

  Referring to FIG. 16, three write operations (PROGRAM1, PROGRAM2, and PROGRAM3) are executed. In PROGRAM1, the word line voltage is set to 18V, in PROGRAM2, the word line voltage is set to 17V, and in PROGRAM3, the word line voltage is set to 16V.

  Data “01” is written in PROGRAM1, data “00” is written in PROGRAM2, and data “10” is written in PROGRAM3.

  The processing of PROGRAM 1 is as shown in FIGS. Referring to FIG. 17A, data latch 1 has the first bit data (“1”, “0”, “0”, “1”), and data latch 2 has the second bit data (“0”). ”,“ 0 ”,“ 1 ”,“ 1 ”). Data is transferred from the data latch 1 to the sense latch 3 (transfer processing).

  Referring to FIG. 17B, all the bit lines between data latch 2 and sense latch 3 are precharged (“1”). Referring to FIG. 17C, selective discharge processing is performed based on data latch 2 and selective discharge processing is performed based on sense latch 3 for the bit line.

  Next, referring to FIG. 17D, the sense latch 3 performs a sensing process. Data corresponding to the potential of the bit line (“1”, “0”, “0”, “0”) and inverted data are latched in the sense latch 3. Data “01” is written into the memory cell M connected to the sense latch that latched “0”.

  The processing of PROGRAM2 is as shown in FIGS. Referring to FIG. 18A, data is transferred from data latch 1 to sense latch 3 (transfer processing). Referring to FIG. 18B, a selective precharge process is performed on the bit line between data latch 2 and sense latch 3 based on sense latch 3. Referring to FIG. 18C, a selective discharge process is performed on the bit line based on data latch 2. Referring to FIG. 18D, sense processing is performed by sense latch 3. Data corresponding to the potential of the bit line (“0”, “1”, “0”, “0”) and inverted data are latched in the sense latch 3. Data “00” is written into the memory cell M connected to the sense latch that latched “0”.

  The processing of PROGRAM 3 is as shown in FIGS. Referring to FIG. 19A, data is transferred from data latch 1 to sense latch 3 (transfer processing). Referring to FIG. 19B, all bit lines between sense latch 3 and data latch 1 are precharged (“1”). Referring to FIG. 19C, the selected discharge process is performed based on sense latch 3 and the selected discharge process is performed based on data latch 1 for the bit line.

  Next, referring to FIG. 19D, the sense latch 3 performs a sensing process. Data corresponding to the potential of the bit line (“0”, “0”, “1”, “0”) and inverted data are latched in the sense latch 3. Data “10” is written into the memory cell M connected to the sense latch that latched “0”.

  The relationship between the data (value of the data latch after data loading) and the value latched in the sense latch 3 in each operation is as shown in FIG.

  On the other hand, flash memory 1000 executes the write sequence shown in FIGS. 21 to 23 when writing multi-value data.

  Referring to FIG. 21, three write operations (PROGRAM1, PROGRAM2, and PROGRAM3) are executed. In PROGRAM1, the word line voltage is set to 18V, in PROGRAM2, the word line voltage is set to 17V, and in PROGRAM3, the word line voltage is set to 16V.

  The processing of PROGRAM1 is as shown in FIGS. 22 (A) to (D). Referring to FIG. 22A, data latch 1 has the first bit data (“1”, “0”, “0”, “1”), and data latch 2 has the second bit data (“0”). ”,“ 0 ”,“ 1 ”,“ 1 ”). Data is transferred from data latch 1 to sense latch 3 # 1 (transfer process).

  At the same time, “0” is written to the memory cell array MA side of the sense latch 3 # 2 in order to write “0” to the multi-value flag MF on the memory cell array MA side.

  Referring to FIG. 22B, all the bit lines of memory cell array MB are precharged (“1”). Referring to FIG. 22C, selective discharge processing is performed on the bit lines of memory cell array MB based on data latch 2, and selective discharge processing is performed on sense latch 3 # 1.

  Referring to FIG. 22D, sense processing is performed in sense latch 3 # 1. Data corresponding to the potential of the bit line (“1”, “0”, “0”, “0”) and inverted data are latched in sense latch 3 # 1. Data “01” is written into the memory cell M connected to the sense latch that latched “0”.

  The processing contents of PROGRAM2 and 3 are the same as the processing of PROGRAM2 and 3 in the multi-level flash memory described above. Thereby, data “00” and “10” are written.

  The relationship between the data (value of the data latch after data loading) and the value latched in the sense latch 3 in each write operation is as shown in FIG.

  Thus, when writing multi-value data, the write data is latched in the data latch. When the multi-value data “01” is written, the corresponding sense latch is set to “0”, and the sense latch of the memory cell corresponding to the multi-value data other than “01” is set to “1”. Similarly, when writing multi-value data “00”, the corresponding sense latch is set to “0”, and the sense latch of the memory cell corresponding to multi-value data other than “00” is set to “1”. Further, when multi-value data “10” is written, the corresponding sense latch is set to “0”, and the sense latch of the memory cell corresponding to multi-value data other than “10” is set to “1”. At this time, a value indicating multi-value data is stored in the multi-value flag.

  Further, the flash memory 1000 executes the writing sequence shown in FIGS. 24 to 25 when binary data is written.

  Referring to FIG. 24, one write operation (PROGRAM1) is executed. In PROGRAM1, the word line voltage is set to 18V.

  The processing of PROGRAM 1 is as shown in FIGS. Referring to FIG. 25A, write data (“0”, “0”, “1”, “1”) is stored in data latch 2. At the same time, in order to write “1” into the multi-value flag MF on the memory cell array MA side, “1” is stored on the memory cell array MA side of the sense latch 3 # 2. Then, all the bit lines of the memory cell array MB are precharged (“1”).

  Referring to FIG. 25B, selective discharge processing is performed on the bit lines of memory cell array MB based on data latch 2. Referring to FIG. 25C, sense processing is performed in sense latch 3 # 1. Data corresponding to the potential of the bit line (“1”, “1”, “0”, “0”) and inverted data are latched in sense latch 3 # 1. As a result, data “0” (corresponding to data “01”) is written into the memory cell M connected to the sense latch that latched “0”.

  The relationship between the data (value of the data latch after data loading) and the value latched in the sense latch 3 by one write operation is as shown in FIG.

  As described above, when there is a binary write request, the write operation can be terminated when the data “01” is written.

  Thus, according to the flash memory 1000 according to the first embodiment of the present invention, multi-value data and binary data can be mixed and stored. Therefore, in response to a write request, for example, data requiring high reliability can be stored in binary, and large capacity data can be stored in multiple values. Further, multi-value data can be read as multi-value data, and binary data can be read as binary data.

[Embodiment 2]
In the second embodiment of the present invention, an improved example of the flash memory 1000 will be described. The control CPU 16 according to the second embodiment of the present invention controls to read out binary data three times as in the case of multivalued data when reading out binary data. If the read data value differs between the first read operation and the third read operation, more specifically, the threshold values correspond to multi-value data “10” and “00”. If so, a warning is generated indicating that the threshold value of the binary stored data has changed.

  When a warning occurs, the control CPU 16 performs control for rewriting binary data.

  A binary data read sequence in the flash memory according to the second embodiment of the present invention will be described with reference to FIGS.

  In Embodiment 2 of the present invention, as shown in FIG. 28, a total of three read operations (READ1, READ2, and READ3) are executed. In READ1, the word line voltage is set to 3.0V, in READ2, the word line voltage is set to 4.0V, and in READ3, the word line voltage is set to 2.0V.

  The memory cell into which binary data has been written is in a state of multi-value data “01” (“0P”), a state of multi-value data “00” (“0E”), a state of multi-value data “11” (“1P ”) Or the state of multi-value data“ 10 ”(“ 1E ”). The control CPU 16 detects the states of “0E” and “1E” and generates a warning.

  In READ1 (see FIG. 29A), the data of the memory cell M of the memory cell array MA and the multilevel flag MF corresponding to the memory cell M are read and latched by the sense latch. Data (“1”, “1”, “0”, “0”) corresponding to the memory cell M (“0P”, “0E”, “1E”, “1P”) is stored in the sense latch 3 # 1. On the memory cell array MA side of sense latch 3 # 2, data ("1") of multilevel flag MF is stored. Data is transferred from sense latch 3 # 1 to data latch 2 (transfer process).

  In READ2 (see FIG. 29B), data is read from the memory cell M. The read data (“1”, “0”, “0”, “0”) is latched by the sense latch 3 # 1. Data is transferred from sense latch 3 # 1 to data latch 1 (transfer process).

  In READ3 (see FIG. 29C), data is read from the memory cell M. The read data (“1”, “1”, “1”, “0”) is latched by the sense latch 3 # 1.

  Next, arithmetic processing is performed (see FIG. 29D). In the arithmetic processing, selective precharge processing is performed on the bit lines of the memory cell array MA based on the sense latch 3 # 1, and selective discharge processing is performed based on the data latch 1. Thus, XOR processing of data in data latch 1 and data in sense latch 3 # 1 is performed.

  Next, an output process is performed (see FIG. 29E). Specifically, the data latch 1 performs a sensing process. Data corresponding to the potential of the bit line of the memory cell array MA is latched in the data latch 1 (“0”, “1”, “1”, “0”).

  The relationship between the data (value of the data latch after the three read operations) and the value latched in the sense latch 3 # 1 by each operation is as shown in FIG.

  When the read data is binary data (multi-value flag MF is “1”), the control CPU 16 further performs 00 level detection processing and 10 level detection processing.

  In the 00 level detection process, as the first process (see FIG. 30A), all the bit lines of the memory cell array MA are precharged. In the second process (see FIG. 30B), a selective discharge process is performed on the bit lines of memory cell array MA based on data latch 1, and a sense process is performed by sense latch 3 # 1.

  In the third process (see FIG. 30C), a selective precharge process is performed on the bit lines of the memory cell array MB based on the sense latch 3 # 1, and a selective discharge process is performed on the data latch 2. Further, as the fourth process (see FIG. 30D), the sense latch 3 # 1 performs the sense process. Data corresponding to the potential of the bit line of memory cell array MB is latched in sense latch 3 # 1 (“0”, “1”, “0”, “0”).

  The sense latch corresponding to the memory cell in the “0E” state stores a value different from that of the sense latch corresponding to another memory cell. Using the latched value, ALL determination processing is performed by all the latch determination circuits 200 shown in FIG. When the fourth process of the 00 level detection process ends, a 10 level detection process is performed.

  In the first process of the 10-level detection process (see FIG. 31A), data is transferred from the data latch 1 to the sense latch 3 # 1 (transfer process). In the subsequent second process (see FIG. 31B), the selective discharge process is performed on the bit lines of the memory cell array MB based on the sense latch 3 # 1, and the selective precharge process is performed on the data latch 2.

  In the subsequent third process (see FIG. 31C), the sense latch 3 # 1 performs the sense process. Data corresponding to the potential of the bit line of memory cell array MB is latched in sense latch 3 # 1 (“0”, “0”, “1”, “0”).

  The sense latch corresponding to the memory cell in the “1E” state stores a value different from that of the sense latch corresponding to the other memory cell. Using the latched value, ALL determination processing is performed by all the latch determination circuits 200 shown in FIG.

  As shown in FIG. 33, all latch determination circuit 200 that performs the ALL determination processing includes a plurality of NMOS transistors T10, T11, T12,... And a node receiving power supply voltage, and inverters V20 and V21 for inverting the signal on signal line L.

  Transistors T10, T11, T12,... Are provided corresponding to each of the plurality of sense latches 3 # 1. Each of transistors T10, T11, T12,... Is turned on / off according to the output of the corresponding sense latch 3 # 1.

  If the outputs of all sense latches 3 # 1 are at "L" level, the determination value output from inverter V21 is at "H" level.

  Therefore, in the case shown in FIGS. 30 and 31, since the H level signal is output from one sense latch 3 # 1, the determination value becomes "L" level. Based on this determination value, the control CPU 16 writes binary data again to correct the threshold shift, and generates a warning signal indicating the threshold shift. The warning signal is output to the outside via the status register 18, for example.

  Thus, according to the flash memory according to the second embodiment of the present invention, binary data can be accurately stored. In addition, when the deviation of the binary data is detected, the occurrence of the deviation can be notified to the outside.

[Embodiment 3]
In the third embodiment of the present invention, an improved example of the flash memory 1000 is shown. In the first embodiment described above, when there is a write request for binary data “0”, the memory cell is set to the state of multi-value data “01”, that is, the threshold value is the highest.

  On the other hand, when there is a write request for binary data “0”, the control CPU 16 according to the third embodiment of the present invention sets the memory cell to the multivalue closest to the state of the multivalue data “11”. A state of data “10” is set (see FIG. 43).

  Since the threshold shift amount is smaller than in the case of writing to “01”, the writing time can be shortened. As a result, the flash memory according to the third embodiment of the present invention realizes a high-speed write operation.

[Embodiment 4]
A data storage system 4000 according to Embodiment 4 of the present invention will be described with reference to FIG. As shown in FIG. 34, the data storage system 4000 includes a binary flash memory 102, multilevel flash memories 104A and 104B, and a system controller 400 including a counter / timer 401, a buffer 402, a controller 403, and an error correction circuit 404. Is provided.

  The binary flash memory 102 includes a plurality of nonvolatile memory cells. Binary data is written into a memory cell included in the binary flash memory 102, and binary data is read from the memory cell.

  Each of multi-level flash memories 104A and 104B includes a plurality of nonvolatile memory cells. Multi-value data is written in the memory cells included in each of the multi-value flash memories 104A and 104B, and multi-value data is read from the memory cells.

  Each of the binary flash memory 102 and the multi-level flash memories 104A and 104B inputs and outputs data from the I / O pins. The I / O pin is connected to the buffer 402.

  The binary flash memory 102 outputs a signal R / B0 indicating whether or not it is operating from the R / B pin. Each of the multi-value flash memories 104A and 104B outputs signals R / B1 and R / B2 indicating whether or not they are operating from the R / B pin. The signals R / B0, R / B1, and R / B2 are input to the controller 403.

  Each of the binary flash memory 102 and the multi-level flash memories 104A and 104B operates by receiving a chip enable signal output from the controller 403 at the / OE pin.

  The counter / timer 401 measures the size of write data requested from the host system 4100 within a certain period. The measurement result of the counter / timer 401 is output to the controller 403.

  Buffer 402 captures data transferred from host system 4100 and captures data read from flash memory.

  Based on the control of the controller 403, the error correction circuit 404 adds an error correction detection signal to the write data taken in the buffer 402, and is taken into the buffer 402 when the read data is transferred to the host system 4100. Error correction processing is performed on the received data.

  The controller 403 monitors the output of the counter / timer 401 and signals R / B0, R / B1, and R / B2, and controls the writing of data to the fresh memory. It also controls whether or not error correction is performed when reading data.

  As shown in FIG. 35, software for driving the data storage system 4000, FAT information (file information indicating the correspondence between flash memory addresses and addresses in the data storage system 4000), and user data at the time of high-speed write request Is written in the flash memory 102 capable of relatively high reliability and high speed operation. Other user data is written into the multi-level flash memories 104A and 104B.

  A first example of writing control to the flash memory by the system controller 400 will be described in comparison with a data storage system in which only a plurality of multi-value flash memories are arranged.

  When only the multi-level flash memory is used, writing is performed according to the procedure shown in FIG. It is assumed that the data storage system is equipped with N multi-value flash memories. Device numbers 1 to N are assigned to each of the N multilevel flash memories. When there is a write request from the host system (step S401), a device number (DEVICE NO) designated as a write target is initialized to “0” (step S401).

  Subsequently, the device number is incremented by “1” (step S402). It is determined whether writing is possible (Ready state) or writing is not possible (Busy state) in accordance with the signal R / B of the corresponding multi-level flash memory (Step S403).

  If it is writable (Ready state), the data received from the host system is written into the multilevel flash memory corresponding to the device number (step S404). Then, the next write request from the host system is accepted (step S400).

  If writing is not possible (Busy state), it is determined whether or not the device number has reached the maximum value “N” (step S405). If the device number is smaller than N, the process proceeds to a process of incrementing the device number by “1” (step S402). If the device number is “N”, the process proceeds to processing for initializing the device number to “0” (step S401). In this way, data is sequentially written into a writable flash memory among a plurality of mounted multi-value flash memories.

  On the other hand, according to the data storage system 4000, writing is executed according to the procedure shown in FIG. It is assumed that the data storage system 4000 is equipped with N multi-value flash memories and one binary flash memory. Device numbers 1 to N are assigned to each of the N multilevel flash memories, and a device number (N + 1) is assigned to the binary flash memory.

  When there is a write request from the host system 4100 (step S410), the device number to be written is initialized to “0” (step S411). Subsequently, the device number is incremented by “1” (step S412). It is determined whether writing is possible (Ready state) or writing is impossible (Busy state) in accordance with the signal R / B of the corresponding multilevel flash memory (Step S413).

  If it is writable (ReadY state), data is written into the flash memory corresponding to the device number (step S414). Then, the next write request from the host system 4100 is accepted (step S410).

  If writing is not possible (Busy state), it is determined whether or not the device number has reached the maximum value “N + 1” (step S415). If the device number is smaller than “N + 1”, the process proceeds to a process of incrementing the device number by “1” (step S412).

  When the device number is “N + 1”, the process proceeds to processing for determining whether the corresponding flash memory (binary flash memory) is in the Ready state or the Busy state (step S413).

  That is, the system controller 400 monitors the state (R / B) of the flash memory and controls to write data from the multi-value flash memory in the Ready state. Then, when all the multi-level flash memories are in the Busy state, control is performed so that data is written to the binary flash memory. With this operation, a large amount of data can be stored in the data storage system 4000.

  A second example of writing control to the flash memory by the system controller 400 will be described with reference to FIG. Referring to FIG. 38, it is determined whether or not there is a write request from host system 4100 (step S420). If there is a write request, the process proceeds to a write control process (step S421) based on the data size described later.

  If there is no write request, it is determined whether or not the user data at the time of the high-speed write request is written in the binary flash memory 102 (step S422). If there is no user data at the time of the high-speed write request in the binary flash memory 102, the processing is not performed (step S423). When the user data at the time of the high-speed write request is written in the binary flash memory 102, the data in the binary flash memory 102 is transferred to the buffer 402 (step S424).

  The data is written to the multi-value flash memory via the buffer 402 (step S425). Then, the process proceeds to processing for determining the next write request of the host system 4100 (step S420).

  That is, when there is no write request from the host system 4100, the user data at the time of the high-speed write request written in the binary flash memory 102 is transferred to the multi-level flash memory. Thereby, both high-speed writing and large capacity can be achieved.

  The write control process (step S421) based on the size of the write data will be described with reference to FIG. When there is a write request from the host system 4100 (step S430), based on the output of the counter / timer 401, it is determined whether or not there is write data of a certain time (reference value). If the size of the write data is within the reference value, the device number to be written is initialized to “0” (step S432). Subsequently, the device number is incremented by “1” (step S433), and the process proceeds to processing for determining the ready / busy state of the corresponding flash memory (step S435).

  If the size of the write data is greater than or equal to the reference value, the device number is set to “N + 1” (step S434), and the process proceeds to processing for determining the ready / busy state of the corresponding binary flash memory (step S435).

  If the corresponding flash memory is in the Ready state, data is written to the flash memory (step S436). Then, the next write request from the host system 4100 is accepted (step S430).

  If the corresponding flash memory is in the Busy state, it is determined whether or not the device number has reached the maximum value “N + 1” (step S437). If the device number is smaller than “N + 1”, the process proceeds to a process of incrementing the device number by “1” (step S433).

  If the device number is “N + 1”, the process proceeds to processing for determining whether the corresponding flash memory (binary flash memory) is in the Ready state or the Busy state (step S435).

  That is, the system controller 400 determines that high-speed data writing is requested when the data is large, and writes the data to the binary flash memory capable of high-speed operation.

  Next, an example of flash memory read control by the system controller 400 will be described with reference to FIG. When there is a read request from the host system 4100 (step S450), the corresponding data stored in the flash memory is transferred to the buffer 402 (step S451).

  It is determined whether the data transferred to the buffer 402 is multilevel data read from the multilevel flash memory (step S452).

  If the data is read from the binary flash memory, the error correction process in the error correction circuit 404 is not performed, and the process proceeds to a process of transferring data from the buffer 402 to the host system 4100 (step S456).

  When the data is read from the multilevel flash memory, the data transferred to the buffer 402 is sent to the error correction circuit 404 (step S453). Error correction processing is performed in the error correction circuit 404 (step S454). The data after error correction is stored in the buffer 402 (step S455). Then, the process proceeds to a process of transferring data from the buffer 402 to the host system 4100 (step S456).

  That is, no error correction code is added when writing to the binary flash memory, and an error correction code is added when writing to the multilevel flash memory. In response to a data read request from the host system 4100, when data is read from the high-reliability binary flash memory, error correction is not performed, and when data is read from the multi-value flash memory, an error occurs. Control is performed so that data is transferred to the host system 4100 after correction. As a result, high-speed operation can be realized.

[Embodiment 5]
A data storage system 5000 according to the fifth embodiment of the present invention will be described with reference to FIG. Data storage system 5000 includes multi-value / binary flash memories 100A, 100B and 100C, and system controller 400, as shown in FIG. The multi-value / binary flash memories 100A to 100C have the configuration described in the first, second, or third embodiment, and can store binary data or multi-value data in a memory cell.

  In the case of the configuration according to the fifth embodiment, as shown in FIG. 42, the user data is written to the flash memories 100A and 100B as multi-value data, and the user data at the time of the high-speed write request is written as binary data. In addition, the user data is multi-value data, user data at the time of a high-speed write request, software for driving the data storage system, and FAT information (file information indicating correspondence between the address of the flash memory and the address in the data storage system 5000) ) Can be written as binary data.

  The system controller 400 controls whether to store multiple values or binary values depending on the type of write data received from the host system 4100. The system controller 400 can also control whether or not to perform error correction according to the type of data.

  Further, when there is no write request, when the user data (binary data) at the time of the high-speed write request is written in the flash memory, the data is transferred to the buffer 402, and the multi-value is transmitted via the buffer 402. It is also possible to store the data in this state.

  In the case of the fourth embodiment, although there are many unused areas remaining in the binary flash memory 102, there are no unused areas in the multilevel flash memory, or many unused areas remain in the multilevel flash memory. In spite of this, there may be no unused area in the binary flash memory 102.

  Therefore, in the fifth embodiment of the present invention, a flash memory is provided in which multi-value data / binary data can be written and the written multi-value data / value data can be read. This makes it possible to perform a highly reliable and high-speed operation while effectively using the memory space.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

1 is a block diagram showing an outline of an overall configuration of a flash memory 1000 according to Embodiment 1 of the present invention. FIG. 2 is a circuit diagram showing a configuration of a main part of a flash memory 1000. FIG. 3 is a circuit diagram for explaining a configuration of a signal processing circuit 25. FIG. (A)-(C) is a figure which shows the state of the signal in a selection precharge process, a selection discharge process, and a sense process. It is a figure which shows the word line voltage at the time of read-out operation | movement of a multilevel flash memory. (A)-(C) is a figure which shows the reading sequence (READ1-READ3) in a multi-value flash memory. (A) and (B) are diagrams showing a read sequence in the multi-level flash memory. It is a figure which shows the relationship between the data at the time of read-out operation | movement of a multilevel flash memory, and the value of a sense latch. FIG. 5 is a diagram showing a word line voltage during a multi-value data read operation of the flash memory 1000. (A) to (C) are diagrams showing a multi-value data read sequence (READ1 to READ3) in the flash memory 1000. FIG. (A) and (B) are diagrams showing a multi-value data read sequence in the flash memory 1000. FIG. FIG. 6 is a diagram showing a relationship between data and a sense latch value during a multi-value data read operation of flash memory 1000. FIG. 5 is a diagram showing a word line voltage during binary data read operation of the flash memory 1000. (A) And (B) is a figure for demonstrating the reading sequence of the binary data in the flash memory 1000. FIG. FIG. 3 is a diagram showing a relationship between data and a sense latch value during binary data read operation of flash memory 1000. It is a figure which shows the word line voltage at the time of write-in operation | movement of a multi-value flash memory. (A)-(D) is a figure for demonstrating the write sequence (PROGRAM1) in a multi-value flash memory. (A)-(D) is a figure for demonstrating the write sequence (PROGRAM2) in a multi-value flash memory. (A)-(D) is a figure for demonstrating the write sequence (PROGRAM3) in a multi-value flash memory. It is a figure which shows the relationship between the data and the value of a sense latch at the time of write-in operation | movement of a multilevel flash memory. FIG. 5 is a diagram showing a word line voltage during a multi-value data write operation of the flash memory 1000. (A)-(D) is a figure which shows the write sequence (PROGRAM1) of the multi-value data in the flash memory 1000. FIG. 6 is a diagram showing a relationship between data and a value of a sense latch during a multi-value data write operation of flash memory 1000. FIG. FIG. 5 is a diagram showing a word line voltage during binary data write operation of the flash memory 1000. (A)-(C) is a figure which shows the write-in sequence (PROGRAM1) of the binary data in the flash memory 1000. FIG. 6 is a diagram showing a relationship between data and a value of a sense latch during binary data write operation of flash memory 1000. FIG. (A)-(D) is a figure for demonstrating the voltage relationship at the time of writing / erasing / reading of the flash memory 1000. FIG. It is a figure which shows the word line voltage at the time of the binary data read of the flash memory by Embodiment 2 of this invention. (A)-(E) are figures which show the reading sequence of the binary data in the flash memory by Embodiment 2 of this invention. (A)-(D) are the figures which show the content of the 00 level detection process in Embodiment 2 of this invention. (A)-(C) are the figures which show the content of the 10 level detection process in Embodiment 2 of this invention. It is a figure which shows the relationship between the data at the time of binary data read-out operation | movement, and the value of a sense latch. 2 is a circuit diagram showing a configuration of an all latch determination circuit 200. FIG. It is a figure for demonstrating the data storage system 4000 by Embodiment 4 of this invention. 6 is a diagram illustrating an example of data arrangement on an address space in the data storage system 4000. FIG. It is a flowchart which shows the write-in control in the data storage system which has arrange | positioned only multiple multi-value flash memories. 12 is a flowchart showing first write control in the data storage system 4000. 10 is a flowchart showing second write control in data storage system 4000. 10 is a flowchart showing a write control process according to the size of write data in the data storage system 4000. 10 is a flowchart showing read control in the data storage system 4000. It is a figure for demonstrating the data storage system 5000 by Embodiment 5 of this invention. 6 is a diagram showing an example of data arrangement on an address space in the data storage system 5000. FIG. It is a figure which shows the relationship between multi-value data and binary data. It is a figure which shows the relationship between multi-value data and binary data in a non-volatile memory cell.

Explanation of symbols

  1, 2 Data latch, 3 # 1, 3 # 2 Sense latch, 11 Input / output buffer, 12 Address decoder, 13 Command decoder, 14A, 14B X decoder, 15A, 15B Multi-level flag section, 16 Control CPU, 17 Verify Circuit, 18 status register, 19, 20 Y decoder / data latch, 21 Y decoder / sense latch, 22 multi-level flag sense latch unit, 25 signal processing unit, 100A to 100C multi-level / binary flash memory, 102 binary flash Memory, 104A, 104B Multi-level flash memory, 400 system controller, 401 counter / timer, 402 buffer, 403 controller, 404 error correction circuit, 1000 flash memory, 4000 data storage system, 4100 host Stem, MA, MB memory cell array, M memory cells, MF multivalued flag.

Claims (7)

A memory region including a plurality of first nonvolatile semiconductor memories having a first characteristic and at least one second nonvolatile semiconductor memory having a second characteristic different from the first characteristic;
A controller for exchanging data with the outside and writing data in the memory area and reading data from the memory area;
The controller is
In a first state where at least one of the plurality of first non-volatile semiconductor memories can receive a command from the control device , based on stored data for writing to the memory area received from the outside , it is determined whether the write that matches the second characteristic or write is the first case that is being requested match the first characteristic is the case where the second being requested, the first case when it is determined that it is the unwritten said stored data in said second nonvolatile semiconductor memory when it is determined that the write data stored, the second case the first non-volatile semiconductor memory,
In a second state in which all of the plurality of first nonvolatile semiconductor memories cannot receive a command from the control device, the second nonvolatile semiconductor memory can receive the command when the second nonvolatile semiconductor memory can receive the command. writing the stored data in the nonvolatile semiconductor memory free, the data storage system. The first characteristic is
It is a characteristic that can store data with a predetermined reliability and operate at a predetermined processing speed,
The second characteristic is
The data storage system according to claim 1, wherein the data storage system is a characteristic that can store data with higher reliability than the first characteristic and can operate at a higher speed than the first characteristic. The first nonvolatile semiconductor memory is
A plurality of multi-value data memory cells each storing two or more bits of data;
The second nonvolatile semiconductor memory is
The data storage system of claim 2, comprising a plurality of memory cells each storing one bit of data. The controller is
A measurement circuit for measuring the size of stored data received from the outside within a predetermined period;
Based on the measurement result of the measurement circuit, when the size of the stored data is less than or equal to a reference value, it is determined that it is the first case, and the stored data is written to the first nonvolatile semiconductor memory, said storage data writing free on the second non-volatile semiconductor memory when the size of the stored data exceeds the reference value it is determined that the case of the second data storage system of claim 2. The controller is
The data already written in the second nonvolatile semiconductor memory in the second state is transferred to the first nonvolatile semiconductor memory in response to the absence of data exchange with the outside. The data storage system described. The controller is
3. The management data for managing the memory area is determined to be the second case when the stored data is management data for managing the memory area, and the management data is written to the second nonvolatile semiconductor memory. Data storage system. The controller is
An error correction circuit for adding an error detection code to the data ;
When writing the stored data to the first nonvolatile semiconductor memory, the error detection code is added to the stored data and writing is performed, and when the stored data is written to the second nonvolatile semiconductor memory The data storage system according to claim 2, wherein writing is performed without adding the error detection code to the stored data.

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