KR19990061052A - Cell repair control circuit of semiconductor memory device - Google Patents

Abstract

The present invention is to provide a cell repair control circuit of a semiconductor memory device to accurately control the block to be a cell repair to prevent unnecessary cell repair.

To this end, the present invention provides a cell array block for repairing a word line driver for repairing a word line to be repaired, having an input means for inputting a low repair control signal from a low repair control circuit and a plurality of inverters and transistors connected to the input means. And a plurality of row repair control means, wherein the row repair control means comprises: a first fuse provided on an input path of the row repair control signal in a semiconductor memory device configured to commonly use an adjacent cell array block and a fuse box; And a second fuse provided between the input path and the ground terminal, and disconnecting only one of the first fuse and the second fuse when one cell array block is repaired between the adjacent cell array blocks. By repairing the cells of the block, it is possible to repair unnecessary cells during cell repair. It is able to.

Description

Cell repair control circuit of semiconductor memory device

The present invention relates to a cell repair control circuit of a semiconductor memory device, and more particularly, to a cell repair control circuit of a semiconductor memory device configured to prevent unnecessary cell repair occurring during cell repair in a semiconductor memory device.

In general, when any one of a large number of fine cells constituting a DRAM occurs, the DRAM may not function properly. Therefore, in this case, a redundancy scheme is adopted in which the yield rate is increased by replacing defective cells by using spare memory cells installed in the DRAM in advance.

In particular, in such a redundancy method, redundancy cells of memory are installed for each sub-array block, and in case of 16 mega DRAM, spare rows and columns are pre-installed for every 256K cell array, causing a failure due to failure. The memory cell is replaced by a spare memory cell (i.e., a redundancy cell) on a row / column basis.

For example, a conventional row repair device for repairing a word line has a row decoder installed at one end of an array of cells, and a fuse box for row repair next to the row decoder. A low repair control means having a low repair control circuit is provided, and a repair word line driver is provided between the low repair control means and the cell array block.

The conventional repair word line driver is connected in parallel with an inverter IV1 for inverting an nrd signal provided from a low repair control circuit (not shown) and an output terminal of the inverter IV1, as shown in FIG. The inverters are provided through a plurality of inverters IV2, IV4, IV6, and IV8 inverting signals from the inverter IV1 and transfer transistors T1, T2, T3, and T4 which are controlled by the control signal wlxfr. A plurality of transistors T5, T7, T9, and T11 for applying word line boosting signals px0 to px3 to the repair word lines rwl0 to rwl3 according to signals from (IV2, IV4, IV6, IV8); A plurality of transistors which make the potential of the repair word lines rwl0 to rwl3 the ground potential by the signals from the inverters IV3, IV5, IV7, and IV9 which invert the signals of the inverters IV2, IV4, IV6, and IV8. T6, T8, T10, and T12).

According to the conventional repair word line driver configured as described above, when the address fuse (not shown) to be repaired is disconnected, the nrd signal is enabled at a high level.

As a result, a high level signal is output at the output terminals of the inverters IV2, IV4, IV6, and IV8, and a low level signal is output at the output terminals of the inverters IV3, IV5, IV7, and IV9. At this time, as the transfer transistors T1, T2, T3, and T4 are turned on by the control signal wlxfr, the transistors T5, T7, T9, and T11 may receive signals from the inverters IV2, IV4, IV6, and IV8. The high-level signal is turned on to drive the repair word lines rwl0, rwl1, rwl2, and rwl3 to repair four cells.

Referring to the arrangement state of a cell array block employing a conventional repair word line driver for performing such an operation, as shown in FIG. 2, two repair word line drivers WL DRV0, for each cell array block CA1 to CA16 are shown. Row repair control means F1-F16 provided with WL DRV1, a fuse box (not shown), and a row repair control circuit (not shown) are provided.

The row repair control means F1 to F16 use the adjacent cell array block and the fuse box (not shown) in common.

For example, the upper two repair word line drivers WL DRV0 of the cell array block CA1 and the cell array block CA5 share a fuse box of the row repair control means F5, and the cell array block CA The two repair word line drivers WL DRV1 below CA1) and the cell array block CA5 use a fuse box of the row repair control means F1 in common.

Therefore, if the addresses to be repaired are 0 and 1, the cells corresponding to 0 at the top and 1 at the bottom are repaired, and repair is possible even if there are two or more addresses to be repaired per cell.

However, even when the portion to be repaired is limited to the cell array block CA1, a problem arises in which both the cell array block CA1 and the cell array block CA5 are repaired.

That is, since a cell in which the repair of the cell array block CA5 is unnecessary is also repaired, in this case, if there is an abnormality in the repair cell, this die cannot be used.

Accordingly, an object of the present invention is to provide a cell repair control circuit of a semiconductor memory device configured to prevent a cell from being repaired by accurately controlling a block to be a cell repair.

In order to achieve the above object, the cell repair control circuit of a semiconductor memory device according to the present invention comprises an input means for inputting a low repair control signal from a low repair control circuit, and a plurality of inverters and transistors connected to the input means. A plurality of repair word line drivers for repairing a word line to be repaired are provided between the cell array block and the row repair control means, and the row repair control means for a semiconductor memory device in which adjacent cell array blocks and a fuse box are commonly used. ,

And further comprising a first fuse provided on an input path of the row repair control signal and a second fuse provided between the input path and a ground terminal, so as to repair one cell array block between the adjacent cell array blocks. The cell of the cell array block may be repaired by breaking only one fuse of the first fuse and the second fuse.

1 is an internal circuit diagram of a conventional repair word line driver;

FIG. 2 is a layout view of a cell array block employing a repair word line driver shown in FIG. 1;

3 is a cell repair control circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

Explanation of symbols for main parts of the drawings

f1: first fuse f2: second fuse

CA1 to CA16: Cell array block

F1 to F16: Low repair control means

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a cell repair control circuit diagram of a semiconductor memory device according to an embodiment of the present invention. The same reference numerals will be given to the same parts as those described in FIG. 1, and description thereof will be omitted.

FIG. 1 differs from FIG. 1 in that a first fuse f1 is additionally provided between the nrd signal input terminal and the first inverter IV1 in each repair word line driver provided in each of the two cell array blocks. The difference is that a second fuse f2 is additionally installed between the input terminal of the first inverter IV1 and the ground terminal.

Next, the operation of the cell repair control circuit of the semiconductor memory device according to the embodiment of the present invention configured as described above will be described.

In an exemplary embodiment of the present invention, a cell array block CA1 and a cell array block CA5 connected adjacent thereto will be described as an example.

If only the cell array block CA1 needs to be repaired among the two cell array blocks, the repair word line driver on the side of the cell array block CA1 cuts the second fuse f2 so that the repair word lines rwl0 to rwl3 appear. On the other hand, in the repair word line driver toward the cell array block CA5, the first word f1 is cut off so that the repair word lines rwl0 to rwl3 do not float.

Therefore, only four cells on the cell array block CA1 side are repaired, and the cells on the cell array block CA5 side are not repaired.

The same operation is performed in the other cell array block and the cell array block adjacent thereto.

According to the present invention as described above, it is possible to prevent unnecessary cell repair by using a fuse during cell repair.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (1)

An input means for inputting a low repair control signal from the low repair control circuit and a repair word line driver having a plurality of inverters and transistors connected to the input means for repairing a word line to be repaired is provided between the cell array block and the low repair control means. In the semiconductor memory device, a plurality of row repair control means is installed in common to the adjacent cell array block and the fuse box, A first fuse provided on an input path of the row repair control signal; Further comprising a second fuse provided between the input path and the ground terminal, The cell repair control circuit of a semiconductor memory device, wherein when repairing one cell array block between adjacent cell array blocks, only one of the first fuse and the second fuse is disconnected to repair a cell of the corresponding cell array block.