KR19990060871A - Power Reset Circuit for Semiconductor Memory Devices - Google Patents

Abstract

The present invention relates to a power reset circuit for a semiconductor memory device.

The conventional power reset circuit has a problem in that the power reset signal is output only by the power supply voltage regardless of the chip enable (CE) signal, and excessive standby current is consumed.

The present invention outputs the first power reset signal by the power supply voltage in the initial state, and outputs the first power reset disconnection signal when the transition from the low state to the high state and feeds it back to block the current path and the power supply voltage to reset the power. When the power supply voltage transitions from the high state to the low state, the second power reset signal and the second power reset blocking signal are output in accordance with the CE signal to minimize the current loss.

Description

Power Reset Circuit for Semiconductor Memory Devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power reset circuit for a semiconductor memory device, and more particularly to a power reset circuit for reducing a standby current.

FIG. 1 is a conventional power reset circuit diagram for a semiconductor memory device. The operation when the power supply voltage Vcc transitions from a low state to a high state will be described below.

When the power supply voltage is supplied and transitions from the low state to the high state, the second node K2 becomes high by the fourth PMOS transistor P4 serving as a capacitor. The high state signal resets the chip connected to the output terminal by outputting the high signal delayed for a predetermined time through the first, second, third and fourth inverters I1, I2, I3 and I4.

In this state, the potential of the first node K1 transitions to the high state by the power supply voltage input through the first PMOS transistor P1 and the second PMOS transistor P2. Since the second, third, and fourth NMOS transistors N2, N3, and N4 are turned on by the first node K1 in a high state, a power supply voltage input through the third PMOS transistor P3 is bypassed to ground. The second node K2, which has been kept high, goes low. Since the signal in the low state is output in the low state through the first, second, third and fourth inverters I1, I2, I3, and I4, the reset operation is stopped.

The power reset circuit driven in this way is driven independently of the chip enable (CE) signal, causing the standby current to flow excessively to about 20-30 mA, increasing overall current consumption.

Accordingly, an object of the present invention is to provide a power reset circuit for a semiconductor memory device that can reduce current consumption as much as possible.

The present invention for achieving the above object is to output a first power reset signal by the power supply voltage in the initial state when a power supply voltage is applied, and the first power reset when the power supply voltage transitions from a low state to a high state A first power reset signal generator for outputting a cutoff signal and feeding back the first power reset cutoff signal to cut off a current path and a power supply voltage to maintain the first power reset cutoff signal; A second power reset signal generator for outputting a second power reset signal and a second power reset cutoff signal according to a chip enable signal when the state transitions to a low state; an output signal of the first power reset signal generator and the second signal; And logical combining means for logically combining the output signals of the power reset signal generator.

1 is a circuit diagram of a conventional power reset circuit for a semiconductor memory device.

2 is a circuit diagram of a power reset circuit for a semiconductor memory device according to the present invention.

3 is a graph of current over time that flows when a chip is initialized using a power reset circuit for a conventional semiconductor memory device.

4 is a graph of current over time flowing when a chip is initialized using a power reset circuit for a semiconductor memory device according to the present invention.

Explanation of symbols for the main parts of the drawings

A: first power reset signal generator

B: second power reset signal generator

P1 to P4: first to fourth PMOS transistors

P11 to P16: first to sixth PMOS transistors

N1 to N4: first to fourth NMOS transistors

N11 to N23: first to thirteenth NMOS transistors

I1 to I4: first to fourth inverters

I11 to I21: first to eleventh inverters

K1 and K2: first and second node

K11 to K14: first to fourth nodes

NOR: NOR gate

The present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a power reset circuit for a semiconductor memory device according to the present invention.

First, an operation of the first power reset signal generator A will be described.

In the initial state in which the power supply voltage is applied, the second NMOS transistor N12 and the third PMOS transistor P13 are turned on so that the first node K11 is turned low. The third, fourth and fifth NMOS transistors N13, N14, and N15 are turned off by the first node K11 in the low state, and the second node K12 is turned high. The sixth NMOS transistor N16 of the inverter means is turned on by the second node K12 in the high state to form a path to the ground, so that the output of the inverter means becomes low. The low state signal is output to the NOR gate through the first inverter I11 in the high state, the low state through the second inverter I12, and through the third inverter I13 to the NOR gate.

When the power supply voltage transitions from the low state to the high state, the first node K11 becomes high by the power supply voltages input through the first PMOS transistor P11 and the second PMOS transistor P12. The third, fourth and fifth NMOS transistors N13, N14, and N15 are turned on by the first node K11 in the high state to form a path to the ground, and thus the second node K12 is brought low. The fifth PMOS transistor P15 of the inverter means is turned on by the second node K12 in the low state so that the output of the inverter means becomes high. The high state signal is inputted to the NOR gate in a low state through the first inverter I11, in a high state through the second inverter I12, and in a low state through the third inverter I13.

The low state signal passing through the first inverter I11 goes high through the fourth inverter I14, goes low through the fifth inverter I15, and goes high through the sixth inverter I16. The third PMOS transistor P13 is turned off by the signal transitioned to the high state via the sixth inverter I16, and is turned to the low state via the seventh inverter I17 to turn the second NMOS transistor N12. It is turned off to maintain the high and low states of the first node K11 and the second node K12 while blocking the current path. Therefore, the reset driving is stopped because a low state signal is output to the output terminal.

On the other hand, the first block A driven in this manner may reset the chip connected to the output terminal in the initial state and may block the current path and the power supply voltage so as to stop the reset driving when the power supply voltage transitions to the high state. When the voltage transitions to the low state, the first node K11 and the second node K12 maintain a low state and output a low state signal, thereby preventing the chip from being reset.

The operation of the second power reset signal generation unit B will now be described.

The operation when the power supply voltage transitions to the high state and the CE signal is applied to the low state is as follows.

Since the CE signal is applied in the low state, the eleventh NMOS transistor N21 is turned off, becomes high through the ninth inverter I19, and the sixth PMOS transistor P16 is turned off, and the thirteenth NMOS transistor N23 ) Is turned on. As a result, the third node K13 becomes high, the twelfth NMOS transistor N22 is turned on, and the fourth node K14 remains low, thereby outputting a low state signal.

The operation when the power supply voltage transitions to the high state and the CE signal is applied to the high state is as follows.

The CE signal is applied in the high state to turn on the eleventh NMOS transistor N21, and the low state is passed through the ninth inverter I19. The sixth PMOS transistor P16 is turned on by the low state signal, and the thirteenth NMOS transistor N23 is turned off. In this state, when the power supply voltage transitions to a high state, a path is formed to the ground by the eleventh NMOS transistor N21 input and turned on through the ninth NMOS transistor N19 and the tenth NMOS transistor N20, and thus, the third Node K13 goes low. The twelfth NMOS transistor N22 is turned off by the third node K13 in the low state. The power supply voltage is applied through the turned-on sixth PMOS transistor P16 to bring the fourth node K14 high. Since the fourth node K14 is in a high state, the fourth node K14 is in a low state through the tenth inverter I20 and is in a high state through the eleventh inverter I21 and input to the NOR gate.

In addition, the operation when the power supply voltage transitions to the low state and the chip is disabled, that is, when the CE signal remains low will be described.

Since the CE signal is applied in the low state, the eleventh NMOS transistor N21 is turned off, becomes high through the ninth inverter I19, and the sixth PMOS transistor P16 is turned off, and the thirteenth NMOS transistor N23 ) Is turned on. As a result, since the third node K13 maintains a low state and the fourth node K14 maintains a low state, the third node K13 outputs a low state signal.

On the other hand, the operation when the power supply voltage transitions to a low state and the chip is enabled (that is, when the CE signal remains high) will be described.

The CE signal is applied in the high state to turn on the eleventh NMOS transistor N21, and the low state is passed through the ninth inverter I19. The sixth PMOS transistor P16 is turned on by the low state signal, and the thirteenth NMOS transistor N23 is turned off. In this state, when the power supply voltage transitions to the low state, a path is formed to the ground by the eleventh NMOS transistor N21 input and turned on through the ninth NMOS transistor N19 and the tenth NMOS transistor N20, and thus, the third Node K13 goes low. The twelfth NMOS transistor N22 is turned off by the third node K13 in the low state. The power supply voltage is applied through the turned-on sixth PMOS transistor P16 to bring the fourth node K14 high. Since the fourth node K14 is in a high state, the fourth node K14 is in a low state through the tenth inverter I20 and is in a high state through the eleventh inverter I21 and input to the NOR gate.

That is, the second power reset signal generation unit B outputs the reset signal in the high state only when the CE signal is applied in the high state.

When the power supply voltage transitions to a high state by such a circuit operation, the chip is reset while reducing current consumption by feedback of the internal signal of the first power reset signal generator A without being affected by the CE signal. When the power supply voltage transitions to a low state, the chip is initialized by the second power reset signal generator B driven by the CE signal.

The current of the second power reset signal generator B is cut off when the chip is deactivated, and the standby current of the first power reset signal generator A and the second power reset signal generator B is about 0.8 to 0.9 mA. Can be reduced.

3 is a graph illustrating a current flowing when a chip is reset using a power reset circuit for a conventional semiconductor memory device, and FIG. 4 is used to reset the chip using a power reset circuit for a semiconductor memory device according to the present invention. When the current flowing in the graph is shown. As shown, the standby current flows about 16 mA when using the conventional power reset circuit, and the standby current flows about 0.8 mA when using the power reset circuit according to the present invention.

As described above, according to the present invention, when the power supply voltage transitions to the high state, the first power reset signal generator is operated, and when the power supply voltage transitions to the low state, the second power reset signal generator is operated, and these are transferred to the OR gate. Combination can reduce current consumption during initialization.

Claims (3)

Outputting a first power reset signal by the power supply voltage in an initial state where a power supply voltage is applied; outputting the first power reset blocking signal when the power supply voltage transitions from a low state to a high state; A first power reset signal generator for holding the first power reset blocking signal by feeding back a reset blocking signal to cut off a current path and a power supply voltage; A second power reset signal generator configured to output a second power reset signal and a second power reset stop signal according to a chip enable signal when the power supply voltage transitions from a high state to a low state; And logic combining means for logically combining the output signal of the first power reset signal generator and the output signal of the second power reset signal generator. 2. The apparatus of claim 1, wherein the first power reset signal generator comprises: first signal adjusting means for adjusting an output signal according to a power supply voltage; Second signal adjusting means for outputting a first power reset signal or a first power reset blocking signal in accordance with an output signal of the first signal adjusting means; First switching means for controlling a current path of the first signal adjusting means according to the first power reset blocking signal; And second switching means for controlling said power supply voltage input to said second signal adjusting means in accordance with said first power reset blocking signal. 2. The apparatus of claim 1, wherein the second power reset signal generator comprises first signal adjusting means for adjusting an output signal according to a power supply voltage; Second signal adjusting means for outputting a second power reset signal or a second power reset blocking signal in accordance with the output signal of the first signal adjusting means; First switching means for controlling a current path of the first signal adjusting means in accordance with a chip enable signal; Second switching means for controlling a power supply voltage input to the second signal adjusting means according to the chip enable signal; And third switching means for controlling the output of the second power reset signal in accordance with the chip enable signal.