KR19990058667A - Pattern Method of Next Generation Semiconductor Copper Wiring - Google Patents

Abstract

The present invention relates to a method of patterning a next-generation semiconductor copper wiring, and more particularly, in the method of patterning a next-generation semiconductor copper wiring, after depositing a copper thin film on a pattern on which a contact hole or a via hole is formed, 10 ^-1 The present invention relates to a patterning method for a next-generation semiconductor copper wiring for reflowing the copper thin film by supplying oxygen gas at 350 to 500 ° C. at 10 to 200 sccm in a vacuum atmosphere of less than torr, and performing heat treatment for 10 to 30 minutes. In the method of the present invention, a small amount of oxygen is added in a low temperature vacuum atmosphere to completely fill contact holes or via holes of one or more gigabytes of wiring by simple heat treatment.

Description

Pattern Method of Next Generation Semiconductor Copper Wiring

The present invention relates to a method of patterning a next-generation semiconductor copper wiring, and more particularly, a next-generation semiconductor capable of seamlessly patterning one or more gigabytes of next-generation semiconductor copper wiring using a reflow process of a copper thin film. The pattern method of the copper wiring for this invention is related.

Recent developments in semiconductor devices have increased the integration density by increasing the chip area and shrinking the existing circuits as a way to increase the degree of integration. As a result, the length of the metal wiring in the device increases and Increasing signal delay time due to the decrease of line width and thickness, and the increase of current density per unit area causes significant electrical reliability.

Until now, aluminum alloys have been used as wiring materials for highly integrated semiconductor devices.As the circuit becomes ultra-high density of more than 1 giga-class, aluminum alloys are caused due to the reduction of operation speed due to signal delay and the destruction of wiring due to electrical movement. There is a need for a next-generation wiring material that can replace.

On the other hand, copper has a lower specific resistance (1.67μΩ · ㎝) and excellent resistance to electrical movement compared to aluminum alloy, so that the operation speed and reliability of the device can be maintained even if the cross-sectional area of the metal thin film is reduced, and sputtering or metal The thin film can be manufactured by organic chemical vapor deposition, which will be used as a wiring material for ultra-high integrated circuits.

If a copper thin film is used as a next-generation wiring material to replace an aluminum alloy thin film, there are two types of patterning methods for processing the metal wiring. First, after depositing a copper thin film is a method of processing to have a desired pattern of wiring using a dry etching method. However, this method does not remove from the copper surface and remains as it is because the compounds formed by copper etching have a very low vapor pressure. Therefore, in order to remove the compounds produced by dry etching, the temperature of the substrate should be raised to 200 ° C. or higher. However, the conventional photoresist film may be deformed at 150 ° C. or higher, thus making it difficult to accurately control the critical dimension and burn out the photo film. Entails. Secondly, there is a method of forming a trench-shaped wiring pattern in advance, depositing a copper thin film, and filling it, and then removing the extra copper layer remaining on the surface by using a chemical mechanical polishing (CMP) process. This method uses chemical vapor deposition as a method of embedding copper in a trench pattern, but has a disadvantage in that it does not completely fill a contact hole or a via hole of 0.3 μm or less. That is, as can be seen in Fig. 1B, pores and the like are present, which results in poor electrical reliability. Therefore, a new pattern method for metal wiring after the deposition of a copper thin film to be used as the next-generation wiring material at 1 giga or more should be sought.

The present invention has been made to solve the above problems, by depositing a copper thin film as the next-generation semiconductor wiring material, and then heat-treated in a low-temperature oxygen atmosphere to reflow the copper thin film to perfect the contact hole or via hole of 1-gigabit wiring with copper After filling, the next generation semiconductor wiring pattern is formed by the CMP process.

Accordingly, an object of the present invention is to provide a method for patterning a next-generation semiconductor copper wiring that can seamlessly pattern a next-generation semiconductor copper wiring of one or more gigabytes using the above-described copper thin film reflow process.

The pattern method of the present invention for achieving the above object in the pattern method of the next-generation copper wiring pattern, after depositing a copper thin film on a substrate on which a contact hole or via hole is formed, 350 ~ in a vacuum atmosphere of 10 ^-1 torr or less Oxygen gas is supplied at 500 ° C. at 10 to 200 sccm, followed by heat treatment for 10 to 30 minutes to reflow the copper thin film.

FIG. 1 is a cross-sectional view of a pattern of a next-generation semiconductor copper wiring by a conventional method, and FIG. 1A shows a wiring line width (a) of 0.15 to 0.25 µm and an aspect ratio (b / a) of about 4 to 5. 1B is a cross-sectional view of a pattern hole after depositing a copper thin film, and FIG. 1C is a cross-sectional view of a pattern after a chemical mechanical polishing (CMP) process.

Figure 2 is a cross-sectional view of the pattern before and after embedding the copper thin film by the method of the present invention, Figure 2a is a cross-sectional photograph of the pattern after depositing the copper thin film, Figure 2b is a cross-sectional view of the pattern after reflowing the copper thin film It is a photograph.

FIG. 3 is a cross-sectional view of a pattern of a next-generation semiconductor wiring according to the present invention, and FIG. 3A shows a wiring line width (a) of 0.15 to 0.25 µm and an aspect ratio (b / a) of about 1 to about 1 giga class. 3B is a cross-sectional view of a pattern after depositing a copper thin film, FIG. 3C is a cross-sectional view of a pattern after reflowing a copper thin film, and FIG. 3D is a cross-sectional view of a pattern after a CMP process.

4 is a cross-sectional view of the pattern after the embedding by the copper reflow method according to the first embodiment of the present invention in a one-gigabit line & space pattern, Figure 4a is a cross-sectional view of a one-gigabit L / S pattern, Figure 4b It is a cross-sectional photograph of the pattern after reflowing a copper thin film at 400 degreeC, and FIG. 4C is a cross-sectional photograph of the pattern after reflowing a copper thin film at 450 degreeC.

※ Explanation of code for main part of drawing

1, 10: copper thin film 2, 20: pores

3, 30: contact hole 40: TiN diffusion barrier

50: Si oxide film

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

The reflow method of the copper thin film, which is the most important process in the next-generation semiconductor wiring pattern, may be achieved by heat treatment by adding a small amount of oxygen in a low temperature vacuum atmosphere. The conditions and principle of the process are as follows. Process conditions for reflowing copper thin film include heat treatment temperature up to 350 ~ 500 ℃, heat treatment pressure below 10 ^-1 torr, O ₂ partial pressure from 10 to 200 sccm, heat treatment time from 10 to 30 minutes, heating and cooling The atmosphere is in a hydrogen gas state and is not affected by the material of the substrate, the thickness of the copper thin film, and the conditions of the microstructure.

Under these conditions, only the surface of the copper thin film is oxidized to generate instantaneous high-temperature calorific value. Also, in the vacuum atmosphere, the surface diffusion of copper atoms is enhanced to increase the fluidity of the copper thin film to reduce the surface energy, thereby causing reflow. . In this process, care should be taken in order to reduce the surface oxidation of the copper thin film by adding a small amount of oxygen in a range of 10 to 200 sccm in a low temperature of 350 to 500 ° C. and a vacuum atmosphere of 10 ⁻¹ torr or less, and performing heat treatment within 10 to 30 minutes. shall. At this time, when the temperature exceeds 500 ° C. or the oxygen partial pressure exceeds 200 sccm, the reflowed surface oxide film of copper may not be formed to a uniform thickness and aggregate by copper peroxidation. When the above process is carried out, the surface oxide film of copper is less than 300Å thickness and the oxide layer oxidized on the surface can be removed by a CMP (Chemical Mechenical Polishing) process which is a subsequent process for forming a final pattern.

The pattern cross section after the contact hole 30 is embedded by the copper reflow method which concerns on this invention is shown in FIG. FIG. 2A is a cross-sectional view of the pattern after the copper thin film 10 is deposited, and FIG. 2B is a cross-sectional view showing the shape of completely filling the pattern after the reflow of the copper thin film 10. As can be seen in Figure 2, it can be seen that the contact hole 30 pattern can be completely filled with copper in a reflow process.

The most important property of the reflow process of the present invention is that the deeper the pattern, the preferentially the reflow of the copper thin film so that the contact hole or the via hole can be completely filled with copper. Such a copper reflow method of the present invention can be completely embedded in the copper pattern of the ultra-high density wiring of 1 or more gigabytes, and has advantages such as low cost and high yield by low temperature process and simple heat treatment.

The configuration of the process for the pattern method of the next-generation semiconductor copper wiring using the reflow method of the copper thin film of the present invention is schematically shown in FIG. FIG. 3A is a cross-sectional view of a contact hole required for a next-generation next-generation semiconductor device, and FIG. 3B is a cross-sectional view of a contact hole showing partial embedding of a copper thin film layer deposited by a chemical vapor deposition method or a sputtering method. As described above with reference to FIG. 1, in the one-gigabit wiring pattern, pores are necessarily present in the pattern by the current deposition technique, and the pores deteriorate electrical properties and thereby lower reliability. Therefore, in order to remove such pores, a copper thin film reflow method is required. Using the reflow method of the copper thin film of the present invention completely fills the wiring pattern as observed in FIG. 2. The cross section for this is shown in Fig. 3C. By introducing this process, the pattern of the next generation wiring material can be realized. Finally, as shown in FIG. 3D, the CMP process may be performed in a subsequent process to planarize the copper wiring and to remove the surface oxide layer of the copper thin film.

Therefore, it is possible to form a wiring pattern for the next-generation semiconductor wiring material to be used essentially in the ultra-high integration device of one or more gigabytes.

Hereinafter, the present invention will be described in more detail with reference to the following examples, but the scope of the present invention is not limited to the following examples.

Example 1

Line and space and hole patterns as shown in FIG. 4A were formed on the Si oxide film 50. First, SiO ₂ is deposited on the Si wafer by vapor phase chemical vapor deposition (CVD), and then a pattern is formed through a photolithography process, and Ti (500 Å) as a glue layer and TiN as a diffusion barrier are formed thereon by a sputtering method. (1500 Pa) was deposited. It was deposited on the patterned TiN / Ti / SiO ₂ / Si wafer in a CVD reactor maintained at a deposition temperature of 180 ° C. and 0.5 Torr by MOCVD (Metal Organic Chemical Vapor Deposition). The deposited copper thin film was heat-treated for 30 minutes at 400 ° C. and 450 ° C. heat treatment temperature, 50 sccm of oxygen gas, and a vacuum degree of 10 ⁻¹ to 10 ⁻³ Torr. The temperature increase rate was 8 ° C / min, the cooling rate was kept constant at about 4 ° C / min. The scanning electron microscope was used to observe the morphology of the cut surface and the copper surface of the L / S and hole patterns, and the results are shown in FIG. 4. 4 is a cross-sectional view of a pattern after embedding copper by the copper reflow method of the present invention in a 1-giga-line Line & Space pattern. Fig. 4A is a L / S pattern at 1 giga class, and shows a deep groove with a line width of 0.2 占 퐉 and an aspect ratio of 4. 4B and 4C are cross-sectional photographs showing that the 1 Giga-class pattern can be completely filled with copper at a low temperature of 400 ° C. and 450 ° C. by the copper reflow method according to the present invention. As can be seen from Figure 4, the method according to the present invention can completely fill the pattern of the next generation semiconductor of more than 1 gigabyte.

As described above, the reflow process of the copper thin film to be used for patterning the copper thin film to be used as the wiring material for next generation semiconductors of one or more gigabytes according to the method of the present invention has a high cost reduction and high yield by simple heat treatment, and a low temperature vacuum atmosphere. It is a general-purpose semiconductor process that can completely fill copper regardless of the deposition method, the type of diffusion barrier film, the thickness and microstructure of the copper thin film if the process conditions in which trace amount of oxygen is present are satisfied. In addition, the deeper the pattern of the metal wiring, the easier it is to completely fill the pattern has the advantage that can be heat-treated at a lower temperature. Therefore, since the copper thin film reflow process can be used to seamlessly pattern the next generation wiring material of 1G or more, it is considered that 1G will contribute greatly to the development of semiconductor devices of DRAM or more.

Claims (3)

In the method of patterning the next generation copper interconnection, after depositing a thin copper film on a substrate on which a contact hole or a via hole is formed, oxygen gas is supplied at 10 to 200 sccm at 350 to 500 ° C. in a vacuum atmosphere of 10 to ¹ torr or less. The patterning method of next-generation semiconductor copper wiring, characterized in that the copper thin film is reflowed by heat treatment for 10 to 30 minutes. The method of claim 1, wherein the method further comprises a chemical mechanical polishing (CMP) process after reflowing the copper thin film. The method of claim 1, wherein the deposition method of the copper thin film is a chemical vapor deposition method or a sputtering method.