KR19990058265A - Massive power switching element (IGBT) drive control circuit. - Google Patents

Abstract

The present invention relates to a drive control device of a switching circuit for switching a power supply in a power conversion device of a device using a high voltage in a railway vehicle, and the like, in particular, a large capacity IGBT for stably driving and controlling a high speed power switching device. It relates to a drive control circuit of.

In case of large capacity IGBT, a separate driving circuit is required for each configured IGBT. For stable switching control, gate drive voltage is determined, gate turn-on and turn-off. It is necessary to set the proper value of the resistor and to accurately design the overcurrent protection circuit and the low voltage detection circuit.

In view of the above, the present invention stabilizes the gate driving voltage, and recognizes when an overcurrent is detected in the gate or when the driving voltage drops to a low voltage, thereby blocking the driving voltage of the corresponding IGBT, thereby achieving stable switching of the IGBT. The purpose of the present invention is to propose a large capacity IGBT driving control circuit that can protect the IGBT from gate failure, power failure, and so on.

Description

Large capacity power supply switching element (IVT) drive control circuit.

The present invention relates to a drive control device of a switching circuit for switching a power supply in a power conversion device of a device using a high voltage in a railway vehicle, and the like, in particular, a large capacity IGBT for stably driving and controlling a high speed power switching device. It relates to a drive control circuit of.

In general, in a large-capacity power converter, as a switching element, one or more IGBTs are configured in series or in parallel according to the phase configuration (single phase and three phase) to perform power switching.

Such an IGBT is a voltage-driven switching element whose switching characteristics are determined by a voltage applied to a gate, and a large capacity power supply switching element in which several switching elements have a parallel connection structure.

Since the IGBT has a structure in which small-capacity devices are connected in parallel, a separate driving circuit is required for stable switching operation.

If the IGBT, which is a voltage-driven switching element, fails to establish an appropriate gate voltage (± 15V), a gate drive failure may occur due to a power supply abnormality (low voltage). If such a gate drive failure occurs, a stable power supply is provided to the device. This becomes difficult.

In addition, if the stable switching operation is not performed due to the gate driving failure and the control power failure as described above, an overcurrent flows, thereby causing a problem that the IGBT is broken.

Therefore, in order to drive the IGBT stably, the gate drive voltage is determined, the gate turn-on and turn-off resistance are appropriately set, and the overcurrent protection circuit and the low voltage detection circuit are correct. Design is necessary.

In view of the above, the present invention stabilizes the gate driving voltage, and recognizes when an overcurrent is detected in the gate or when the driving voltage drops to a low voltage, thereby blocking the driving voltage of the corresponding IGBT, thereby achieving stable switching of the IGBT. The purpose of the present invention is to propose a large capacity IGBT driving control circuit that can protect the IGBT from gate failure, power failure, and so on.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the configuration of a large capacity power supply switching element drive control circuit of the present invention.

2 is a circuit diagram showing an embodiment of the present invention.

The large-capacity power supply switching element driving control circuit according to the present invention includes an optical signal input means for receiving a gate pulse signal output from a power control logic and a gate for transmitting a gate pulse signal input from an optical signal input means. A pulse transmission means, a control means for outputting a switching control signal of an IGBT which is a power switching means in accordance with an applied gate pulse, an amplification means for amplifying a gate pulse signal and transferring it to a gate of an IGBT under control of the control means, An overcurrent sensing means for detecting an overcurrent by receiving a voltage applied to the collector terminal of the apparatus, a low voltage sensing means for detecting a low voltage by comparing a gate driving voltage with a reference voltage, and the overcurrent sensing means or a low voltage sensing means According to the result detected from the fault signal to the power control logic It consists of optical signal transmitting means for transmitting,

The control means stops the operation of the IGBT according to the result detected by the overcurrent detection means or the low voltage detection means, and monitors the detection result of the means every predetermined time to stop the operation of the IGBT until the cause of the error is resolved. It is characterized in that.

The power supply switching element driving control circuit of the present invention having such a configuration detects whether the gate driving voltage and the voltage flowing through the IGBT are compared with the reference voltage, and recognizes whether there is an overcurrent and a low voltage, thereby protecting the IGBT. To cut the driving voltage,

1 is a view illustrating an IGBT driving control circuit configured as a 2-channel in a power supply switching element driving control circuit of the present invention, and each of the IGBTs constitutes a separate driving control circuit. Since the configurations of the IGBT and the IGBT drive control unit 200 are the same, the following description will be given of the configuration by the same reference numerals.

IGBT and each of the IGBT is configured with an IGBT drive control unit 200, characterized in that the power supply unit 100 for supplying the control power of the IGBT drive control unit 200,

First, the power supply unit 100 is a pulse width modulation (PWM) to switch and output the control power supply unit 101 for supplying the driving control voltage of each IGBT and the power supplied from the control power supply unit 101. ) PWM control unit 102 for outputting a control signal to the power switching transformer 103 and rectifying and filtering the power output voltage converted through the power switching transformer 103 to drive each driving voltage for switching control of each IGBT, respectively. It is configured to include a rectifier and filter unit 104 to output to the IGBT drive control unit 200,

The IGBT driving controller 200 includes an optical signal input unit 1 for receiving a gate pulse signal transmitted from an optical signal output unit configured in a power supply control circuit, and a gate pulse transmitter 2 for transmitting the received gate pulse signal. And an amplifier 3 for driving an IGBT by amplifying the applied gate pulse signal to a gate of the IGBT, an overcurrent detector 4 detecting the collector voltage of the IGBT, and detecting whether an overcurrent is generated, and an IGBT. Control the switching operation of the IGBT according to a result detected by the low voltage detector 5 and the overcurrent detector 4 and the low voltage detector 5 that detect the presence of a low voltage at which the driving voltage of the voltage falls below a predetermined voltage. Under the control of the control unit 6 and the control unit 6, the control unit 6 latches the gate driving pulse input to the IGBT against an error caused by an overcurrent or a low voltage. A latch & reset control unit 7 which monitors and latches the gate drive pulse until the cause of the error is eliminated, and an optical signal informing the power supply control circuit of such an error operation signal when the overcurrent or undervoltage is detected. It comprises an optical signal transmitter 8 for transmitting the.

As described above, in one or more IGBTs constituting the power switching circuit, each IGBT is composed of the respective IGBT drive control unit 200,

Each configured IGBT constitutes an IGBT drive control unit 200 having the above configuration, and is switched by a gate pulse signal applied to the gate from the IGBT drive control unit 200 configured as described above, and switched from the outside. It will supply the used power supply voltage to the device.

The IGBT driving control unit 200 determines the gate driving voltage for the stable switching operation of the IGBT. The IGBT switching control operation of the IGBT driving control unit 200 will be described below.

The entire power supply control circuit outputs the gate pulse signal through the optical signal transmitter configured therein to operate the IGBT.

The gate pulse signal transmitted as described above is received by the optical signal input unit 1, and the received gate pulse signal is applied to the controller 6 through the gate pulse transmitter 2.

The control unit 6 outputs the switching control pulse signal according to the gate pulse signal input as described above, and amplifies the switching control pulse signal to the gate of the IGBT.

The IGBT receives the driving voltage input as described above, and accordingly switches to supply power to the device.

As described above, in the IGBT performing the switching operation, the overcurrent detecting unit 4 detects whether the overcurrent has occurred by detecting the collector terminal voltage of the IGBT and comparing it with the reference voltage.

At this time, if the IGBT fails to perform stable switching due to the failure of driving of the gate, the junction temperature is increased and the saturation voltage is increased accordingly, and when compared with the reference voltage, it is possible to detect whether overcurrent occurs. It will be possible.

As such, when an overcurrent is detected through the overcurrent detector 4, the controller 6 recognizes this and blocks the gate driving voltage of the IGBT to stop the operation of the IGBT.

The latch and reset unit 7 latches the gate driving voltage in a blocked state.

Thereafter, the latch and reset unit 7 redetects whether the overcurrent is sensed through the overcurrent detecting unit 4 at a predetermined time.

The control unit 6 controls the latch and reset unit 7 as described above to repeat the above operation until no overcurrent is detected. If no overcurrent is detected thereafter, the controller 6 releases the latch and restarts the IGBT. Drive.

In addition, when the gate driving voltage falls to a low voltage state below a predetermined voltage, the gate driving failure of the IGBT may be caused. Therefore, the low voltage detecting unit 5 detects the voltage compared with the comparison voltage and informs the controller 6.

The controller 6 recognizes this and controls the latch and reset unit 7 to control the operation of the IGBT by performing the same process as when the overcurrent is detected.

That is, if an overcurrent flows in the IGBT or the gate driving voltage falls below a certain voltage, the controller 6 stops the IGBT until the problem of the overcurrent or the low voltage is solved, thereby enabling stable switching of the IGBT.

If overcurrent or undervoltage occurs due to instantaneous surge voltage or power abnormality, IGBT will be cut off.Recognize that error has been resolved by repairing circuit or eliminating surge voltage by resetting error every certain time. It is to control the switching of the IGBT.

When the overcurrent or undervoltage condition is detected as described above, the error signal of the IGBT is transmitted to the power control circuit through the optical signal transmitter 8 to inform that the current IGBT is not normally operating.

FIG. 2 illustrates an embodiment of the power supply switching element driving control circuit of the present invention as described above. Referring to FIG. 2, its configuration and operation will be described below.

An optical signal input unit (1) comprising a receiving side optical coupler (PC1) for receiving a gate pulse signal transmitted from a light emitting side of a photo coupler, which is a transmitting means configured to transmit a gate pulse signal to a power supply control circuit Wow,

A logic circuit NAND gate 2a and a switching element transistor Q1 for switching the bias power + 5V applied according to the gate pulse signal to switch and convert the voltage to + 15V, which is a gate driving voltage, and to output the same. A logic circuit nand gate 2b for driving the light emitting diode LED1 for notifying the outside that pulse transfer is being made, transistor Q2 which is a switching element, and a gate pulse inputted as a trigger signal A gate pulse transmitter 2 including a Schmitt trigger 2c for shaping and outputting a pulse, and

When the gate is turned on with an AND gate 6a for outputting the gate pulse output from the Schmitt trigger 2c and a gate driving pulse output from the AND gate 6a as an input. The NAND gate 6b having the output signal and the gate pulse repeatedly outputted from the Schmitt trigger 2c to the high and low repetitive outputs of the amplifying unit 3 can detect the overcurrent. The NAND gate 6c for driving the field effect transistor FET1 and a gate pulse of high and low repetitive output from the Schmitt trigger 2c are inputted as a base to perform a switching operation to perform the switching operation of the amplifier 3. A control unit 6 including a transistor Q3 for driving the field effect transistor FET2 as a switching pulse inverted from the operation of the field effect transistor FET1;

The field effect transistor FET1 for driving the IGBT by amplifying the gate pulse input to the gate according to the output of the nend gate 6c and outputting it to the gate G of the IGBT, and inverted with the field effect transistor FET1. An amplifier 3 including a field effect transistor FET2 for receiving a driving voltage and turning off the IGBT on a negative voltage;

A high voltage blocking portion 4a for dropping the voltage at the collector C end of the IGBT to detect the overcurrent, and a filter portion 4b for filtering the voltage dropped through the high voltage blocking portion 4a; The variable resistor VR1 for setting the reference voltage for judging the overcurrent and the sense voltage applied through the filter unit 4b are negative inputs, and the variable resistor VR1 is used as a negative input. An overcurrent sensing section 4 including a comparator 4c for comparing the set voltages as positive inputs and comparing these voltages;

A reference voltage setting unit 5a for setting a reference voltage for determining whether the low voltage potential of the gate driving voltage (+ 15V) is set and a voltage of the gate driving voltage as positive (+) inputs, and the reference voltage setting unit 5a A low voltage sensing section 5 including a comparator 5b for comparing a low voltage displacement of the gate driving voltage by comparing these voltages with a reference voltage set by the negative input;

The NAND gate 7a for inverting and outputting the signal output from the comparator 4c of the overcurrent sensing unit 4 and the signal output from the comparator 5b of the low voltage sensing unit 5 are inverted and output. Recognizing the overcurrent and the low voltage state according to the Ned gate 7b and the signals input from the nend gates 7a and 7b, and if it is determined that the overcurrent and the low voltage state, the diodes (D10, D11) are conducted to the gate The latch 7c controls the input signal of the AND gate 6a of the pulse transfer unit 2 to latch the gate pulse in the blocked state, and the count starts from the time when the gate pulse is blocked by the latch 7c. When a predetermined time has elapsed, the counter 7d outputs a fault reset signal, the clock generator 7e providing a reference counter clock to the counter 7d, and the fault reset signal from the counter 7d. And from the comparator 4c of the overcurrent detector 4 An input gate 7f for resetting the latch state so that the gate pulse can be transmitted again when the output detection signal is input and the fault is removed, the output fault reset signal of the counter 7d and the low voltage detection A latch and reset section 7 including an end gate 7g for inputting the output signal of the comparator 5b to reset the latch state so that the gate pulse can be transmitted again;

An optical signal transmitter 8 including an optical coupler PC2 for transmitting a control signal for notifying the power supply control circuit that a fault has occurred;

The driver 9 is configured to drive the optical coupler PC2 to transmit a fault signal, and to drive an overcurrent generation warning light emitting diode LED2 indicating a fault has occurred and a low voltage generation warning light emitting diode LED3.

Reference numerals R1 to R26 are resistors, D1 to D11 are diodes, ZD1 to ZD3 are zener diodes, and C1 to C19 are capacitors.

Referring to the operation of the gate drive device of the present invention as shown in Figure 2 having such a configuration as follows.

The gate driving pulse transmitted from the optical coupler originating side of the power supply control circuit is received through the optical coupler PC1.

The gate pulse received as described above is input to the NAND gate 2a of the gate pulse transmitter 2, and the AND gate 2a performs an AND operation with the input bias voltage (+ 5V) and inverts the transistor Q1. ) To switch on / off.

In addition, the gate pulse as described above is input to the NAND gate 2b, and the transistor Q2 is turned on / off to flash the light emitting diode LED1, thereby indicating that normal pulse transmission is being performed.

Thereafter, as the transistor Q1 is switched on / off, a bias voltage applied to the collector terminal of the transistor Q1 is input to the trigger TRIG terminal of the schmitt trigger 2c.

That is, the gate driving voltage is converted from + 5V to + 15V.

In the Schmitt trigger 2c, a pulse waveform is shaped using a gate driving voltage pulse input to the trigger stage TRIG as a trigger, and is output to the AND gate 6a.

At this time, since the input of one side of the AND gate 6a is maintained in a high state, the input gate pulse is output through the AND gate 6a as it is.

The gate pulse output in this way is input to the base of the nand gate 6c and the transistor Q3.

The NAND gate 6c inverts the gate pulse which repeats high / low to switch the field effect transistor FET1 to supply a gate driving voltage to the gate terminal G of the IGBT to switch the IGBT.

At this time, when a low is input to the base of the transistor Q3, the transistor Q3 performs the on-switching operation, so that the field effect transistor FET2 performs the ounce switching, and thus the driving voltage is applied to the gate terminal G of the IGBT. By not applying this, the IGBT is stopped.

In other words, driving the IGBT to ± 15V, turn off the IGBT at -15V.

As described above, in the switching operation of the IGBT, when an overcurrent or a low voltage is generated, the IGBT is stopped for protection and stable switching operation of the IGBT.

The collector voltage of the IGBT drops while passing through the diodes D4, D5, D6, and D7 having the reverse biased configuration in the high voltage blocking portion 4a.

The voltage dropped in this manner is filtered by the diode D8 and the capacitor C9 of the pulver unit 4b, and is input to the negative of the comparator 4c as a voltage sensing result.

The positive voltage of the comparator 4c is input to the reference voltage set by the variable resistor VR1.

The comparator 4c compares these voltages and detects an overcurrent.

When the normal operation is performed, the high output is achieved because the positive reference voltage is larger. However, when the overcurrent flows, the output of the comparator 4c becomes low.

In other words, by detecting a voltage proportional to the current to determine whether the overcurrent, at this time, the resistance value of the variable resistor (VR1) is appropriately adjusted to set the reference voltage to match the overcurrent boundary value.

When the gate pulse repeated high / low is input from the AND gate 6a, the inverted signal of the signal is input from the NAND gate 6b so that the diode D9 switches on and off. do.

That is, since the diode D9 switches on / off, when the high pulse is input, that is, the IGBT performs the operation of detecting the overcurrent only at the ounce switching time.

At this time, when the overcurrent is detected and the output of the comparator 4c becomes low, the NAND gate 7a inverts it and applies it as a high signal to the CP2 terminal of the latch 7c.

Since the latch 7 recognizes the high signal input to the CP2 stage and outputs the Q2 signal as a high signal, The low signal is output through the stage to conduct the diode D10.

When the diode D10 is turned on, a low signal is inputted to the AND gate 6a, so that the gate pulse output from the Schmitt trigger 2c cannot be output, so that the IGBT is stopped.

At this time, a low signal is also input to the MR stage of the counter 7d, and counting starts with the reference clock input from the clock generator 7e from this time on the counter 7d.

After that, when the set time (about 30 msec) elapses, the counter 7d outputs a high signal through the O terminal and applies it to the AND gate 7f.

At this time, since the output of the comparator 4c is input to one input of the AND gate 7f, when the overcurrent is not solved while the count operation of the counter 7d is in progress, the one input of the AND gate 7f is low. Since the state is maintained, the reset signal output from the counter 7d is not input to the latch 7c.

Therefore, the latch 7c continues to latch with the gate pulse interrupted.

In addition, since the voltage output from the Q2 terminal of the latch 7c becomes high, this voltage is input to the I2 terminal of the driver 9.

When high is input to the I2 terminal as described above, the driver 9 outputs a high signal through the O6 terminal, and the high signal of the O6 terminal is inverted through the inverter of the O6 terminal to low signal to the light emitting diode LED2. By outputting the light-emitting diode (LED2) is lit to inform the outside that the overcurrent has occurred.

The driver 9 applies the low signal to the optical coupler PC2 via the inverter of the O2 stage in accordance with the signal input to the I2 stage as described above to drive the optical coupler PC2. Signals are sent to the receiving optical coupler configured to indicate that an overcurrent has occurred.

After that, when the detection voltage becomes smaller than the reference voltage and the output of the comparator 4c becomes high, the one side input of the AND gate 7f is kept high, and when the reset signal is output from the counter 7d, A high signal is output from the AND gate 7f and input to the CD2 end of the latch 7c.

When the reset signal is input to the CD2 terminal of the latch 7c as described above, the latch 7c outputs the signal output of the Q2 terminal as a low signal again. The output of the signal becomes a high signal and the diode D10 is turned off.

Therefore, since the input of one side of the AND gate 6a becomes high, the gate pulse is output as it is, and the IGBT is driven again.

That is, the latch 7c latches the gate pulse in the state of stopping the operation of the IGBT as described above, and when the overcurrent is not detected, inputs the gate pulse of the IGBT again according to the reset signal inputted to restart the IGBT. It is to be made.

On the other hand, the low voltage detection unit 5 compares the reference voltage set by the reference voltage setting unit 5a with the gate driving voltage (+ 15V) input through the resistor R14 to determine whether the low voltage,

In the comparator 5b, the reference voltage set through the reference voltage setting unit 5a is the negative input of the comparator 5b, and the gate driving voltage sensed through the resistor R14 is the positive input of the comparator 5b. These voltages are compared, and the compared signals are output as sensing signals.

In normal operation, the output of the comparator 5b is output as a high signal because the gate driving voltage is higher than the reference voltage, but the output of the comparator 5b is low because the gate driving voltage is lower than the reference voltage.

When the gate driving voltage is lower than the reference voltage, the output of the comparator 5b outputs a low signal, and the output low signal is inverted through the nand gate 7b to the CD1 terminal of the latch 7c. Is entered.

When the high signal is input to the CD1 terminal, the latch 7c recognizes the low voltage state and outputs the output of the Q terminal as the high signal.

therefore, Since the output of is low, the diode D11 is conducted so that one input of the AND gate 6a is low.

Therefore, since the output of the AND gate 6a is always low, the gate pulse cannot be transmitted and the IGBT is stopped.

Since the output of the Q terminal becomes high, the I1 terminal of the driver 9 is pulled high, so the driver 9 drives the light emitting diode LED3 through the O5 terminal to notify the outside that the current voltage is low. .

In addition, the optical coupler PC2 is operated through the O1 terminal to inform the power supply control circuit of the low voltage state.

At the same time, as in the operation control according to the overcurrent sensing, when one side input is low to the AND gate 6a, this low signal is input to the MR terminal of the counter 7d, thereby counting the counter 7d. It begins.

Thereafter, when a predetermined time elapses, a fault reset signal is output to the AND gate 7g.

At this time, as described above, since one side input of the AND gate 7g is an output of the comparator 5b according to whether the low voltage is detected, one side input of the AND gate 7g is low until the low voltage state is resolved. State is maintained.

If the low voltage condition is not solved, the output of the AND gate 7g goes low and is input to the CD1 of the latch 7c, so that the latch 7c latches the IGBT in a stopped state.

When the low voltage condition is solved and the one side input of the AND gate 7g becomes high, when a fault reset signal is input, a high signal is input to the CD1 terminal of the latch 7c, and the latch 7c outputs the output of the Q1 terminal. The diode D11 is turned off by making it high.

Therefore, when the diode D11 is turned off, since one side input of the AND gate 6a becomes high again, the gate pulse is transmitted to the IGBT again through the AND gate 6a, and the IGBT is driven again.

The voltage input to the comparator 5b is ± 13.5V to ± 15V when it is operating normally. However, when the gate voltage fails to supply a stable gate voltage due to a failure in establishing the gate voltage, the gate driving fails.

Therefore, when the low voltage is generated by detecting the gate driving voltage as described above, the IGBT is blocked.

As described above, by determining the overcurrent and undervoltage conditions and controlling the operation of the IGBT accordingly, the IGBT is protected from the overcurrent, and the cause of the gate driving failure is eliminated to provide a stable switching operation of the IGBT. have.

Claims (4)

Optical signal input means for receiving the gate pulse signal output from the power supply control logic, Gate pulse transmission means for transmitting the gate pulse signal input from the optical signal input means, Power supply switching means in accordance with the applied gate pulse A control means for outputting a switching control signal of an IGBT; An overcurrent sensing means for detecting an overcurrent, a low voltage sensing means for detecting a low voltage by comparing a gate driving voltage with a reference voltage, and a fault signal according to a result detected by the overcurrent sensing means or a low voltage sensing means. It consists of optical signal transmission means for transmitting to the power control logic, The control means stops the operation of the IGBT according to the result detected by the overcurrent detection means or the low voltage detection means, and monitors the detection result of the means every predetermined time to stop the operation of the IGBT until the cause of the error is resolved. And a latch and reset means configured to cause the large-capacity power supply switching element (IVT) drive control circuit. The power supply switching element (IVT) drive control circuit according to claim 1, further comprising: display means for notifying outside that an error has occurred, and drive means for driving the display means. 3. The receiving side optical coupler according to claim 1 or 2, wherein the optical signal input means is a receiving side optical coupler for receiving a gate pulse signal transmitted from a light emitting side of the optical coupler, which is a transmitting means configured to transmit a gate pulse signal to a power supply control circuit. (PC1), The gate pulse transmission means includes a logic circuit nandgate 2a and a switching element transistor Q1 for switching and outputting a + 5V bias power applied to the gate pulse signal to switch to a + 15V voltage which is a gate driving voltage. The gate pulse is generated by using a logic circuit nand gate 2b for driving the light emitting diode LED1 for notifying the outside that normal pulse transmission is being performed, a transistor Q2 which is a switching element, and an input gate pulse as a trigger signal. Is configured to include a Schmitt trigger (2c) for outputting the standardized, The control unit inverts the AND gate 6a for outputting the gate pulse output from the Schmitt trigger 2c, and the amplification unit by inverting the gate pulse repeatedly outputting the high and low gates from the Schmitt trigger 2c. (3) The NAND gate 6c for driving the field effect transistor FET1 and the gate pulse outputted from the Schmitt trigger 2c from the high and low repetitive outputs are inputted as a base to perform a switching operation. A switching pulse inverted from the operation of the field effect transistor FET1 of 3), comprising a transistor Q3 for driving the field effect transistor FET2; The amplifying means amplifies the gate pulse input to the gate according to the output of the nend gate 6c, outputs it to the gate G of the IGBT, and drives the IGBT, and the field effect transistor FET1. ) And a field effect transistor (FET2) for turning off the IGBT on the negative voltage by operating the inverted driving voltage. The overcurrent detecting means includes a high voltage blocking portion 4a for dropping the voltage at the collector C end of the IGBT and a filter portion 4b for filtering the voltage dropped through the high voltage blocking portion 4a. And the variable resistor VR1 for setting the reference voltage for determining the overcurrent and the sense voltage applied through the filter unit 4b as negative inputs, and are set by the variable resistor VR1. And a comparator 4c for comparing these voltages by using the reference voltages as positive inputs, The low voltage detecting means includes a reference voltage setting unit 5a for setting a reference voltage for determining whether the gate driving voltage (+ 15V) is a low voltage potential, a voltage of the gate driving voltage as a positive input, and the reference voltage. And a comparator 5b for detecting low voltage displacement of the gate driving voltage by comparing these voltages with the reference voltage set by the setting unit 5a as a negative (-) input, The latch and reset means outputs from the NAND gate 7a for inverting and outputting the signal output from the comparator 4c of the overcurrent sensing unit 4 and the comparator 5b of the low voltage sensing unit 5. Recognizing the overcurrent and undervoltage states according to the nand gate 7b for inverting and outputting the signal and the signals input from the nend gates 7a and 7b, and determining that the overcurrent and undervoltage states are present, the diodes D10 and D11 Is connected to the latch 7c for controlling the input signal of the AND gate 6a of the gate pulse transmitter 2 to latch the gate pulse in a blocked state, and the gate pulse is blocked by the latch 7c. The counter starts from the point of time, and when a predetermined time elapses, the counter 7d outputs a fault reset signal, the clock generator 7e providing a reference counter clock to the counter 7d, and the counter 7d. Fault reset signal and the overcurrent detector 4 An end gate 7f for resetting the latch state so that the gate pulse can be transmitted again when the sense signal output from the comparator 4c is input, and the fault is removed, and the output fault of the counter 7d. And an end gate (7g) for resetting the latch state so that the reset signal and the low voltage detection unit (5) input the output signal of the comparator (5b) so that the gate pulse can be transmitted again, The optical signal transmitting means comprises an optical coupler (PC2) for transmitting a control signal for notifying the power supply control circuit that a fault has occurred, The display means comprises an overcurrent warning light emitting diode (LED2) and a low voltage warning light emitting diode (LED3). The driving means drives the optical coupler (PC2) to transmit a fault signal, and generates an overcurrent indicating that a fault has occurred. And a driver (9) for driving a warning light emitting diode (LED2) and a low voltage warning light emitting diode (LED3). 4. The power supply switching method according to claim 3, further comprising a nend gate (6b) having an output signal to detect an overcurrent only when the gate is turned on by using a gate driving pulse output from the AND gate (6a) as an input. Element (IVT) drive control circuit.