KR19990057939A - How to remove damage after etching gate electrode pattern - Google Patents

Abstract

The present invention relates to a process for removing damage after etching a gate electrode pattern of a semiconductor device, and to provide a method of manufacturing a semiconductor device which prevents abnormal oxidation during the reoxidation process after etching a gate electrode pattern while excluding a high temperature process of 900 ° C. or more. There is this. The present invention provides a process for recovering etching damage by performing nitriding heat treatment using NO gas at a temperature of 700 to 800 ° C after etching the gate electrode pattern. In addition to nitriding silicon (Si) even at relatively low temperatures, such as 800 ° C, NO gas can cause oxidation of silicon by inducing a self-limiting effect due to nitrogen pile-up. It has the property of preventing. Due to this self-limiting effect, the edge portion of the gate oxide film is hardly oxidized during heat treatment to suppress the gate bird's beak phenomenon, and to the gate oxide film edge and the remaining oxide film damaged by etching. Nitrogen can be effectively combined to repair defects generated during etching. In addition, this nitrogen accumulation leads to an increase in immunity to hot carrier stress. On the other hand, if the outside air is completely removed by the vacuum process before raising the temperature to about 800 ° C. and NO gas is introduced, the edge portion of the silicide film is nitrided to prevent abnormal oxidation of the silicide film.

Description

How to remove damage after etching gate electrode pattern

TECHNICAL FIELD The present invention relates to the field of semiconductor manufacturing, and more particularly, to a process of forming a gate electrode of a semiconductor device, and more particularly, to a process of removing damage after etching a gate electrode pattern of a semiconductor device.

Various patterns including gate electrodes have been miniaturized due to high integration of semiconductor devices, and in recent years, miniaturization has been progressed to a line width of 0.25 µm or less. Accordingly, the impurity doped polysilicon film used in the conventional gate electrode formation has a problem in that it is difficult to be applied to devices requiring fast operation because of its high resistivity and long delay time. This problem is becoming more serious due to the high integration of semiconductor devices, and in consideration of this, interest in the gate electrode having a polyside structure using a titanium silicide film, a cobalt silicide film, etc., including a tungsten silicide film is increasing.

However, in applying such a polyside structure to a gate electrode, there is a problem that a re-oxidation process for recovering etching damage of the gate oxide film and the substrate after the gate patterning is not easy. This is because, when the silicide film is exposed to the oxidizing environment, an abnormal oxidation of the silicide film occurs, in which an oxide metal in the silicide film is oxidized to generate an ear silicide defect or an abnormal reaction. Considering this problem, annealing at a high temperature of about 900 ° C. can reduce anomalous oxidation to some extent. However, in high-integration devices that require short channel and shallow junction characteristics, such high temperature processes are not. It is difficult to apply a polyside gate electrode to a highly integrated device because it may cause fatal deterioration of operating characteristics.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device which prevents abnormal oxidation during the reoxidation process after etching the gate electrode pattern while excluding a high temperature process of 900 ° C. or higher.

1A to 1D are MOS transistor forming process diagrams according to an embodiment of the present invention.

2 is a detailed flowchart of a heat treatment process using NO gas applied to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

10 silicon substrate 11 device isolation film

12 gate oxide film 13 polysilicon film

14 tungsten silicide film 15 mask oxide film

16: residual oxide film 17: source / drain

18: oxide spacer 12a, 14a, 16a: nitrided portion

The present invention provides a process for recovering etching damage by performing nitriding heat treatment using NO gas at a temperature of 700 to 800 ° C after etching the gate electrode pattern. In addition to nitriding silicon (Si) even at relatively low temperatures, such as 800 ° C, NO gas can induce self-limiting effects due to nitrogen pile-up, which leads to oxidation of silicon. It has the property of preventing. Due to this self-limiting effect, the edge portion of the gate oxide film is hardly oxidized during heat treatment to suppress the gate bird's beak phenomenon, and to the gate oxide film edge and the remaining oxide film damaged by etching. Nitrogen can be effectively combined to repair defects generated during etching. In addition, this nitrogen accumulation leads to an increase in immunity to hot carrier stress. On the other hand, if the outside air is completely removed by the vacuum process before raising the temperature to about 800 ° C. and NO gas is introduced, the edge portion of the silicide film is nitrided to prevent abnormal oxidation of the silicide film.

A characteristic semiconductor device manufacturing method provided from the above-described invention includes a first step of sequentially laminating a gate insulating film, a polysilicon film, and a silicide film on a semiconductor substrate; A second step of forming a gate electrode pattern by selectively etching the silicide layer, the polysilicon layer, and the gate insulating layer; And performing a heat treatment in an NO gas atmosphere to nitride the gate insulating film and the gate electrode pattern.

In addition, a characteristic semiconductor device manufacturing method provided from the present invention includes a first step of sequentially laminating a gate insulating film, a polysilicon film on a semiconductor substrate; A second step of forming a gate electrode pattern by selectively etching the polysilicon layer and the gate insulating layer in sequence; And performing a heat treatment in an NO gas atmosphere to nitride the gate insulating film and the gate electrode pattern.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention.

1A to 1D illustrate a process of forming a MOS transistor according to an embodiment of the present invention. Hereinafter, a process of etching and removing damage after etching the gate electrode pattern to which the tungsten silicide layer is applied according to an embodiment of the present invention will be described.

First, as shown in FIG. 1A, an isolation layer 11 is formed on a silicon substrate 10, and a phosphorous-doped polysilicon layer doped with a gate oxide layer 12 and phosphorus on an exposed active region is formed. (13), the tungsten silicide film 14 and the mask oxide film 15 are sequentially deposited.

Next, as illustrated in FIG. 1B, the gate electrode pattern is defined by selectively etching the polysilicon layer 13 using the gate electrode mask. Reference numeral 16 denotes a residual oxide 16 left to prevent damage to the silicon substrate 10 in the etching process.

Subsequently, as illustrated in FIG. 1C, a heat treatment using NO gas is performed to remove etch damage of the gate oxide film 12 at the edge portion of the gate electrode pattern, thereby nitriding each layer constituting the gate electrode. At this time, the accumulation of nitrogen caused by the edge portion 12a of the gate oxide 12 film prevents the oxidation of Si by the self-limiting effect, and due to this property, the edge portion of the gate oxide film 12 is hardly oxidized so that the gate buzz Beaking will not occur. At this time, the edge portion 14a of the tungsten silicide film 14 is also nitrided to prevent oxidation of tungsten (W), thereby preventing abnormal oxidation such as ear tungsten silicide defects or abnormal reactions. In addition, the residual oxide film 16 is nitrided to recover the etching damage. Reference numeral 16a denotes a nitrided residual oxide film.

Next, n ⁻ source / drain ion implantation is performed to form a lightly doped drain (LDD) structure as shown in FIG. 1D, and an oxide spacer 18 is formed on the sidewall portion of the gate electrode pattern. This oxide spacer 18 is vulnerable to subsequent hot carriers, and the immunity to hot carrier stress is increased by the nitrided residual oxide film 16a formed thereunder. Thereafter, the subsequent process is performed.

2 is a detailed flowchart of a heat treatment process using NO gas applied to an embodiment of the present invention described above.

As shown, the NO nitriding process according to the present invention is a batch type furnace (or a furnace that is perfectly safe and capable of removing the outside air completely). ), A wafer is loaded into a reactor such as a rapid heat treatment chamber or a single wafer type chemical vapor deposition chamber, and a vacuuming step is performed to completely remove external air. Until this time, the process temperature is adjusted to 600 ° C or lower. Subsequently, after ramping up to 800 ° C., the NO gas is flowed up to 10 L under a pressure of about 100 Torr to 400 Torr through a temperature stabilization step and annealed for 1 hour in the NO gas atmosphere. At this time, the pressure is limited to about 400 Torr for safety, in a system that can ensure more stability can be carried out the nitriding process by raising the pressure to 1 atm. The process is then conventional, followed by a purge step, a temperature reduction step, a back-fill step and an unloading step.

In the above-described embodiment of the present invention, a tungsten silicide film has been described as an example. However, the present invention can be applied to a gate electrode structure employing a silicide film made of a cobalt, molybdenum, titanium, or the like, and a general polysilicon film gate. Even when applied to the structure it is possible to obtain an excellent etching damage prevention effect compared to the prior art.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

The present invention can prevent the gate buzz beak phenomenon to suppress the reduction of the drain saturation current (I _{d, sat} ), nitrogen is effectively bonded to the gate oxide edge and the remaining oxide film to recover the defects due to etching and hot Immunity to carrier stress can be increased to improve operating characteristics and reliability of the semiconductor device. In addition, the present invention can be applied to the production of highly integrated semiconductor devices of 1G DRAM or higher by performing heat treatment at a relatively low temperature around 800 ℃ to prevent abnormal oxidation of the silicide film.

Claims (9)

A first step of sequentially laminating a gate insulating film, a polysilicon film, and a silicide film on a semiconductor substrate; A second step of forming a gate electrode pattern by selectively etching the silicide layer, the polysilicon layer, and the gate insulating layer; A third step of performing a heat treatment in an NO gas atmosphere to nitride the gate insulating film and the gate electrode pattern A semiconductor device manufacturing method comprising a. The method of claim 1, In the second step And a portion of the gate insulating film remains on the semiconductor substrate. The method of claim 1, The third step is A semiconductor device manufacturing method made under a temperature of 700 ℃ to 900 ℃. The method of claim 1, The third step A method for manufacturing a semiconductor device at a pressure of at least 100 Torr. The method of claim 1, The silicide film A method of manufacturing a semiconductor device, which is any one of a tungsten silicide film, a titanium silicide film, a cobalt silicide film, and a molybdenum silicide film. The method of claim 1, After performing the third step And forming an insulating film spacer on the sidewall portion of the gate electrode pattern. The method of claim 1, The third step is A method for manufacturing a semiconductor device, which is made in a reaction furnace of a batch furnace, a rapid heat treatment chamber, or a single wafer type chemical vapor deposition chamber capable of a pressure reduction process. The method of claim 1, The third step is A method of manufacturing a semiconductor device using the NO gas not exceeding 10 l. A first step of sequentially laminating a gate insulating film and a polysilicon film on the semiconductor substrate; Forming a gate electrode pattern by selectively etching the polysilicon layer and the insulating layer in sequence; A third step of performing a heat treatment in an NO gas atmosphere to nitride the gate insulating film and the gate electrode pattern A semiconductor device manufacturing method comprising a.