KR19990055115A - Static random access memory device - Google Patents

Abstract

A static random access memory (SRAM) device of the present invention includes at least one word line; At least a pair of bit lines; At least one memory cell coupled between the bit lines and having two access transistors, two storage transistors, and two load transistors; A peripheral circuit receiving a first power supply voltage; Wherein each load transistor has a source, a drain and a gate, the sources are supplied with a second power supply voltage, the drains are grounded through corresponding storage transistors, and the gates are controlled to the corresponding word lines, Respectively connected to the corresponding bit lines through the access transistors, and their bulks are biased by a third supply voltage.

Description

STATIC RANDOM ACCESS MEMORY DEVICE

The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory device.

1 is a block diagram illustrating a power supply voltage relationship between a memory cell and a peripheral circuit of a semiconductor memory device according to the related art.

In recent years, in the manufacture and design of static random access memory (SRAM) devices, reliability has become a big issue. In particular, it is virtually impossible to screen any potential failures in a cell array during the initial test process at normal supply voltage structures. In order to solve this issue, a normal power supply voltage structure, that is, as shown in FIG. 1, through the same power pad 22 to the peripheral circuitry 20 and the memory cell array 10 is provided. In a structure in which a supply voltage VCC of the same potential is supplied, there is always a reliability debate because only a significant test time as well as stress due to a limited supply voltage are possible.

It is therefore an object of the present invention to provide a static random access memory device with improved reliability.

It is another object of the present invention to provide a static random access that can shorten the test time by biasing the bulk of the load transistors of the memory cell with voltages of different potentials, while also providing different supply voltages of the memory cells and peripheral circuits during the test. It is to provide a memory device.

1 is a block diagram showing a power supply voltage relationship between a memory cell and a peripheral circuit of a semiconductor memory device according to the prior art;

2 is a block diagram showing a power supply voltage relationship between a memory cell and a peripheral circuit of a semiconductor memory device according to the present invention;

* Explanation of symbols on the main parts of the drawings

10: memory cell array 20: peripheral circuit

22, 30, 40, 50: power voltage pad

(Configuration)

According to one aspect of the present invention for achieving the above object, at least one word line; At least a pair of bit lines; At least one memory cell coupled between the bit lines and having two access transistors, two storage transistors, and two load transistors; A peripheral circuit receiving a first power supply voltage; Wherein each load transistor has a source, a drain and a gate, the sources are supplied with a second power supply voltage, the drains are grounded through corresponding storage transistors, and the gates are controlled to the corresponding word lines, Respectively connected to the corresponding bit lines through the access transistors, and their bulks are biased by a third supply voltage.

In this embodiment, the first, second and third power supply voltages have the same potential during normal operation.

In this embodiment, the second and third power supply voltages have a potential different from the first power supply voltage during a test operation.

In this embodiment, the second and third power supply voltages have different potentials or have the same potential during the test operation.

(Action)

With such a device, the power supply voltage of the memory cell and the power supply voltage of the peripheral circuits can be provided differently during the test, and the bulk of the load transistors of the memory cell can also be biased to voltages of different potentials.

(Example)

Hereinafter, the present invention will be described in detail with reference to FIG. 2. In FIG. 2, the same reference numerals are given together about the components which have the same function as the component of FIG.

In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.

The static random access memory device according to the present invention maintains the power supply voltages of the memory cell array and the peripheral circuits the same during normal operation, and is driven by power supply voltages having different potentials in the wafer test step. In addition, by separating the source and the bulk of the load transistors of the memory cell with different bond pads, the potential of the source and the bulk can be tested by the same or different potentials. As a result, it is easy to determine the DC current path of the memory cell array and the peripheral circuit by separating the power supply voltage of the cell source and the bulk supply voltage of the cell source as well as the stress effect through the expansion of the stress area.

Referring to FIG. 1, a block diagram showing a supply voltage supply relationship between a memory cell and a peripheral circuit of a semiconductor memory device according to the present invention is shown. The semiconductor memory device according to the present invention includes a memory cell array 10 and a peripheral circuit 20. For convenience, the memory cell array 10 has one memory cell, one word line WL and a pair of bit lines BL and BLB, but more cells and their associated bit lines and word lines. It is obvious to those who have acquired common knowledge in this field.

Referring back to FIG. 1, the memory cell includes two access transistors T1 and T2, two storage transistors T3 and T4, and two load transistors. Consisting of (T5) and (T6). The transistors T1-T4 are composed of N-channel metal oxide semiconductor transistors (hereinafter referred to as NMOS) transistors, and the transistors T5 and T6 are P-channel metal oxide semiconductor ( metal oxide semiconductor (hereinafter referred to as PMOS) transistors.

The gate of the transistor T1 is connected to the word line WL, and its current path is connected between the bit line BL and the node A. The gate of the transistor T2 is connected to the word line WL, and its current path is connected between the bit line BLB and the node B. The current paths of the transistors T5 and T3 are sequentially formed in series between the power pad 50 and the ground, the gates of which are commonly connected to the node B. The current paths of the transistors T6 and T4 are sequentially formed in series between the power pad 50 and ground, the gates of which are commonly connected to the node A. Here, the bulks of the transistors T5 and T6 are commonly connected to the power pad 40.

The peripheral circuit 20 receives the power supply voltage VCC1 from the power pad 30. The power supply voltages VCC1, VCC2 and VCC3 applied through the power pads 30, 40 and 50, respectively, have the same potential during normal operation, and the power supply voltages VCC2 And VCC3 has a potential different from the power supply voltage VCC1 during a test operation. The power supply voltages VCC2 and VCC3 may have different potentials or have the same potential during a test operation. It should be noted, however, that the power pads VCC1, VCC2 and VCC3 are bonded as the same pad in the package step.

In the SRAM device having the power supply voltage structure described above, the power supply voltage of the memory cell can be controlled at a voltage level of a potential different from that of the peripheral circuit 20, so that the reliability or stress test can be performed. For example, a weak cell that can always be screened with a pass in a normal power supply voltage structure may be detected and repaired as a fail cell during a test operation. In addition, even though a leakage path exists through the transistors T5 and T6, normal operation is performed, but a super voltage is applied to the source and bulk of the transistors T5 and T6. A weak cell can be detected as a fail cell and repaired.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.

As described above, by separating the power supply voltages of the memory cell array and the peripheral circuit in the wafer state, the reliability can be improved through the cell stress and the initial DC current can be irradiated.

Claims (4)

At least one word line; At least a pair of bit lines; At least one memory cell coupled between the bit lines and having two access transistors, two storage transistors, and two load transistors; A peripheral circuit receiving a first power supply voltage; Wherein each load transistor has a source, a drain and a gate, the sources are supplied with a second power supply voltage, the drains are grounded through corresponding storage transistors, and the gates are controlled to the corresponding word lines, And are respectively coupled to corresponding bit lines through the access transistors, and their bulks are biased by a third power supply voltage. The method of claim 1, And wherein the first, second and third power supply voltages have the same potential during normal operation. The method of claim 1, And the second and third power supply voltages have a potential different from the first power supply voltage during a test operation. The method of claim 3, wherein And said second and third power supply voltages have different or equal potentials during a test operation.