KR19990053212A - Drexel and its manufacturing method - Google Patents

Abstract

The present invention relates to a DRAM cell including a MOS transistor and a capacitor and a method of manufacturing the same. In order to prevent a short channel phenomenon, a gate electrode in a silicon substrate is disposed so that three sides of the gate electrode can be utilized as a channel region And achieves interlayer insulation with a smaller number of interlayer insulating films than in the prior art, thereby improving the bit line and capacitor contact margin.

Description

Drexel and its manufacturing method

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a DRAM cell including a MOS transistor and a capacitor, and a manufacturing method thereof.

1 is a process sectional view showing a conventional DRAM cell.

As shown in FIG. 1, a polysilicon film 12 and a silicide film 13 are formed of a gate oxide film and a gate conductive film on a silicon substrate 11, and then a gate electrode is patterned by selective etching. Next, a spacer is formed on the side wall of the gate electrode, and a source and a drain (not shown in the figure) are formed. A BPSG film 15 is formed as a first interlayer insulating film and a BPSG film 15 and an MTO film 14 are selectively formed And a bit line contact hole for exposing the underlying silicon substrate 11 is formed by etching. Here, the BPSG film 15 and the MTO film 14 are films for insulation between the gate electrode and a bit line to be formed later, and the oxide films (BPSG film 15 and MTO film 14) ) Must be etched.

Next, a polysilicon film 16, a tungsten silicide film 17 for forming bit lines, and a nitride film 20 for preventing the bit lines from being etched are formed on the tungsten silicide film 17 and then patterned. Then, a BPSG film 18 is formed as a second interlayer insulating film.

Next, the multilayer insulating films of the BPSG films 18 and 15 and the MTO film 14 as the second and first interlayer insulating films are etched to form charge storage electrode contact holes of the capacitor, and the polysilicon film 19 is deposited Thereby forming a charge storage electrode of the capacitor. Also, it can be seen that the etching process for forming the contact hole of the charge storage electrode of the capacitor must also etch the multilayer insulating film.

In the DRAM cell having the above-described structure, since the gate electrode serving as a switch and the source and the drain are arranged in a planar configuration on both sides thereof, a channel is formed between the source and the lower portion A of the gate And is formed in a two-dimensional shape directed toward the drain. Therefore, a channel is formed in the two-dimensional channel region A by the bias applied to the gate electrode, and current flows. The linear two-dimensional channel of the gate lower portion A leads to a decrease in the width of the gate as the device becomes more highly integrated, thereby causing short channel phenomenon. Therefore, it is necessary to develop a new DRAM cell which can prevent short channel phenomenon and incidental parasitic effects even if the gate width is reduced. Also, it is necessary to develop a DRAM cell which can effectively reduce the horizontal length and vertical length of the device It is necessary to develop a forming method.

In addition, as described above, since the multilayer insulating film must be etched for the contact of the bit line and the charge storage electrode, the contact margin is reduced and the aspect ratio of the contact hole is increased.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a DRAM cell capable of preventing a short channel phenomenon induced by a gate width shortening in a highly integrated DRAM, and a manufacturing method thereof.

Another object of the present invention is to provide a DRAM cell capable of improving a contact margin of a bit line and a charge storage electrode and a method of manufacturing the same.

1 is a process sectional view showing a conventional DRAM cell structure.

2 is a cross-sectional view illustrating a structure of a DRAM cell according to an embodiment of the present invention;

FIGS. 3A through 3E are cross-sectional views illustrating a method of fabricating a DRAM cell according to an embodiment of the present invention; FIGS.

4 is a layout diagram for manufacturing a DRAM cell.

DESCRIPTION OF THE REFERENCE NUMERALS

31: silicon substrate 32: field oxide film

35: gate oxide film 36: polysilicon film

37: tungsten film 38: source and drain junction regions

39: oxide film 40, 41: bit line

42: tungsten silicide 43: nitride film

44: interlayer insulating film 45: capacitor

According to an aspect of the present invention, there is provided a DRAM comprising: a local insulating layer positioned below a surface of a semiconductor substrate to define an active region of the device; A gate electrode formed below the semiconductor substrate surface of the active region through a gate insulating film; Source and drain regions formed on the side of the gate electrode below the semiconductor substrate surface of the active region; A bit line insulated from the gate electrode to be in contact with the source region; A capacitor insulated from the gate electrode and the bit line to be in contact with the drain region; And a nitride film formed on the surface of the semiconductor substrate, the bit line side, and the bit line to insulate the capacitor, the bit line, and the gate electrode, respectively.

According to another aspect of the present invention, there is provided a method of manufacturing a DRAM cell, including: forming a device isolation insulating film in a semiconductor substrate; A second step of forming a trench for forming a gate electrode on a semiconductor substrate of an active region defined by the element isolation insulating film; A third step of forming a gate oxide film and a gate conductive film on the trench; A fourth step of forming source and drain regions in the active region beside the gate conductive film; A fifth step of forming a monolayer first oxide film exposing the source region; A sixth step of forming a bit line pattern by selectively etching the second oxide film, the bit line conductive film, and the first oxide film by laminating a bit line conductive film and a second oxide film on the result of the fifth step; A seventh step of forming a nitride film along the step of the finished product of the sixth step; An eighth step of forming a third oxide film on the nitride film; And forming a capacitor contact hole by etching the third oxide film and the nitride film.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a cross-sectional view illustrating a structure of a DRAM cell according to an embodiment of the present invention, and FIGS. 3A through 3E are cross-sectional views illustrating a method of fabricating a DRAM cell according to an embodiment of the present invention.

Referring to FIG. 2, there is shown a DRAM cell having a MOS transistor inside a silicon substrate 31 and a capacitor and a bit line above the silicon substrate 31.

That is, an oxide film 32 as a trench type element isolation film for device isolation is formed in the silicon substrate 31, and a gate oxide film 35, a polysilicon film 36, A gate electrode embedded with the tungsten film 37 is formed. Source and drain regions 38 are formed in the active region on the side of the gate electrode.

A bit line formed of the polysilicon films 40 and 41 and the tungsten silicide film 42 is contacted to the source (or drain) region 38 and the drain (or source) region 38 are contacted with a capacitor 45 composed of a first electrode, a dielectric film, and a second electrode.

The DRAM cell having the above structure can secure a channel length that can sufficiently overcome the short channel phenomenon despite the decrease in the gate width due to the high integration of the device by utilizing the three sides of the gate electrode as the channel region .

The bit line is connected to the source (or drain) region 38 through the single oxide film 39 and the capacitor 45 passes only through the oxide film 44 and the nitride film 43 to form the drain (or source) region 38 It is understood that the contact margin can be greatly increased as compared with the conventional structure.

4 is a layout diagram for manufacturing a DRAM cell. Reference numeral 401 designates a mask for forming a trench of the buried gate electrode, 402 designates a mask for device isolation, 403 designates a mask for a bit line pattern, , And "404" denote masks for forming contact holes, respectively, and a dummy cell is manufactured using such a mask. Hereinafter, an embodiment of the present invention will be described by taking a process sectional view taken along the line A-A 'in FIG. 4 as an example.

3A to 3E, a method of fabricating a DRAM cell according to an embodiment of the present invention will be described in detail.

3A, a pad oxide film 33 is formed on a silicon substrate 31 and a nitride film 34 is formed as a film for preventing the underlying silicon substrate 31 from being oxidized by a subsequent thermal process ). Subsequently, the nitride film 34 and the pad oxide film 33 are etched by an etching process using an element isolation mask (see "402" in FIG. 4), and the silicon substrate 31 which is subsequently exposed is etched at a certain depth to form a trench do.

The oxide film 32 as a trench type isolation film is formed by polishing the surface of the nitride film 34 after forming the oxide film 32 filling the trench.

Next, as shown in FIG. 3B, the nitride film 34, the pad oxide film 33, and the silicon substrate 31 are sequentially formed by using a mask (see "401" in FIG. 4) for forming the trenches of the gate electrode By etching, a plurality of trenches are formed in the silicon substrate 31 in the active region for forming the gate electrode.

Next, as shown in FIG. 3C, a gate oxide film 35 is formed on the silicon substrate 31 exposed by trench formation, and a polysilicon film 36 having excellent step coverage is formed as a conductive film, A tungsten film 37 buried in the tungsten film 37 is formed to form a gate electrode. Then, a polishing process is performed so that the surface of the silicon substrate 31 is exposed. Here, the tungsten film 37 inside the trench is formed to improve the conductivity of the gate electrode.

Next, as shown in FIG. 3D, the source and drain regions 38 are formed by ion implanting the silicon substrate 31 using an ion implantation mask. Subsequently, an oxide film 39 is formed, a bit line contact hole exposing the source (or drain) region 38 is formed by selectively etching the oxide film 39, and then, as a conductive film buried in the contact hole, A film 40 is formed. A polysilicon film 41, a tungsten silicide film 42 and an oxide film 47 are deposited thereon to form a bit line mask pattern (see "403" in FIG. 4). Here, the oxide film 47 is formed to prevent the bit line to be patterned from being inaccurately etched due to misalignment or the like. In addition, since the single oxide film 39 is etched during the etching for forming the bit line contact holes, etching with a large bit line contact margin can be performed. When the ion implantation for forming the source and drain regions 38 is performed, the channel depth formed on the three sides of the gate can be controlled by adjusting the junction depth.

Finally, the bit line is patterned by etching the oxide film 47, the tungsten silicide film 42, the polysilicon film 41, and the oxide film 39, as shown in FIG. 3E. Then, a nitride film 43 is formed on the entire structure along the lower step, an oxide film 44 is formed thereon as an interlayer insulating film, and a capacitor 45 is formed by a normal process. Here, the nitride film 43 formed along the lower step serves to insulate the capacitor 45 from the bit line and the gate electrode at the same time.

In the method of forming the DRAM according to the present invention, since the bit line contact etching is performed only by etching the oxide film 39 composed of a single layer, compared to the conventional method of forming the bit line contact hole by etching the multilayer interlayer insulating film, Can be increased. In addition, the formation of the nitride film 43 formed on the entire structure along the lower step after the formation of the bit line simultaneously insulates the gate electrode and the bit line, while the misalignment occurs due to the small pattern size upon the charge storage electrode contact etching. Lt; RTI ID = 0.0 > bitline < / RTI > That is, the nitride film 43 serves as an etch stop layer when the oxide film 44 is etched.

Also, since the gate electrode is formed in the silicon substrate, the three sides of the gate electrode can be utilized as a channel region.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Will be clear to those who have knowledge of.

According to the present invention as described above, a gate is formed in a silicon substrate in order to form a channel on three sides of a gate when a bias is applied to the gate electrode in manufacturing a semiconductor device including a MOS transistor and a capacitor It is possible to sufficiently prevent the short channel phenomenon caused by the decrease in the gate width. Accordingly, not only is it highly advantageous in terms of high integration of the device in terms of electrical characteristics, but also the gate is positioned under the silicon substrate structurally, which is advantageous for the planarization process of the device, thereby improving the yield of the device. In order to improve the conductivity of the gate electrode, a tungsten film is formed on the polysilicon film to improve the conductivity of the device. In addition, the contact margin of the bit line and the capacitor is greatly improved, which leads to improvement in the manufacturing yield of the device.

Claims (8)

A local insulating film positioned below the surface of the semiconductor substrate and defining an active region of the device; A gate electrode formed below the semiconductor substrate surface of the active region through a gate insulating film; Source and drain regions formed on the side of the gate electrode below the semiconductor substrate surface of the active region; A bit line insulated from the gate electrode to be in contact with the source region; A capacitor insulated from the gate electrode and the bit line to be in contact with the drain region; And A nitride film formed on the surface of the semiconductor substrate, on the side of the bit line, and on the bit line to insulate the capacitor, the bit line, . The method according to claim 1, A polysilicon film having the gate electrode stacked thereon, and a tungsten film. The method according to claim 1, Wherein the bit line includes a plug polysilicon film, a polysilicon film, and a tungsten silicide film. The method according to claim 1, Wherein the capacitor is connected to the drain region through the oxide film and the nitride film. The method according to claim 1, And the bit line is connected to the source region through the single-layer oxide film. A first step of forming an element isolation insulating film in a semiconductor substrate; A second step of forming a trench for forming a gate electrode on a semiconductor substrate of an active region defined by the element isolation insulating film; A third step of forming a gate oxide film and a gate conductive film on the trench; A fourth step of forming source and drain regions in the active region beside the gate conductive film; A fifth step of forming a monolayer first oxide film exposing the source region; A sixth step of forming a bit line pattern by selectively etching the second oxide film, the bit line conductive film, and the first oxide film by laminating a bit line conductive film and a second oxide film on the result of the fifth step; A seventh step of forming a nitride film along the step of the finished product of the sixth step; An eighth step of forming a third oxide film on the nitride film; Forming a capacitor contact hole by etching the third oxide film and the nitride film, Wherein the method comprises the steps of: The method according to claim 6, Wherein the gate conductive film comprises a polysilicon film and a tungsten film. The method according to claim 6, Wherein the conductive film of the bit line includes a plug polysilicon film, a polysilicon film, and a tungsten silicide film.