KR19990050218A - Vertical sync signal detection device for digital television - Google Patents

Abstract

In particular, the present invention relates to a vertical synchronization signal detecting apparatus in a US-oriented digital TV receiver using a residual side band (VSB) method. A reference signal generator for generating a reference vertical synchronization signal having the same pattern as that inserted by the transmitter each time it is input, and a process of comparing the output of the code bit extractor and the output of the reference signal generator for a predetermined symbol for each symbol. The data segment, which is performed for each data segment and determined that both signals are the same during a predetermined symbol, is determined as a vertical synchronization signal section. PN 63 pattern of the reference vertical sync signal generated by the generator in 63 symbol units By generating the Foe signal representing the even / odd field by comparing with each other, the vertical synchronization signal and the even / odd field are detected using only the most significant bit having the sign information among the input digital data. The number of sea gates can be reduced by about one-third, which facilitates integration and reduces IC size, resulting in lower cost.

Description

Vertical sync signal detection device for digital television

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for detecting vertical synchronizing signal in a US-oriented digital TV receiver using a residual sideband (VSB) scheme.

High Definition Television (High Definition Television) is the next generation of digital television systems developed to allow you to feel the impression of a theater in your room. Compared to current analog TVs, the screen resolution is much higher (e.g. 1080 × 1920) and wider in the horizontal direction (4: 3.5: 3.1.85: 1.2.4: 1, etc.). CD-level sound is supplied in multiple channels (up to 5.1 channels).

Such digital TVs are being standardized by the US, Europe, and Japan in their own broadcasting methods and standards. In the United States, the transmission format adopts the residual sideband (VSB) method proposed by Zenith in the United States, the compression format adopts MPEG (MPEG) for video compression, and Dolby AC-3 for audio compression. The display format is specified to be compatible with existing display methods.

Error correction coding (ECC) is performed on the compressed image data to digitally transmit the image data compressed according to the above standard. At this time, in order to facilitate data recovery on the receiving side, a synchronization signal is created and inserted into a predetermined period between the data before transmitting the data.

The synchronization signal is largely classified into two types, one as a horizontal synchronization signal and a data segment synchronization signal, and the other as a vertical synchronization signal and called a field synchronization signal. The horizontal and vertical synchronization signals are different from the horizontal and vertical synchronization signals of NTSC.

Here, one data segment will be described first. As shown in FIG. 1, the horizontal synchronization signal is composed of four symbols and the data of 828 symbols. The horizontal synchronization signal is not error corrected coded. That is, each data segment is composed of four symbols of horizontal synchronization signal and 828 symbols of data + EEC signal. A field consists of 313 data segments. The 313 data segment is composed of one field sync segment and a general data segment of 312 including a training sequence signal.

That is, the transmitting side, such as a broadcasting station, passes a mapper that changes to a desired power level before transmitting a signal. In the case of 8 VSB for terrestrial broadcasting, the output level of the mapper is 8 symbol values (amplitude level), that is,- 168, -120, -72, -24, 24, 72, 120, 168. In addition, the mapper forcibly creates and inserts 4 symbols of horizontal sync signals for every 832 symbols by appointment, and forcibly creates and inserts vertical sync signals at 313 data segment positions.

At this time, the promised form of the horizontal synchronization signal is logically 1, 0, 0, 1, and the mapper output level is assigned to '120' when the synchronization is '1' and '-120' when the '0'. That is, the horizontal synchronizing signal has only two levels and is repeated every data segment continuously.

In addition, the vertical synchronization signal has a length of one data segment, as shown in FIG. 2, and the horizontal synchronization pattern '1001' exists in the first four symbols, and then a pseudo random sequence is generated. PN 511, PN 63, PN 63, and PN 63, which are random sequences, exist, the VSB mode-related information exists in the next 24 symbols, and then there is a reserved region. Here, the second PN 63 of the three PN 63 section is changed in polarity every time. That is, '1' is changed to '0' and '0' is changed to '1'. Therefore, it may be divided into even / odd fields according to the polarity of the second PN 63.

On the other hand, when a receiving side such as a television receives a VSB modulated RF signal through an antenna as shown in FIG. 3, the tuner 31 selects a frequency of a desired channel by tuning and converts it into an IF signal. ) Demodulates the IF signal output from the tuner 31 into the I and Q signals of the base band to lock the frequency and phase. That is, the FPLL unit 32 is a circuit in which a frequency tracking loop and a PLL are integrated, and locks a frequency first and then locks a phase when the frequency is locked.

The analog / digital (A / D) converting section 33 converts the I signal of the FPLL section 32 into 10-bit digital data. Here, the Q signal is used only for carrier recovery. The synchronization recovery unit 34 restores the horizontal synchronization signal, the vertical synchronization signal, and the like, which were inserted at the time of transmission using the digitally converted 10-bit data for use in timing recovery. These synchronization signals are designed to facilitate the recovery of the received data. When they are detected incorrectly, the recovery of the data is not performed properly, which greatly affects the whole system.

The equalization and error correction unit 35 uses horizontal and vertical synchronization signals restored by the synchronization recovery unit 34 as a training signal to detect linear distortion of amplitude causing interference between symbols and ghosts generated by reflections from buildings or mountains. After correcting equalization, the error generated through the transmission channel is corrected. The video decoder 36 decodes the equalized and error corrected signal using an MPEG algorithm to make the signal visible to the viewer.

In this case, the synchronization recovery unit 34 receives the 10-bit digital data output from the A / D conversion unit 33 and detects the vertical synchronization signal, so that the circuit configuration becomes very complicated, and the number of gates when ICization is geometrical To increase. This leads to an increase in price with an increase in IC size.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a vertical synchronization signal detection apparatus of a digital TV that detects a vertical synchronization signal using only code bits of input digital data.

Another object of the present invention is to provide a vertical synchronization signal detection apparatus of a digital TV that detects a vertical synchronization signal using the PN 511.

It is still another object of the present invention to provide a vertical synchronization signal detection apparatus of a digital TV that generates a signal indicating an even / odd field by determining the polarity of the second PN 63 of the vertical synchronization signal.

According to an aspect of the present invention, there is provided an apparatus for detecting a vertical synchronization signal of a digital TV, comprising: a code bit extraction unit for extracting only the most significant bit having code information from input data; A reference signal generator for generating PN 511 and PN 63 signals as a reference signal among the vertical synchronization signals of the same pattern as that inserted at the side; A comparison process is performed for every data segment, and a F_Sync signal indicating a vertical sync interval is generated by judging a data segment that is determined to be the same for both signals for 511 symbols as a vertical sync signal interval. The sign bit of the second PN 63 input to each synchronization section and the reference signal generator; Compare for 63 symbol PN 63 the pattern of occurrence based on the vertical synchronizing signal in symbol units, characterized by a comparison part configured to generate a signal indicative of the Foe even / odd field.

The comparison unit compares a sign bit of each data output from the sign bit extracting unit with a reference vertical sync pattern value generated by the reference signal generator in symbol units and counts the result by one data segment. And a segment error unit for comparing the counted value with a reference value, and a confidence counter for checking the reliability of the output of the segment error unit and generating an F_Sync signal indicating a vertical sync interval when the reliability is higher than a certain threshold. do.

The segment error unit is a first comparator for comparing the input code bit and the reference vertical synchronization signal in symbol units, and resets every data segment, and when the first comparator outputs a signal indicating that the two inputs are the same, the count value remains the previous value. An error counter that performs one data segment for increasing the count value by one step each time it maintains and outputs a signal that two inputs are wrong, and stores the output value of the error counter only when an enable signal is input. The memory unit outputs the reference value, the count value output from the error counter and the size of the reference value output from the memory unit, and outputs the result to the confidence counter. The count value of the error counter is the reference value. A second comparison for outputting an enable signal to the storage unit if it is determined to be less than or equal to Characterized by consisting of a.

The storage unit is preset to the largest value once every 313 data segments under the control of the confidence counter.

The confidence counter has a 313 counter that increments by 1 for each data segment and counts from 0 to 312, so that the 313 counter is zero whenever the second comparator indicates that the output of the error counter is less than or equal to the reference value. When the reliability is increased at the same time as the forced reset, but the reliability is higher than a certain threshold value, the 313 counter is not forced reset anymore, and an F_Sync signal is generated indicating the vertical synchronization signal interval in the data segment interval in which the 313 counter becomes zero. It is done.

Another characteristic of the segment error unit includes: a first comparator comparing whether an input code bit is equal to or not a reference vertical sync signal; a count is reset every data segment and each time the first comparator outputs a signal indicating that the two inputs are the same; When increasing the value by one step and outputting a signal that the two inputs are wrong, the count value is a correlation counter that performs the process of maintaining the previous value by one data segment, and the output of the correlation counter only when the enable signal is input. A storage unit for storing a value and outputting the value as a reference value, a count value output from the correlation counter and a magnitude value of the reference value output from the storage unit, and outputting the result to the confidence counter, If it is determined that the count value is larger than the reference value, an enable signal is output to the storage unit. The can consists of two comparators.

Another characteristic of the comparator includes: a first comparator for comparing a PN 63 pattern value of the second PN 63 and a PN 63 pattern value among the reference vertical sync signals of the input vertical sync signal with a symbol unit; When the PN 63 is reset every time the PN 63 is started and the first comparator outputs a signal indicating that the two inputs are the same, the count value remains the previous value and the count value is increased by one step each time the two inputs are output. An error counter for 63 symbols, a storage unit for storing the output value of the error counter of the previous vertical synchronization section by the enable signal and outputting it as a reference value, the count value and the memory output from the error counter. A third comparator comparing the magnitude of the reference value output from the negative part, and confidence in the output of the third comparator It examines the reliability may consist of a confidence counter for generating a signal indicative of the Foe even / odd number field if the certain threshold or more.

1 is a view showing the structure of a data frame of a general digital TV

FIG. 2 is a diagram illustrating a structure of a vertical synchronization signal of FIG. 1.

3 is a block diagram of a general digital TV receiver

4 is a conceptual diagram of a vertical synchronization signal detection apparatus of a digital TV according to the present invention.

5 is a detailed block diagram of a vertical synchronization signal detection apparatus of a digital TV according to the present invention.

FIG. 6 is a detailed block diagram of a reference vertical synchronization signal generator of FIG. 5. FIG.

7 is a detailed block diagram of a segment error unit of FIG. 5.

FIG. 8 is a detailed block diagram illustrating another embodiment of the segment error unit of FIG. 7. FIG.

Explanation of symbols for the main parts of the drawings

41, 51: code bit extractor 42: reference signal generator

43: comparator 52: reference vertical synchronization signal generator

53: segment error section 54,55: confidence counter

61: F 511 generator 62: F 63 generator

63: multiplexer 71,75,78: comparator

73: error counter 74,77: storage unit

Hereinafter, the embodiment of the present invention will be further described with reference to the features of the present invention.

The present invention generates a F_Sync signal, which is a signal representing a vertical sync signal section, by detecting a vertical sync signal using only code bits among 10-bit digital data, and detects an even / odd field by detecting an even / odd field when a vertical sync signal is detected. Generate a Foe signal, which is a signal that represents. To this end, first, the PN 511 is used to detect the F_Sync signal, and the second PN 63 is used to detect the Foe signal. In addition, the algorithm used to detect the F_Sync detects the data segment having the least error, and after detecting the F_Sync, determines the polarity of the second PN 63 to generate a Foe signal.

The conceptual diagram of the vertical synchronization signal detection apparatus of the digital TV according to the present invention for realizing this is shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a conceptual diagram of a vertical synchronization signal detection apparatus of a digital TV according to the present invention. When 10-bit digital data is input, a code bit extracting unit 41 extracting only the most significant bit having code information, inserted by the transmitter. A reference signal generator 42 for generating a pattern of a known vertical synchronizing signal and outputting it as a reference signal using a generation polynomial such as the above, and the output of the sign bit extractor 41 and the reference signal generator 42 Comparator for comparing outputs for 511 symbols in symbol units for each data segment, and generating a F_Sync signal indicating a vertical sync interval by judging a data segment whose two input signals are the same for 511 symbols as a vertical sync signal section. It consists of 43.

FIG. 5 is a block diagram of FIG. 4. The pattern bit extracting unit 51, a horizontal sync signal (Seg Sync), and a horizontal sync signal lock signal (Seg Lock) are used to show a pattern of a known vertical sync signal. Data segments in which the reference vertical sync signal generator 52, the output of the code bit extracting unit 51, and the PN 511 pattern and PN 63 pattern generated by the reference vertical sync signal generator 52 are generated in units of symbols The first error counter 54 for generating an F_Sync signal by checking the reliability of the comparison result of the segment error unit 53, the comparison result of the PN 511 pattern of the segment error unit 53, and the segment error unit 53. The second confidence counter 55 generates a Foe signal by checking the reliability of the comparison result of the PN 63 pattern.

As illustrated in FIG. 6, the reference vertical synchronization signal generator 52 generates a generated polynomial equation such as inserted by a transmitter when an input horizontal sync signal and a horizontal lock signal Seg Lock are input. The F 511 generator 61 and the F 511 generator 61 to generate the PN 511 pattern, the F 63 generator 62 to generate the PN 63 pattern, and the PN 511 and PN 63 to be arranged in this order. The multiplexer 63 selects an output of the 63 generator 62, and a flip-flop 64 that performs timing alignment with respect to the output of the multiplexer 63.

As shown in FIG. 7, the segment error unit 53 determines whether the code bit extracted by the code bit extracting unit 51 and the vertical synchronizing signal generated by the reference vertical synchronizing signal generating unit 52 are the same. A comparator 71 for comparing the data, a flip-flop 72 performing timing alignment with respect to the output of the comparator 72, an error that is reset every data segment and increases a count value according to the output of the flip-flop 72. A memory unit which is preset to the largest value once every 313 data segments under the control of the counter 73 and the first confidence counter 54, and stores the output of the error counter 73 only when an enable signal is input. (74), when the output of the error counter 73 is compared with the magnitude of the output of the storage unit 74, and it is determined that the output of the error counter 73 is smaller than or equal to the output value of the storage unit 74, the storage unit; 74 Roy Comparator 75 for outputting a signal, flip-flop 76 for outputting to the confidence counter 34 after timing alignment of the output of the comparator 75, the output of the error counter of the previous field by the enable signal A flip-flop type storage unit 77 for storing the data, a comparator 78 for comparing the magnitude of the output of the error counter 73 and the output of the storage unit 77, and an output of the comparator 79 It consists of a flip-flop 79 that performs timing alignment.

The present invention thus configured uses only the code component of the received signal for the detection of the vertical synchronization signal. Since the start point of every data segment can be known only after the horizontal synchronization signal is detected, normal operation is performed after the horizontal synchronization signal is detected. That is, the starting point of every data segment can be known from the horizontal sync signal (Seg Sync). In addition, since the pattern of the vertical synchronization signal inserted at the transmitting side is already known, the reference vertical synchronization signal generator 52 generates a vertical synchronization signal to be a reference by using the same generation polynomial as that inserted at the transmitting side.

That is, when 10 bits of digital data Din [9: 0] are input, the sign bit extracting unit 51 extracts only the most significant bit having the sign information and outputs it to the segment error unit 53.

When the horizontal sync signal (Seg Sync) and the horizontal sync lock signal (Seg Lock) are input, the F 511 generator 61 of the reference vertical sync signal generator 52 performs a promise after the horizontal sync signal (Seg Sync). A PN 511 signal having the same pattern as that inserted at the transmitting side with the polynomial of the form is generated, and the F 63 generator 62 generates a PN 63 signal. 3, the multiplexer 63 sequentially selects PN 511 of the F 511 generator 61 and PN 63 of the F 63 generator 62, and then performs a timing on the flip-flop 64. The alignment is output to the segment error unit 53. Here, the horizontal lock signal Seg Lock is a signal indicating that the horizontal sync signal Seg Sync has been found.

As shown in FIG. 7, the segment error unit 53 receives a comparator when the code bit of the data extracted by the code bit extracting unit 51 and the PN 511 signal generated by the reference vertical synchronization signal generating unit 52 are input. 71 compares two signals in symbol units. The comparator 71 outputs '0' when the two signals are the same and '1' when the two signals are different to the error counter 73 through the flip-flop 72.

The error counter 73 should be reset every line, i.e., every data segment. The error counter 73 can be reset by the first confidence counter 54 or externally, and can be reset during the horizontal synchronization signal period. Therefore, the error counter 73 increments the count value according to the signal input by one data segment. If the output of the comparator 71 is '0', that is, the two inputs are the same, the count value remains the previous value. If the output is '1', that is, the two inputs are different, the count value is increased by one step. After the counting process is performed for one data segment, that is, for 511 symbols, the error counter 73 outputs the counted value. At this time, if the compared data segment is a vertical synchronization signal interval, the output count value has a small value, and if the normal data interval has a large value. The output of the error counter 73 is compared with a reference value at the comparator 75. The comparator 75 outputs '1' if the output of the error counter 73 is less than or equal to the reference value, and if it is large, '0'. Output '

In the storage unit 74 which provides the reference value to the comparator 75, the highest value is initially stored. In addition, the storage unit 74 is preset to the highest value under the control of the first confidence counter 54 once every 313 data segments. The reference value is changed by using the output of the comparator 75 as an enable signal. That is, when the output of the comparator 75 is '1', the storage unit 74 changes the stored reference value to the output value of the current error counter 73, and when the output of the comparator 75 is '0', the stored reference value is stored. Leave the reference value unchanged.

For example, if 255 is stored in the memory 74 and the output of the error counter 73 is 100, the comparator 75 has a value of '1' because the output of the error counter 73 is smaller than the reference value (= 255). The memory unit 74 stores the value '100' output from the error counter 73 because '1' is output from the comparator 75. That is, the reference value stored in the storage unit 74 is changed to 100. If the output of the error counter 73 is 101 in the next data segment, the comparator 75 outputs '0' because the output of the error counter 73 is greater than the reference value (= 100), and the memory 74 compares the comparator. Since '0' is output at 75, the previously stored '100' is kept as it is. If the output of the error counter 73 in the next data segment is 90, the comparator 75 outputs '1' because the output of the error counter 73 is less than the reference value (= 100) and the memory 74 compares the comparator. Since '1' is output at 75, the value '90' output from the error counter 73 is stored. When the above process is performed for each data segment and becomes a data segment with a vertical synchronization signal, the output of the error counter 73 becomes '0' and also the storage unit 74 by the enable signal output from the comparator 75. '0' is stored. Thereafter, since the output value of the error counter 73 is not smaller than zero until the data segment of the next vertical sync signal comes, the output of the comparator 75 becomes '0' until the data segment of the next vertical sync signal comes. . Thus, after the 313 data segment has progressed, the position at which the last '1' of the comparator 75 is generated is in the data segment with the vertical sync signal. Subsequently, the output of the comparator 75 becomes '1' only in the data segment section in which the vertical synchronization signal is present.

Meanwhile, the output of the comparator 75 is timing-aligned in the flip-flop 76 and then output to the first confidence counter 54. The first confidence counter 54 checks the reliability of the output of the flip-flop 76 to determine the data segment having the smallest segment error value among the input signals as the vertical synchronization signal section, and during the data segment section. Generates an F_Sync signal.

The first confidence counter 54 has a 313 counter that counts from 0 to 312 by incrementing 1 for each data segment, for example, when a horizontal synchronization signal is input. The first confidence counter 54 has a 313 counter. Controls to reset to zero in the data segment with the vertical sync signal. That is, when the power is turned on for the first time or when the channel is changed, the vertical synchronization section is not known. When the output of the comparator 75 becomes '1', the 313 counter is forcibly reset to zero. When this process is performed for a predetermined time, the comparator 75 outputs '1' only in the data segment section in which the vertical synchronization signal is present, and the count value of the 313 counter is also zero in the data segment section. That is, the interval at which the output of the comparator 75 becomes '1' is changed to the vertical synchronization section. Accordingly, the F_Sync signal may be generated in a section in which the count value of the 313 counter becomes zero. From this point on, the 313 counter is no longer forcibly reset.

To this end, first, the first confidence counter 54 checks the reliability. That is, if the count value of the 313 counter is 0 and the output of the comparator 75 is 1, the first confidence counter 54 increases the reliability by one step, and the count value of the 313 counter is 0 and the count of the comparator 75 is zero. A zero output decreases the reliability by one step. Here, the case where the count value of the 313 counter is 0 and the output of the comparator 75 is 0 corresponds to a case where a lot of initial or error occurs.

The first confidence counter 54 continues the process described above and does not reset the 313 counter any more when the reliability is above a certain threshold. In this case, since the data segment having the count value of the 313 counter is 0 is an accurate vertical synchronization signal section, the output of the comparator 75 becomes '1' due to an error in the data segment that is not the vertical synchronization signal, thereby preventing the 313 counter from being reset. For that.

Therefore, when the reliability is above a certain threshold value, since the count value of the 313 counter becomes 0 in the correct vertical synchronization signal, the F_Sync signal is generated in a section in which the count value of the 313 counter becomes 0 without forcibly resetting it.

In addition, the first confidence counter 54 presets 255 to the storage unit 74 when the count value of the 313 counter becomes 0, for example, a maximum value, for example, 8 bits of precision.

When the F_Sync signal is generated through the first confidence counter 54, the segment error unit 53 generates information about the Foe, that is, information about an even / odd field. That is, information about F_Sync is obtained using only the PN 511 signal among the vertical synchronization signals, and information about Foe uses the second PN 63 whose polarity is inverted in every field among three PN 63.

To this end, the error counter 73 is reset once more after the end of PN 511. That is, the error counter 73 may be reset at the position where the second PN 63 section starts. In this case, the comparator 71 compares the sign bit of the input data with the PN 63 signal generated by the reference vertical synchronization signal generator 52 in symbol units and compares the result with an error counter 73 through the flip-flop 72. ) Similarly, the comparator 71 outputs '0' if the two inputs are the same and '1' if the inputs are different, and the error counter 73 outputs the previous value if the output of the comparator 71 is '0'. Keep it as it is. If it is '1', the count value is increased by one step.

After the counting process is performed for 63 symbols, the error counter 73 outputs the counted value. At this time, since the polarity of the second PN 63 is changed every field, the output of the error counter 73 becomes 0 or 63 in the vertical synchronization signal section. Here, if the output of the error counter 73 is 0, the polarity of the second PN 63 has the same polarity as that of the first and third PN 63, and if it is 63, the polarity is inverted. The output of the error counter 73 is input to the comparator 78 and compared with a reference value. At this time, the comparator 75 does not operate.

The comparator 78 outputs '1' if the output of the error counter 73 is smaller than the reference value, and outputs '0' if the output of the error counter 73 is smaller than the reference value. The output of the comparator 78 is timing aligned in the flip flop 79 and then output to the second confidence counter 55. At this time, the storage unit 77 which provides the reference value to the comparator 78 always stores the output value of the error counter 73 of the previous field. The storage unit 77 stores the output of the error counter 73 only when the enable signal is input, which is provided by the first confidence counter 54. When all the systems are reset by turning on the power, the memory 77 is also reset to zero. Therefore, initially, the output of the error counter 73 and the reference value 0 are compared in the comparator 78.

If the output of the error counter 73 is zero in the initial state, the comparator 78 outputs zero. When the output of the error counter 73 reaches 63 in the next vertical synchronization signal section, the comparator 78 outputs '0' because the output value of the previous error counter, that is, 0, is stored in the memory 77. When the output of the error counter 73 becomes zero in the next vertical synchronization signal section, since the output value of the previous error counter, that is, 63 is stored in the memory 77, the comparator 78 outputs '1'. In the next vertical sync signal section, the comparator 78 outputs '0' again. In this way, the output of the comparator 78 repeats 0 and 1 for every vertical synchronization signal section. In this case, when the output of the comparator 78 is '0', the polarity of the second PN 63 is inverted, and if it is '1', the polarity is not inverted.

In the present invention, if a field having no changed polarity is an odd field and a field having changed polarity is an even field, it is determined that an odd field is output when '1' is output from the flip-flop 79, and an even field is output when a '0' is output. You can judge.

If an inverter is connected to the flip-flop 79, it is determined that an odd field is output when '0' is output and an even field when '1' is output.

In this case, the second confidence counter 55 operates by receiving an enable signal from the first confidence counter 54. Here, the second PN 63 of the vertical synchronization signal is normal when the polarity is changed in every field. Therefore, the second confidence counter 55 checks the reliability of '1' or '0' output from the segment error unit 53 and increases or decreases the reliability. Generate and output a Foe signal indicating.

Meanwhile, FIG. 8 is another embodiment of the segment error unit of the present invention. In FIG. 7, if the vertical sync interval is found by comparing the difference between the sign bit and the reference signal, FIG. 8 compares how the sign bit and the reference signal are the same. To find the vertical sync interval.

That is, when the sign bit of the data extracted by the sign bit extracting unit 51 and the PN 511 signal generated by the reference vertical sync signal generating unit 52 are input, the comparator 81 compares whether the two signals are the same in units of symbols. . The comparator 81 outputs '1' if the two signals are the same and '0' if the two signals are different to the correlation counter 83 through the flip-flop 82. The correlation counter 83 increments the count value by one only when the two inputs of the comparator 81 are the same. That is, if the output of the comparator 81 is '1', that is, if the two inputs are the same, the count value is increased by one step. If '0', that is, if the two inputs are different, the count value keeps the previous value.

Similarly, the correlation counter 83 should be reset every line, i.e., every data segment. The correlation counter 83 can be reset by the first confidence counter 54 or externally. do. Therefore, the correlation counter 83 increments the count value according to the signal input by one data segment.

After the counting process is performed for one data segment, that is, for 511 symbols, the correlation counter 83 outputs the counted value. At this time, if the data segment to be compared is a period of the vertical synchronization signal, the output count value has a large value, and if it is a general data period, it has a small value. The output of the correlation counter 83 is compared with the reference value at the comparator 85. The comparator 85 outputs' 1 'if the output of the correlation counter 83 is greater than or equal to the reference value, and if the output is smaller than' Output 0 '.

In the storage unit 84 that provides the reference value to the comparator 85, the minimum value is initially stored. The storage unit 84 is also reset to the minimum value by the control of the first confidence counter 54 once for every 313 data segments. The reference value is changed by using the output of the comparator 85 as an enable signal. That is, if the output of the comparator 85 is '1', the storage unit 84 changes the stored reference value to the output value of the current correlation counter 83, and if the output of the comparator 85 is '0', the stored reference value is stored. The reference value is left unchanged.

Since the subsequent operation is performed by the same process as in FIG. 7, the description thereof is omitted.

As described above, according to the vertical synchronizing signal detecting apparatus of the digital TV according to the present invention, the circuit configuration is simplified by detecting the vertical synchronizing signal using only the most significant bit having the sign information among the input digital data. The number of sea gates can be reduced by about one-third, which facilitates integration and reduces IC size, resulting in lower cost.

In addition, after detecting the vertical synchronization signal, part of the vertical synchronization signal detection circuit is shared to determine the polarity of the second PN 63 among the vertical synchronization signals, and according to the determination result, the Foe signal indicating the even / odd field is generated, thereby detecting the Foe signal detection. It is easy and has the effect of simplifying the hardware.

Claims (20)

In the apparatus for detecting the vertical synchronization signal inserted every 313 data segments at the transmitting side, A sign bit extraction unit for extracting only the most significant bit having sign information from the input data; A reference signal generator for generating a reference vertical synchronization signal of the same pattern as that inserted at the transmitting side whenever a horizontal synchronization signal is input; A process of comparing the output of the code bit extracting unit and the output of the reference signal generating unit for a predetermined symbol for each data segment to determine that the data segment for which the two signals are the same during the predetermined symbol is a vertical synchronization signal section. Digital TV vertical synchronization signal detection apparatus, characterized in that consisting of. The method of claim 1, wherein the reference signal generator is Whenever the horizontal synchronization signal is input, a digital TV vertical synchronization signal is detected and generated as a reference signal by generating a pattern of the PN 511 and PN 63 of the vertical synchronization signal using a generated polynomial such as inserted by the transmitter. Device. The method of claim 1, wherein the comparison unit A value obtained after comparing the sign bit of each data output from the sign bit extracting unit with the reference vertical sync pattern value generated by the reference signal generator in units of symbols and counting the result by one data segment A segment error section for comparing the to a reference value, And a confidence counter that checks the reliability of the output of the segment error unit and generates an F_Sync signal indicating a vertical synchronization section when the reliability is equal to or greater than a certain threshold value. The method of claim 3, wherein the segment error unit A first comparator for comparing an input code bit and a reference vertical synchronization signal in symbol units, If the first comparator outputs a signal indicating that the two inputs are the same, the count value remains the previous value and increases the count value by one step each time the signal indicates that the two inputs are different. Error counters, A storage unit for storing the output value of the error counter and outputting the output value as a reference value only when an enable signal is input; Compare the count value output from the error counter with the reference value output from the memory, output the result to the confidence counter, and if it is determined that the count value of the error counter is less than or equal to the reference value, And a second comparator for outputting an enable signal. The method of claim 4, wherein the first comparator And an input code bit is compared with a PN 511 pattern value among the reference vertical sync signals. The method of claim 4, wherein the error counter And a vertical synchronization signal detection device for a digital TV, characterized in that reset during the horizontal synchronization signal interval of every data segment. The method of claim 4, wherein the error counter The first comparator continues counting until the comparison of the PN 511 pattern of the reference vertical synchronization signal is finished, and outputs the result of the digital TV, it is reset device. The method of claim 4, wherein the memory unit And a preset value for the digital TV, characterized in that the preset value is preset once every 313 data segments by the control of the confidence counter. The method of claim 3, wherein the confidence counter is A 313 counter that increments by 1 for each data segment and counts from 0 to 312, forcing the 313 counter to reset to zero whenever the second comparator indicates that the output of the error counter is less than or equal to the reference value; At the same time, when the reliability is increased and the reliability is above a certain threshold, the digital TV is generated, indicating that the vertical sync signal is generated in the data segment section in which the 313 counter becomes zero, without forcing the 313 counter any more. Vertical synchronization signal detection device. The method of claim 3, wherein the segment error unit A first comparator for comparing whether an input code bit is equal to a reference vertical synchronization signal; When the first comparator outputs a signal that the two inputs are the same, the count value is increased by one step, and when the first input comparator outputs a signal that the two inputs are wrong, the count value is maintained as it is. A correlation counter for each data segment, A storage unit which stores an output value of the correlation counter only when an enable signal is input and outputs the output value as a reference value; Compare the count value output from the correlation counter with the reference value output from the memory, output the result to the confidence counter, and if it is determined that the count value of the correlation counter is greater than or equal to the reference value, And a second comparator for outputting an enable signal. The method of claim 10, wherein the first comparator And an input code bit is compared with a PN 511 pattern value among the reference vertical sync signals. 11. The method of claim 10 wherein the correlation counter And a vertical synchronization signal detection device for a digital TV, characterized in that reset during the horizontal synchronization signal interval of every data segment. 11. The method of claim 10 wherein the correlation counter The first comparator continues counting until the comparison of the PN 511 pattern of the reference vertical synchronization signal is finished, and outputs the result of the digital TV, it is reset device. The method of claim 10, wherein the memory unit And a vertical reset signal detection unit for every 313 data segments under control of the confidence counter. The method of claim 9, wherein the confidence counter is Each data segment has a 313 counter that increments by 1 and counts from 0 to 312. When the second comparator indicates that the output of the correlation counter is greater than the reference value, the 313 counter is forced to reset to 0 and reliability is increased. When increasing the reliability above a certain threshold, the digital TV's vertical sync is generated by indicating that the 313 counter is a vertical sync signal section in the data segment section where the 313 counter becomes 0 without forcing the reset of the 313 counter any more. Signal detection device. The method of claim 1, wherein the comparison unit When the vertical sync signal is detected, the even / odd field is compared by comparing the sign bit of the second PN 63 inputted every vertical sync interval with the PN 63 pattern of the reference vertical sync signal generated by the reference signal generator for 63 symbols in symbol units. And generating a Foe signal representing the digital TV. The method of claim 16, wherein the comparison unit A first comparator for comparing whether a sign bit of the second PN 63 of the input vertical synchronization signal and a PN 63 pattern value among the reference vertical synchronization signals are equal, in symbol units; When the second PN 63 of the vertical sync signal section is reset, the first comparator outputs a signal indicating that the two inputs are the same, and the count value remains the previous value and counts each time the two inputs are wrong. An error counter that increases the value by one step for 63 symbols; The memory unit always stores the output value of the error counter of the previous vertical synchronization section and outputs it as a reference value. A third comparator for comparing a magnitude of a count value output from the error counter with a reference value output from the storage unit; And a confidence counter that checks the reliability of the output of the third comparator and generates a Foe signal indicating an even / odd field when the reliability is equal to or greater than a certain threshold value. When a high frequency (RF) signal is received through an antenna, a tuner selects a frequency of a desired channel by tuning and converts it into an intermediate frequency (IF) signal. An analog / digital conversion unit for demodulating the IF signal output from the tuner into I and Q signals of a baseband, locking the frequency and phase, and converting the IF signal into a digital signal of a predetermined bit; A horizontal sync signal detector for detecting a horizontal sync signal inserted into every data segment from the digital data output from the analog / digital converter; A code bit extraction unit for extracting only the most significant bit having code information from the digital data output from the analog / digital conversion unit; A reference signal generator for generating a reference vertical synchronization signal of the same pattern as that inserted at the transmission side whenever the horizontal synchronization signal is input; A process of comparing the output of the code bit extractor and the output of the reference signal generator for a predetermined symbol for each data segment to determine that the data segment for which the two signals are the same during the predetermined symbol is a vertical synchronization signal section. Wealth, A digital data decoding unit for decoding data output from the analog / digital conversion unit by using the detected horizontal and vertical synchronization signals; And a display unit for displaying the decoded data. The method of claim 18, wherein the comparison unit A first comparator for comparing the PN 511 pattern value of the code bits output from the code bit extracting unit with the reference vertical synchronization signal generated from the reference signal generator in symbol units; If the first comparator outputs a signal indicating that the two inputs are the same, the count value remains the previous value and the count value is increased by one step each time the two input signals are incorrect. An error counter that performs segment by segment, A storage unit for storing the output value of the error counter and outputting the output value as a reference value only when an enable signal is input; A second comparator configured to compare the count value output from the error counter with the magnitude of the reference value output from the storage unit and to output an enable signal to the storage unit when it is determined that the count value of the error counter is less than or equal to the reference value; And a confidence counter that checks the reliability of the output of the second comparator and generates an F_Sync signal indicating a vertical sync interval when the reliability is equal to or greater than a certain threshold value. The method of claim 18, wherein the comparison unit A first comparator for comparing, in symbol units, the PN 63 pattern of the reference vertical synchronization signal generated by the reference signal generator and the sign bit of the second PN 63 input every vertical synchronization interval when a vertical synchronization signal is detected; When the second PN 63 of the vertical sync signal section is reset, the first comparator outputs a signal indicating that the two inputs are the same, and the count value remains the previous value and counts each time the two inputs are wrong. An error counter that increases the value by one step for 63 symbols; The memory unit always stores the output value of the error counter of the previous field and outputs it as a reference value. A third comparator for comparing a magnitude of a count value output from the error counter with a reference value output from the storage unit; And a confidence counter that checks the reliability of the output of the third comparator and generates a Foe signal indicating an even / odd field when the reliability is equal to or greater than a certain threshold value.