KR19990049645A - Signal Restoration Circuit Using Differential Code - Google Patents

Abstract

The present invention relates to a signal recovery circuit using a differential code that can recover a data signal to be transmitted using a differential code, which is one of codes used in wireless communication, to the same data signal with minimized error. Input the same frequency generated by the reference clock generator and the reference clock generator to generate the reference frequency (f0) and twice the reference frequency (2f0) by dividing the input frequency and the edge detector used to clear the counter that makes the clock. A code generator for generating a new differential code that is half frequency received and doubled with a receive request signal (DCD) processing unit that clears the counter when transmitting a receive request signal (DCD) and clears the counter when receiving. Sampling sync to create a new reference frequency (f'0) generated from JK F / F using the reference frequency of It consists of a sampling unit for sampling the reference frequency (f0) generated by the clock generator and the reference clock generator and the new reference frequency (f'0) generated by the sampling sync clock generator to output a signal matching the input signal. In addition, the edge of the received data is detected to correct the temporal error and recover the same data as the transmitted data, thereby having an effect of transmitting stable data without errors.

Description

Signal Restoration Circuit Using Differential Code

The present invention relates to a signal recovery circuit using a differential code, and more particularly, to recover a data signal to be transmitted using a differential code, which is one of codes used in wireless communication, to the same data signal with minimal error. The present invention relates to a signal recovery circuit using a differential code.

When sampling message signals, sampling faster than the Nyquist rate results in higher correlation between adjacent samples. This fact means that if the sample is encoded using the standard PCM method, the resulting encoded signal will contain excess information.

This means that the over-signal assignment resulting from the encoding of the common signal part with little change, and the signal part which is not essential for information transmission, is encoded. More efficient encoding is obtained by removing this excess information before encoding. In other words, by only encoding the difference between adjacent sample pulses, such unnecessary information can be eliminated and efficiency can be expected by quantizing and encoding only the difference between samples having a high correlation.

In this way, it is possible to deduce the magnitude of the signal to be changed in the future if the signal amplitude is changed by a certain time. This process is called prediction, and a method of modulating a sample signal using such a prediction method is differential code modulation (DPCM). Adaptive delta modulation or adaptive differential code modulation are also included in this scheme.

Pulse phase modulation and demodulation are mainly used to transfer data over a single wire between digital systems, and the present invention relates to differential codes.

The operation of the differential code is described with reference to FIG. 1 as follows.

As shown in FIG. 1, the configuration diagram of the differential code is assumed on the assumption that the data signal transmitted from the transmission line is " 111 ".

Zero is represented at the same frequency as the synchronous clock (i.e. twice the baud rate), with the waveform leading from high to low if the leading edge was zero and from low to high if it was leading one.

1 is represented by the half frequency (same baud rate) of the synchronous clock. Like 0, the waveform is expressed as high when the leading edge is 0, and when the leading edge is 1, only the level changes to low.

In other words, when it is 0, the same frequency is output, and when it is 1, only half frequency is output and it is alternately complemented.

In the conventional signal restoration circuit, the received data enters together with the reception request signal, which is a single pulse made by the RF module. However, since it is not a synchronized pulse train, it only serves to indicate the start of the reception data. It has no choice but to accept and process a series of pulse trains. That is, even if the receiving end has made the correct synchronization frequency, this is a separate pulse from the transmitting end, which causes a problem that an error is generated after a certain time.

Accordingly, the present invention has been made to solve such a problem, and an object of the present invention is to detect the edge of the received data, to correct the temporal error, to restore the same data as the transmitted data, and to transmit the differential data without error. It is to provide a signal recovery circuit using a code.

In order to achieve the above object, the present invention provides a signal recovery circuit for decoding a received code signal by receiving a code signal for use in wireless communication and restoring a signal corresponding to the received original code signal. By exclusively ORing the waveform integrating the input signal, the pulse corresponding to the time constant of the integrator is generated at the edge of the input signal, and the edge detector and the input frequency are used to clear the counter that makes the synchronous clock of the receiver. f0) and the reference clock generator that generates twice the reference frequency (2f0) and the frequency generated by the reference clock generator alternately switching to 0 if the input is twice the frequency and 1 if the same frequency The counter is cleared when a code generator and a receive request signal (DCD) are transmitted to generate a new differential code that is half frequency. A reception request signal (DCD) processing unit for clearing a counter when receiving, and a sampling synchronization clock generation unit for generating a new reference frequency (f'0) generated by JK F / F using a double reference frequency; And a sampling unit configured to sample a reference frequency f0 generated by the reference clock generator and a new reference frequency f'0 generated by the sampling sync clock generator to output a signal matching the input signal. .

1 is a configuration diagram of a differential code.

2 is a circuit diagram showing the configuration of a signal recovery circuit using a differential code according to the present invention.

3 is a timing diagram of a signal recovery circuit using a differential code according to the present invention;

<Explanation of symbols for main parts of the drawings>

10: edge detector 20: reference clock generator

30: code generation unit 40: reception request signal processing unit

50: sampling synchronization clock generating unit 60: sampling unit

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram showing the overall configuration of a signal recovery circuit using a differential code according to the present invention.

As shown in FIG. 2, the present invention provides an edge detector 10, a reference clock generator 20, a code generator 30, a reception request signal (DCD) processor 40, and a sampling synchronization clock generator 50. ) And the sampling unit 60.

The edge detector 10 includes an inverter 15 for inverting an input signal, an inverter 16 for inverting an inverted signal, an integrator 17 and an integrator 17 including a resistor R1 and a capacitor C1. An inverter 18 for inverting the signal passed through and an exclusive oragate 19 for exclusively ORing the output signal of the inverter 15 and the output signal of the inverter 18 are constituted.

The reference clock generator 20 receives a high reference frequency as the clock terminal (terminal 1) of the binary counter 21 and receives the output of the QD terminal (terminal 6) as the clock terminal (terminal 13). The terminal 10 includes a binary counter 22 that outputs twice the reference frequency 2f0 and the QC terminal 9 outputs the reference frequency f0.

The code generator 30 is connected to an input terminal of the inverter 31 for inverting the output data and the reference frequency f0 output from the QC terminal (terminal 9) of the binary counter 22 to the input terminal. The 3-state buffer 32 is connected to the output of the buffer and the reference frequency 2f0, which is output from the QB terminal (terminal 10) of the binary counter 22, is connected to the input and output data (TxD). ) Is connected to the buffer stage, and the pull-up and pull-down resistors R2 and R3 and the 3-state buffer to maintain a constant level when the 3-state buffer 33 and the 3-state buffer 32 and 33 are opened. JK F / F 34 for connecting the output signals of 32 and 33 to the clock terminal (terminal 1) and generating a new code of half frequency.

The reception request signal processing unit 40 logically multiplies the inverter 41 for inverting the reception request signal, the output signal of the inverter 41 and the output signal of the edge detector 10, and the output value thereof is the binary counter 21. And an end gate 42 connected to the clear terminal (terminals 2 and 12).

The sampling synchronization clock generation unit 50 passes through the inverter 51 for inverting the reference frequency f 0 output from the QC terminal (terminal 9) of the binary counter 22 and the output waveform passing through the inverter 51. The inverter 52 for converting the integrated waveform while passing through the silver resistor R4 and the capacitor C3 and inverting the converted integral waveform is connected to the clear terminal (terminal 6). JK F / for generating the reference frequency f0 by connecting a double reference frequency 2f0 output from the QB terminal (terminal 10) of the binary counter 22 to a clock terminal (terminal 5). It consists of F53.

The sampling unit 60 includes an AND gate 61 for logically multiplying the reference frequency f0 and the serial clock SCK output from the binary counter 22, a resistor R5 and a capacitor C4 for delaying the phase. Pass the integrator consisting of the delayed signal to the D terminal (terminal 2), and the waveform output from the JK F / F (53) is connected to the clock terminal (terminal 3) to generate a recovered signal It consists of DF / F62.

Hereinafter, the overall operation of the present invention having the above-described configuration will be described in detail with reference to FIG.

3 is a timing diagram of a signal recovery circuit using a differential code according to the present invention.

As illustrated in FIG. 3, it is assumed that data TXD to be transmitted is " 11001110100 " for explaining the operation of the present invention.

The binary counter 21 divides the frequency of 128 x f0 applied to the clock terminal to produce a synchronization frequency of 2f0 and f0. The higher this input frequency (128 × f0), the higher the accuracy of the system and the less the error.

The data TXD to be transmitted is inverted to " 00110001011 " while passing through the inverter 31 and input to the buffer terminal of the 3-state buffer 32 (b waveform). TXD is also connected to the input of the 3-state buffer 13.

The 2f0 divided by the binary counter 22 is extracted from the QB terminal (terminal 10) and connected to the input terminal of the 3-state buffer 33 (c waveform). In addition, f0 divided by the binary counter 22 is extracted from the QC terminal (terminal 9) and input to the input terminal of the 3-state buffer 32 (d waveform).

The output waveforms of the 3-state buffers 32 and 33 are connected to the pull-up resistor R2 and the pull-down resistor R3 to maintain a constant level (e waveform). This pull-up resistor (R1) and pull-down resistor (R3) prevents two 3-state buffers (32, 33) of the 3-state buffer from operating at the same time, and controls the one to be shorted when the other is open. do.

The waveform (e waveform) passing through the pull-up resistor (R1) and pull-down resistor (R3) is input to the clock terminal (terminal 1) of the JK F / F 34 to generate a new code that becomes half frequency. Applied to the module (f waveform). If the final output frequency is 1 / 2f0, one cycle must be complemented to 1 / 2f0, so the frequency applied to the clock terminal of the JK F / F 34 using the JK F / F 34 is f0. To be

The waveform (g waveform) applied to the RX module is inverted (h waveform) while passing through the inverter 15, and the inverted waveform (h waveform) and the integrated waveform (j waveform) are delayed to delay the inverted waveform. The exclusive OR results in pulses equal to the time constant of integrator 17 occurring at each edge of the signal. This edge signal is used to clear the binary counters 21 and 22, which make the receiver synchronous clock.

Since the signal f0 output from the QC terminal (terminal 9) of the binary counter 22 is cleared at each edge, the clock of 2f0 always exists but the clock of f0 exists only when the clear signal does not exist for more than one period. In other words, the signal f0 goes high, which means that the input signal is high.

If the DCD signal is promised to be transmitted when it is high and is received when it is low, and inverting it so that the input of the AND gate 42 becomes low when transmitting, the binary counter 22 is not cleared during transmission, and Since the input of the gate 42 becomes high, the output waveform (t waveform) is output by the edge pulse of the RX-module input, and is used to clear the binary counters 21 and 22.

Since input data is received at f0 bps, sampling of input data should be performed at f0 frequency. Since f0 frequency of binary counter 22 is cleared, JK F / F using 2f0 frequency output from QB terminal (terminal 10). Generate a new signal f'0 with twice the frequency at (53) (o waveform).

Since the original f0 needs to be sampled with the new signal f'0 generated by the JK F / F 53, the edge of the new signal f'0 and the original f0 signal must match. For this purpose, a new clear signal is generated at the falling edge of the f0 signal and input to the clear terminal of the JK F / F 53 (r waveform).

Since the original f0 signal is slightly out of phase with the new signal f'0 passing through the JK F / F 53, the original f0 signal should be delayed slightly. To this end, a signal (p waveform) delayed by the time constant of the integrator by passing through the integrator consisting of the resistor R5 and the capacitor C4 is input to the D terminal (terminal 2) of the DF / F 62. Sampling to signal f'0 produces the final output.

As described above, according to the signal restoration circuit using the differential code according to the present invention, the coding method actually used is the differential code, which can prevent the phenomenon of padding during communication and solve the problem of frequency synchronization during reception, By detecting the edge of the time correction, and correcting the temporal error, and restores the same data as the transmitted data has the effect that can transmit a stable data without error.

Claims (5)

A signal restoration circuit for receiving a code signal used in wireless communication, decoding a received code signal, and restoring it to a signal corresponding to the received original code signal, An edge detection unit 10 for exclusively ORing the input signal and the waveform integrating the input signal to generate a pulse corresponding to the time constant of the integrator at the edge of the input signal, and to clear a counter for generating a synchronous clock of the receiver; A reference clock generator 20 for generating a reference frequency f0 and a double reference frequency 2f0 by dividing the input frequency; Alternatingly switching the frequency generated by the reference clock generator 20, a code generator for generating a new differential code that is half frequency by receiving twice the frequency when 0 and receiving the same frequency when 1 With 30 A reception request signal processing unit 40 for clearing the counter when transmitting the reception request signal and clearing the counter when receiving the reception request signal; Sampling sync clock generator 50 to create a new reference frequency (f'0) generated by JK F / F using a double reference frequency and Sampling unit 60 for sampling the reference frequency f0 generated by the reference clock generator and the new reference frequency f'0 generated by the sampling sync clock generator to output a signal matching the input signal. A signal recovery circuit using a differential code, characterized in that configured. According to claim 1, wherein the reference clock generator 20 receives a high reference frequency to the clock terminal (terminal 1) of the binary counter 21 and outputs the output of the QD terminal (terminal 6) clock terminal (number 13). Terminal), the QB terminal (terminal 10) outputs twice the reference frequency (2f0), and the QC terminal (terminal 9) comprises a binary counter 22 that outputs the reference frequency (f0). Signal recovery circuit using differential code. The reception request signal processing unit 40 according to claim 1, wherein the reception request signal processing unit 40 multiplies the output signal of the inverter 41, the inverter 41 for inverting the reception request signal, and the output signal of the edge detection unit 10, and the output value thereof. The signal recovery circuit using a differential code, characterized in that composed of an end gate (42) connected to the clear terminals (terminals 2, 12) of the binary counter (21, 22). 2. The inverter of claim 1, wherein the sampling synchronization clock generator 50 inverts the reference frequency f0 output from the QC terminal (terminal 9) of the binary counter 22. The output waveform passing through 51 is converted to an integrated waveform while passing through the resistor R4 and the capacitor C3, and the waveform output from the inverter 52 and the inverter 52 for inverting the converted integral waveform are clear terminals. The reference frequency (f0) by connecting a double reference frequency (2f0) output from the QB terminal (terminal 10) of the binary counter 22 to the clock terminal (terminal 5). Signal recovery circuit using a differential code, characterized in that consisting of JK F / F (53) for generating a. The sampling unit 60 of claim 1, wherein the sampling unit 60 includes an AND gate 61 for logically multiplying the reference frequency f0 and the serial clock SCK output from the binary counter 22, and a resistor for delaying a phase. Pass the integrator consisting of R5) and the capacitor (C4) and connect the delayed signal to the D terminal (terminal 2), and the waveform output from the JK F / F (53) is connected to the clock terminal (terminal 3) And a DF / F (62) for generating a recovered signal.