KR19990049428A - Controller circuit of laser printer - Google Patents

Abstract

The present invention relates to a controller circuit of a laser printer, and more particularly, to a controller circuit of a laser printer to reduce the number of EPROMs for storing the controller program and to improve the execution speed of the controller program.

In the controller circuit of the conventional laser printer, when the CPU accesses the EPROM and reads the program, it takes 2 cycles (62.5ns * 2 = 125ns). Therefore, it takes a long time to read the program of the EPROM. There is a problem in that the circuit configuration cannot be made economically because several expensive EPROMs must be provided to store the controller program.

The present invention reduces the EPROM by compressing and storing the controller program, restores the compressed controller program, stores it in the high speed SRAM, and executes the controller program in the high speed SRAM area, thereby improving the execution speed of the controller program.

Description

Controller circuit of laser printer

The present invention relates to a controller circuit of a laser printer, and more particularly, to a controller circuit of a laser printer to reduce the number of EPROMs for storing the controller program and to improve the execution speed of the controller program.

In general, a laser printer receives a data from a computer system and prints it on a sheet of paper so that it can be visually confirmed. A laser printer has a controller circuit on its own to control such an operation.

The controller circuit of the conventional laser printer is composed of a CPU 10 and a plurality of EPROMs 11 and 12, as shown in FIG.

The EPROMs 11 and 12 store programs for controlling overall operations of the laser printers, and the CPU 10 controls various operations of the laser printers by reading and executing programs stored in the EPROMs 11 and 12.

When the CPU 10 accesses the EPROMs 11 and 12, the CPU 10 outputs the chip select signal CS *, the output enable signal OE *, and an address to the EPROMs 11 and 12 to output the EPROMs 11 and 12. Access the program to load it.

In the controller circuit of the conventional laser printer configured as described above, the access time required by the CPU 10 to the EPROM and the data output time required by the EPROMs 11 and 12 are different, but the CPU 10 is required to access the memory means. One cycle time is 62.5 ns (based on the case where the external clock of the CPU is 16 MHZ), and 120 ns is required for the EPROMs 11 and 12 to access and output data. In other words, when the CPU 10 accesses the EPROMs 11 and 12 to read a program, two cycles of time (62.5 ns * 2 = 125 ns) are required. Therefore, when the program of the EPROMs 11 and 12 is read, It takes a long time, so there is a problem that the program execution speed drops.

In addition, the controller circuit of the conventional laser printer described above has a problem in that it is not possible to make the circuit configuration economical since several expensive EPROMs 11 and 12 must be provided in order to store the controller program.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and reduces the EPROM by compressing and storing the controller program, and restores the compressed controller program to high speed SRAM to execute the controller program, thereby improving the execution speed of the controller program. At the same time, the purpose is to make the circuit construction economical.

1 is a controller circuit diagram of a conventional laser printer

2 is a controller circuit diagram of the laser printer according to the present invention.

Explanation of symbols on the main parts of the drawings

10, 20: CPU 11, 12, 21: EPROM

22a to 22d: high speed SRAM

A feature of the present invention for achieving the above object is, in the controller circuit of the laser printer, EPROM for compressing and storing a program for controlling the operation of the laser printer; High speed SRAM for storing a program restored from a compressed state; And a CPU that accesses the EPROM, reads and restores the compressed and stored program of the EPROM, stores the restored program in the high speed SRAM, and accesses the high speed SRAM to execute the program.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The controller circuit of the laser printer according to the present invention comprises a CPU 20, an EPROM 21, and high speed SRAMs 22a to 22d, as shown in FIG. In the EPROM 21, a program for controlling all operations of the laser printer is compressed and stored.

The CPU 20 reads the program stored in the EPROM 21, restores it to its original state, stores it in the high speed SRAMs 22a to 22d, executes the program while accessing the high speed SRAMs 22a to 22d, and performs various control operations. do. In addition, the high speed SRAMs 22a to 22d store a program authorized from the CPU 20 and provide the program to the CPU 20 in accordance with the request of the CPU 20.

On the other hand, when accessing the EPROM 21, the CPU 20 outputs a chip select signal CS *, an output enable signal OE * and an address to the EPROM 21 to access the EPROM 21. The program stored in the compression is read. In the EPROM 21, basic programs for hardware testing are stored in an uncompressed form, and other programs are stored in a compressed form. When the CPU 20 accesses the high speed SRAMs 22a to 22d, the CPU 20 outputs a chip select signal CS *, an output enable signal OE * and an address to the high speed SRAMs 22a to 22d. The SRAMs 22a to 22d are accessed to store programs in the high speed SRAMs 22a to 22d, and the programs of the high speed SRAMs 22a to 22d are executed to perform overall control operations. In addition, while the EPROM 21 takes access and outputs data, it takes 120 ns while the high speed SRAM 22a-22d takes access and outputs 20 ns. The cycle time required for accessing the memory means is 62.5ns (based on the case where the external clock of the CPU is 16MHZ). That is, when the CPU 20 accesses the EPROM 21 to read a program, it takes 2 cycles (62.5ns * 2 = 125ns), but accesses the high speed SRAMs 22a to 22d to record the program. When reading, it takes 1 cycle time. Therefore, the CPU 20 reads and restores the program compressed and stored in the EPROM 21, stores it in the high speed SRAMs 22a to 22d, and then accesses the high speed SRAMs 22a to 22d to execute the program. This improves the overall control operation of the laser printer.

The operation of the laser printer controller circuit according to the present invention constructed as described above will be described in detail with reference to the accompanying drawings.

First, when a reset signal is applied to the CPU 20, the CPU 20 accesses the EPROM 21 to read and process a program stored in the EPROM 21. The EPROM 21 is a controller program that is responsible for basic hardware testing. Is not compressed. Other programs are stored in a compressed format. When the CPU 20 is reset, the hardware 20 is first tested by reading and executing a hardware test program from the EPROM 21, and the high-speed SRAMs 22a to 22d are read and restored by reading and storing the compressed and stored program. After storing in the high speed SRAMs 22a to 22d, the controller executes the high speed SRAMs 22a to 22d at high speed and executes them in the high speed SRAMs 22a to 22d. Two cycles are required to process data stored in the EPROM 21 with an access time of 120 ns, while one cycle is required to process data stored in the high-speed SRAMs 22a to 22 d with an access time of 20 ns, thereby improving execution speed. .

In addition, since the program is stored in the EPROM 21 in a compressed form, the program storage area can be reduced, thereby greatly reducing the number of EPROM 21.

As stated, the present invention reduces the EPROM by compressing and storing the controller program, restores the compressed controller program, stores it in the high speed SRAM, and executes the controller program in the high speed SRAM area, thereby improving the execution speed of the controller program. .

Claims (2)

In the controller circuit of a laser printer, An EPROM for compressing and storing a program for controlling the operation of the laser printer; High speed SRAM for storing a program restored from a compressed state; And a CPU for accessing the EPROM, reading and restoring a compressed and stored program of the EPROM, storing the restored program in the high speed SRAM, and accessing the high speed SRAM to execute the program. Circuit. The method of claim 1 And the access speed for the high speed SRAM is faster than the access speed for the EPROM.