KR19990047045A - Capacitor Manufacturing Method of Semiconductor Device - Google Patents

Abstract

In order to provide a reproducibility of the capacitance and to provide a method for manufacturing a capacitor of a semiconductor device suitable for increasing the effective area of the capacitor, a method of manufacturing a capacitor of a semiconductor device for achieving the above object is a method of manufacturing a capacitor of a semiconductor device, Forming a cylindrical silicon layer, placing a substrate in a vacuum chamber, injecting a gas containing Ge while maintaining a low temperature, and forming a crystal nucleus containing Ge on the surface of the silicon layer; Forming a lower electrode formed of a silicon layer having a surface protruding from the silicon layer by heat-treating the substrate, and forming a dielectric film on the lower electrode, and an upper electrode of a capacitor on the dielectric film. It characterized in that it comprises a step of forming a.

Description

Capacitor Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device, and more particularly, to a method of manufacturing a capacitor of a semiconductor device suitable for ensuring reproducibility of capacitance and increasing an effective area of a capacitor.

As the integration of semiconductor devices has progressed, the integration of DRAM (DRAM) devices, which are volatile memories, has been greatly progressed. DRAM devices consist of a unit cell consisting of a transistor that performs a number of switching operations and a capacitor that stores information in the form of charge. Therefore, it has a feature of storing information as a state of charge stored in a capacitor of a unit cell. In addition, the capacitor of the DRAM cell must store a certain amount of charge, and it is characteristic that a constant amount of state must be maintained at all times so as not to cause loss of information. Therefore, as the integration of DRAM proceeds, a reduction in the capacitor area is accompanied, and thus the capacitance of the other capacitor is lowered. Therefore, researches are being actively conducted to improve the capacity of the capacitor to the same level as before.

The capacitance stored in the capacitor has a relationship such as C =? A / d (C: capacitance,?: Dielectric constant, A: capacitor, d: thickness of the dielectric). Therefore, in an effort to increase capacitance, many efforts have been made to use a material having a high dielectric constant as an insulating film of a capacitor. The representative material is a silicon nitride film or a tantalum oxide film (Ta ₂ O ₅ ).

Alternatively, efforts have been made to improve the actual area of the capacitor in a limited area in order to improve the area of the capacitor of the DRAM cell. That is, in the conventional polycrystalline silicon as an electrode, a study of improving the area of a capacitor while switching from a simple lamination type to a multi lamination type, or by using a three-dimensional cylindrical structure and improving its area, and a hemispherical grain in their structure Research and development has been conducted to increase the surface area of capacitors by growing polysilicon (Hemispherical Grain poly Si: HSG).

Referring to the accompanying drawings, a capacitor of a conventional semiconductor device and a manufacturing method thereof will be described.

1 is a structural cross-sectional view showing a capacitor of a conventional semiconductor device, Figures 2a to 2g is a process cross-sectional view showing a capacitor manufacturing method of a conventional semiconductor device.

As shown in FIG. 1, a source / drain region 8 is formed in a semiconductor substrate 1 on both semiconductor substrates 1 of a gate electrode 4. A bit line 11 is formed in the source / drain region 8 on one side of the gate electrode 4, and the first lower electrode 14a contacts the source / drain region 8 on the other side of the gate electrode 4. There is). The second lower electrode 17 is formed on both side surfaces of the first lower electrode 14a to have a cylinder shape with the first lower electrode 14a to have a height higher than that of the first lower electrode 14a. At this time, polysilicon (HSG) 19 having hemispherical grains is formed along the surfaces of the first and second lower electrodes 14a and 17, and the dielectric film 20 is formed along the surface of the HSG 19. have. The upper electrode 21 of the capacitor is formed on the dielectric film 20. In this case, the HSG 19 is formed in an irregular shape on the surfaces of the first and second lower electrodes 14a and 17.

In the conventional method of manufacturing a capacitor of a semiconductor device configured as described above, as shown in FIG. 2A, a trench is formed in a field region of a semiconductor substrate 1 in which an active region and a field region are defined, and then an oxide film of the device is deposited and then planarized. An isolation region 2 is formed. Thereafter, a first oxide film is deposited on the semiconductor substrate 1 by a thermal oxidation process to have a thickness of about 80 GPa, and a first silicon layer is deposited on the first oxide film by low pressure chemical vapor deposition to have a thickness of about 2000 GPa. In this case, the first silicon layer is polycrystalline silicon or amorphous silicon, and doping is formed by ion implantation after depositing the first silicon layer which is not doped or when chemically depositing the polysilicon. Next, a second oxide film is deposited on the first silicon layer so as to have a thickness of about 1500 GPa.

Subsequently, the second oxide film, the first silicon layer, and the first oxide film are etched using a gate forming mask to form the gate cap insulating film 5, the gate electrode 4, and the gate oxide film 3. Subsequently, the LDD region 6 is formed by implanting phosphorus ions with low concentration N-type ions, depositing a third oxide film on the entire surface, and then etching back to form a first sidewall on both sides of the gate electrode 4 and the gate cap insulating film 5. The spacer 7 is formed. Subsequently, a source / drain region 8 is formed by implanting a high concentration of N-type ions into the surface of the semiconductor substrate 1 using the first sidewall spacer 7 and the gate electrode 4 as a mask.

As shown in Fig. 2B, a first planar protective film 9 having a thickness of about 4000 GPa is deposited on the entire surface. Subsequently, a first photoresist layer (not shown) is applied on the first planarization protective layer 9 to electrically connect the bit line and the fast transistor for data access to the source / drain on one side of the gate electrode 4. The first photosensitive film is selectively patterned so that the region 8 is exposed on the upper side. The first planarization layer 9 is anisotropically etched using the patterned first photoresist layer as a mask to form a first contact hole 10.

As shown in FIG. 2C, a second silicon layer is deposited to a thickness of about 2000 Pa on the entire surface of the first contact hole 10 by a low pressure chemical vapor deposition method, and then a metal silicide layer 12 is deposited on the second silicon layer. do. Subsequently, the metal silicide layer 12 and the second silicon layer are anisotropically etched using a bit line pattern mask to form the bit line 11 and the metal silicide layer 12. Then, the second planar protective film 13 is deposited on the entire surface to have a thickness of about 6000 kPa by chemical vapor deposition.

As shown in FIG. 2D, the first and second planar passivation layers are exposed so that the source / drain regions 8 on the other side of the gate electrode 4 are exposed to electrically connect the capacitor and the fast transistor for storing the data of the DRAM. (9, 13) is anisotropically etched to form a second contact hole. After depositing the amorphous third silicon layer 14 to be the lower electrode of the capacitor to fill the second contact hole so as to have a thickness of about 1500 kPa of the low pressure chemical vapor deposition method, the silicon oxide film is formed on the amorphous third silicon layer 14. An oxide film 15 is deposited to a thickness of about 3000 kPa. After the second photoresist film 16 is coated on the fourth oxide film 15, the second photoresist film 16 is selectively patterned so that only the second contact hole and the upper portion adjacent thereto are left.

As shown in FIG. 2E, the fourth oxide film 15 and the amorphous third silicon layer 14 are anisotropically etched in sequence using the patterned second photoresist layer 16 as a mask to be patterned with the first lower electrode 14a. The fourth oxide film 15 is formed. Subsequently, an amorphous fourth silicon layer is deposited on the entire surface to have a thickness of about 1500 GPa and then etched back to form second sidewall spacers made of amorphous silicon on both sides of the fourth oxide film 15 and the lower electrode 14a. In this case, the second sidewall spacer is used as the second lower electrode 17.

As shown in FIG. 2F, the fourth oxide film 15 is completely removed by dipping in hydrogen fluoride (HF). Subsequently, the semiconductor substrate 1 is placed in a chamber of a vacuum atmosphere, heated to a temperature of 650 ° C. or less, and then injected with silane (SiH ₄ ) gas to thereby surface the first lower electrode 14a and the second lower electrode 17. Hemispherical Grain poly Si (HSG) seeds 18 are formed with hemispherical grains in.

Subsequently, as shown in FIG. 2G, the gas supply is stopped in the same chamber and the HSG seed 18 is supplied with silicon atoms from the amorphous fourth silicon layer by annealing at 650 ° C. or higher. 14a, 17) to form HSG 19 on the entire surface.

In this case, when the HSG seed 18 is formed, the HSG 19 is formed together so that the reproducibility of capacitance with the first and second lower electrodes 14a and 17 is inferior.

Thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method to have a thickness of about 70 GPa, and the surface of the silicon nitride film is oxidized to form a thin dielectric film 20. Next, a polysilicon layer or an amorphous silicon layer is deposited on the entire surface and then patterned to form the upper electrode 21.

The conventional method of manufacturing a capacitor of a semiconductor device as described above has the following problems.

First, when HSG seed is formed by using SiH ₄ gas, HSG seed is formed and HSG growth progresses, and HSG changes significantly depending on the position of the lower electrode, and thus the capacitance of capacitance is accompanied by the change of capacitance. Poor reliability

Second, when the HSG seed is formed using SiH ₄ gas, the HSG seed is formed and the growth of the HSG proceeds, thereby making it impossible to form a rough surface of the lower electrode. Therefore, there is a limit to increasing the effective area of the capacitor.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a capacitor of a semiconductor device suitable for ensuring the reproducibility of the capacitance and increasing the effective area of the capacitor.

1 is a structural cross-sectional view showing a capacitor of a conventional semiconductor device

Figure 2a to 2g is a process cross-sectional view showing a capacitor manufacturing method of a conventional semiconductor device

3 is a data diagram showing the relationship between nucleation temperature and nucleation time for forming a capacitor according to the type of gas;

Figure 4 is a structural cross-sectional view showing a capacitor of the semiconductor device of the present invention

5A through 5G are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the present invention.

Explanation of symbols for the main parts of the drawings

31: semiconductor substrate 32: device isolation region

33: gate oxide film 34: gate electrode

35: gate cap insulating film 36: LDD region

37: first sidewall spacer 38: source / drain region

39: first planar protective film 40: first contact hole

41: bit line 42: metal silicide layer

43: second planar protective film 44: third silicon layer

44a: first lower electrode 45: fourth oxide film

46: second photosensitive film 47: second lower electrode

48: crystal nucleus

49: polysilicon (HSG) with hemispherical grain

50: dielectric film 51: upper electrode

In the method of manufacturing a capacitor of a semiconductor device of the present invention for achieving the above object, in the method of manufacturing a capacitor of a semiconductor device, forming a cylindrical silicon layer, and putting a substrate in a vacuum chamber to keep Ge Forming a crystal nucleus containing Ge on the surface of the silicon layer by injecting a gas containing the same; Forming an electrode, forming a dielectric film on the lower electrode, and forming an upper electrode of a capacitor on the dielectric film.

Referring to the accompanying drawings, a capacitor and a method of manufacturing the semiconductor device of the present invention will be described.

3 is a data diagram showing the relationship between nucleation temperature and nucleation time for forming a capacitor according to the type of gas, FIG. 4 is a structural cross-sectional view showing a capacitor of the semiconductor device of the present invention, and FIGS. It is a process sectional drawing which shows the capacitor manufacturing method of this invention semiconductor element.

In the present invention, the HSG seed is formed by using GeH ₄ gas or a mixture of silane (SiH ₄ ) and GeH ₄ when manufacturing the HSG capacitor, thereby activating the nucleation of the HSG seed and also forming the HSG seed and the HSG growth step. Through the process of precisely classifying the capacitor is to form.

First, the relationship between the nucleation temperature of the GeH ₄ gas and the silane (SiH ₄ ) gas and the time at which the nucleation is formed will be described. As shown in FIG. 3, the higher the temperature of the GeH ₄ gas and the SiH ₄ gas, the higher the nucleation time. Decreases. And when using GeH ₄ gas, the nucleation becomes easy even at low temperatures than when using the SiH ₄ gas.

This process according to the experimental data will be described as follows.

In the capacitor of the semiconductor device of the present invention, as shown in FIG. 4, a source / drain region 38 is formed on both semiconductor substrates 31 of the gate electrode 34 on the semiconductor substrate 31. A bit line 41 is formed in the source / drain region 38 on one side of the gate electrode 34, and the first lower electrode 44a contacts the source / drain region 38 on the other side of the gate electrode 34. There is). The second lower electrode 47 is formed on both sides of the first lower electrode 44a so as to have a cylindrical shape with the first lower electrode 44a to have a height higher than that of the first lower electrode 44a. At this time, polysilicon (HSG) seeds 48 having hemispherical grains are formed along the surfaces of the first and second lower electrodes 44a and 47, and the dielectric film 50 is formed along the HSG 49 surface. It is. The upper electrode 51 of the capacitor is formed on the dielectric film 50. At this time, the HSG 49 is formed to have a rough surface by disappearing into the surfaces of the first and second lower electrodes 44a and 47.

In the method of manufacturing a capacitor of a semiconductor device according to the first embodiment of the present invention configured as described above, as shown in FIG. 5A, a trench is formed in a field region of a semiconductor substrate 31 in which an active region and a field region are defined. After depositing and planarizing, the device isolation region 32 is formed. Subsequently, a first oxide film is deposited on the semiconductor substrate 31 by a thermal oxidation process to have a thickness of about 80 GPa, and a first silicon layer is deposited on the first oxide film by low pressure chemical vapor deposition to have a thickness of about 2000 GPa. In this case, the first silicon layer is polycrystalline silicon or amorphous silicon, and doping is formed by ion implantation after depositing the first silicon layer which is not doped or when chemically depositing the polysilicon. Next, a second oxide film is deposited on the first silicon layer so as to have a thickness of about 1500 GPa.

Subsequently, the second oxide layer, the first silicon layer, and the first oxide layer are etched using a gate forming mask to form a gate cap insulating layer 35, a gate electrode 34, and a gate oxide layer 33. Subsequently, the LDD region 36 is formed by implanting phosphorus ions with low concentration N-type ions, depositing a third oxide film on the entire surface, and then etching back to form a first sidewall on both sides of the gate electrode 34 and the gate cap insulating layer 35. The spacer 37 is formed. Subsequently, a source / drain region 38 is formed by implanting a high concentration of N-type ions into the surface of the semiconductor substrate 31 using the first sidewall spacer 37 and the gate electrode 34 as a mask.

As shown in FIG. 5B, a first planar protective film 39 having a thickness of about 4000 GPa is deposited on the entire surface. Subsequently, a first photoresist layer (not shown) is applied on the first planarization protective layer 39 to electrically connect the bit line and the fast transistor for data access to the source / drain on one side of the gate electrode 34. The first photosensitive film is selectively patterned so that the region 38 is exposed on the upper side. The first planarization protective layer 39 is anisotropically etched using the patterned first photoresist layer as a mask to form the first contact hole 40.

As shown in FIG. 5C, a second silicon layer is deposited to a thickness of about 2000 kPa on the front surface to fill the first contact hole 40 by a low pressure chemical vapor deposition method, and then a metal silicide layer 42 is deposited on the second silicon layer. do. Subsequently, the metal silicide layer 42 and the second silicon layer are anisotropically etched using a bit line pattern mask to form the bit line 41 and the metal silicide layer 42. Then, the second planar protective film 43 is deposited on the entire surface to have a thickness of about 6000 kPa by chemical vapor deposition.

As shown in FIG. 5D, the second planar passivation layer 43 exposes the source / drain region 38 on the other side of the gate electrode 34 to electrically connect the capacitor and the fast transistor for storing the data of the DRAM. Is anisotropically etched to form a second contact hole. A fourth oxide film, which is a silicon oxide film, is deposited on the amorphous third silicon layer 44 after depositing an amorphous third silicon layer to be a lower electrode of the capacitor to fill the second contact hole so as to have a thickness of about 1500 kPa of the low pressure chemical vapor deposition method. 45) is deposited to a thickness of 3000Å. After the second photoresist layer 46 is coated on the fourth oxide layer 45, the second photoresist layer 46 is selectively patterned so that only the second contact hole and the upper portion adjacent thereto are left.

As shown in FIG. 5E, the fourth oxide film 45 and the amorphous third silicon layer 44 are anisotropically etched in sequence using the patterned second photoresist layer 46 as a mask to be patterned with the first lower electrode 44a. The fourth oxide film 45 is formed. Thereafter, an amorphous fourth silicon layer is deposited on the entire surface to have a thickness of about 1500 mW, and then etched back to form second sidewall spacers made of amorphous silicon on both sides of the fourth oxide layer 45 and the first lower electrode 44a. At this time, the second sidewall spacer is used as the second lower electrode 47. In this case, the amorphous third silicon layer 44 and the amorphous fourth silicon layer are doped with an ethnic or phosphorus ion.

As shown in FIG. 5F, the fourth oxide film 45 is completely removed by dipping in hydrogen fluoride (HF). Subsequently, the semiconductor substrate 31 is placed in a chamber of a vacuum atmosphere, heated to a temperature of 600 ° C. or lower, and then GeH ₄ gas is injected to form germanium (S) on the surfaces of the first lower electrode 44a and the second lower electrode 47. Ge) or a silicon-germanium alloy (Si-Ge) to form a plurality of crystal nuclei 48.

Subsequently, as shown in FIG. 5G, the gas supply is stopped in the same chamber and annealed at a temperature of 620 ° C. or higher to form a crystal nucleus 48 composed of germanium or a silicon-germanium alloy. The silicon atoms are supplied from the silicon layer to produce hemispherical grain poly Si (HSG) 49 having hemispherical grains. At this time, since the silicon atoms around the crystal nucleus 48 are consumed, the roughness of the surface of the HSG 49 is increased. That is, one or more protruding portions appear between the crystal nuclei 48, thereby increasing the effective area of the capacitor.

Thereafter, a silicon nitride film is formed by a low pressure chemical vapor deposition method to have a thickness of about 70 GPa, and the surface of the silicon nitride film is oxidized to form a thin dielectric film 50. Next, a polysilicon layer or an amorphous silicon layer is deposited on the entire surface and then patterned to form an upper electrode 51.

Next, in the method of manufacturing a capacitor of a semiconductor device according to the second embodiment of the present invention, the fourth oxide layer 45 is completely removed by dipping in hydrogen fluoride (HF), and the semiconductor substrate 31 is placed in a chamber of a vacuum atmosphere at 600 ° C. or less. After heating to a temperature of GeH ₄ and the silane (SiH ₄ ) mixed gas is injected into the surface of the first lower electrode 44a and the second lower electrode 47 composed of a silicon-germanium alloy (Si-Ge) Except for forming a plurality of crystal nuclei 48 is formed in the same manner as in the first embodiment of the present invention.

The capacitor manufacturing method of the semiconductor device of the present invention as described above has the following effects.

First, when the capacitor is formed of HSG, the effective area of the capacitor can be increased by roughly forming the HSG on the first and second lower electrodes by precisely controlling the formation of the HSG seed and the HSG nucleation process.

Second, the HSG seed of the capacitor is formed at a low temperature by using GeH ₄ gas or a mixture of GeH ₄ gas and SiH ₄ gas, thereby improving the uniformity of HSG by controlling the formation of HSG seeds and HSG nucleation steps. . Therefore, it is possible to increase reliability by reducing the change in capacitance.

Claims (4)

In the manufacturing method of a capacitor of a semiconductor element, Forming a silicon layer of a cylinder structure; Placing a substrate in a vacuum chamber and injecting a gas containing Ge while maintaining a low temperature to form a crystal nucleus containing Ge on the surface of the silicon layer; Forming a lower electrode formed of a silicon layer having a surface protruded from the silicon layer while the silicon substrate is heat-treated in the chamber; Forming a dielectric film on the lower electrode; And forming an upper electrode of the capacitor on the dielectric film. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein said silicon layer is doped with either anionic or phosphorus ion. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein GeH ₄ gas or GeH ₄ and SiH ₄ mixed gas can be used as the gas containing Ge. The semiconductor according to claim 1, wherein the lower electrode formed of the silicon layer having the protruding surface is made of polysilicon (HSG) having hemispherical grains, and the silicon layer protruding from the crystal nucleus is one or more semiconductors. Method for manufacturing a capacitor of the device.