KR19990043641A - Digital V's Equalizer - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital VCR equalizers, in particular for improving the reliability of a system by appropriately initializing updated weight values.

Accordingly, the present invention provides an A / D converter for converting an analog reproduction signal reproduced from a magnetic channel into a digital signal; An interpolation filter for interpolating and outputting invalid data at an unsynchronized position when a reproduction signal output from the A / D converter is not synchronized with a system clock, and generating an invalid data signal corresponding to the position at which the invalid data is interpolated. ; After the feed forward filtering of the reproduction signal output from the interpolation filter as an input, an error between the previous reproduction signal and the current reproduction signal is detected and the weight is updated by the detected error to equalize the previous reproduction signal and the current reproduction signal. Equalizer; A data detector for detecting and outputting only reproduction data from the rounded reproduction signal outputted from the equalizer; A timing recovery unit for restoring the timing by synchronizing the data detected by the data detector with a system clock based on the error detected by the equalizer and outputting the timing to an interpolation filter; And a weight controller configured to receive an invalid data signal output from the interpolation filter, count the number of times, and initialize the update value of the equalizer when a predetermined number of times is generated.

This prevents unnecessary updating of the equalizer, thereby improving the reliability of the equalizer and preventing malfunction.

Description

EQUALIZER FOR A DIGITAL VCR

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an equalizer for reproducing a self-recorded signal of a digital VCR, and more particularly, to an equalizer of a digital BC for improving the reliability of a system by appropriately initializing an updated weight value.

With the development of computer, communication, broadcasting, home appliances, etc., the quality of information provided to general users is becoming more and more advanced, and such information can be characterized by multimedia, visualization, stereoscopic, and independence.

In particular, digital media use technology is the basis of this trend and has a great impact on the progress to the information society.

As the information age flows, the demand for high-speed data transmission and storage is rapidly increasing.

The storage of digital data has been mainly using a magnetic recording method, and is widely used by providing a lot of data storage capacity at a low price.

Currently, a magnetic recording device that is widely used is an analog method using RLL (Run Length Limited) and Peak Detection.

The equalization process of the conventional PR4 channel will be described with reference to FIG. 1.

The input code string of the magnetic recording / reproducing apparatus is recorded after passing through a precoder 100 composed of a 2-bit delayer 102 and a MOD2 adder 101.

That is, the magnetic channel 110, the equalizer 111, and the reproducing encoder 112, 1 / (1-D ² ) to adjust the characteristics before passing through the regenerator having the characteristics of (1-D ² ) during reproduction It is precoded to have a delay characteristic of.

The regeneration process consists of a delay characteristic of (1-D ² ), so that it can be decomposed into (1-D) and (1 + D).

Here, (1-D) is replaced with the differential characteristic by the magnetic channel 110 and the equalizer 111 of the reproduction system, and (1 + D) is the 1-bit delay 121 and the adder 122. It consists of a playback encoder 112 composed of.

Therefore, the reproduction process allows the reproduction signal to have a delay characteristic by (1-D ² ) consisting of (1-D) and (1 + D), and the recording signal is 1/1 in the precoder 100 for accurate reproduction. It is precoded to have a delay characteristic of (1-D ² ).

The magnetic recording signal precoded and recorded on the magnetic recording tape is reproduced by the head provided in the magnetic channel 110, reproduced and amplified through the rotary transformer, and has a (1-D) delay characteristic through the equalizer 111. Since it is input to the reproduction encoder 112 and has a (1 + D) delay characteristic, it has a delay characteristic of (1-D ² ) during reproduction.

The ternary waveforms (1, 0, -1) passing through the reproduction encoder 112 of (1 + D) are identified as binary waveforms (1, 0) by the data detector 113 to enable reproduction of the recording signal. .

That is, the data detector 113 generates three levels of reproduction signals output from the reproduction encoder 112 at two levels.

In other words, the data detector 113 corresponds to one level of the playback signal output from the playback encoder 112 to one level, to correspond to the 0 level playback signal to 0 level, and to a -1 level playback signal. Is equalized with one level of reproduction signal to generate equalization signals of 0 and 1 levels.

In such a PR4 detection method, the high frequency component emphasized in the equalization circuit can be suppressed by the (1 + D) circuit which is the reproducing encoder 112.

In the magnetic recording / reproduction channel, the reproduction signal is a differential form of the recording signal, so the step response h (t) that determines the characteristics of the magnetic recording channel is modeled by a Lorentzian function of Equation 1 below.

Here, PW ₅₀ is the width of the pulse corresponding to 50% of the maximum output value of h (t) and this value is determined according to the recording density.

However, the conventional analog magnetic recording and reproducing apparatus of the PR4 channel has a simple system implementation and effective timing recovery. However, as the recording density increases, the intersymbol interference (ISI) deepens, making it difficult to detect.

That is, the recording density for recording the magnetic recording signal on the magnetic recording tape becomes gradually higher, which makes it difficult to detect data during analog magnetic recording and reproduction of the aforementioned PR4 channel.

Therefore, in recent years, Partial Response Maximum Likelihood (PRML) technology has been introduced to reduce these effects.

The PRML technology can easily remove interference when detecting data by generating and transmitting artificial interference.

The configuration and operation of the equalizer of the digital VLC to which the PRML technology is applied will be described with reference to FIG. 2.

As shown in FIG. 2, a conventional digital equalizer equalizer includes a weight updater 135 and a weight updater for updating a weight by inputting a digital reproduction signal converted into a digital signal by the A / D converter 150. Delay 136, which delays the weight updated in step 135, and provides the weight update unit 135 to the weight update unit 135, from the A / D converter 150 according to the weight output from the delay unit 136. A feedforward filter 132 for feedforward filtering the output digital reproduction signal and outputting the reproduction signal, and a level for determining a three-level signal by inputting the reproduction signal output from the feedforward filter 132. The unit 133 and the level determiner 133 determine the level and compare the reproduction signal of the next clock output from the feedforward filter 132. The error detection unit 134 detects a signal and outputs the weight update unit 135 to the weight update unit 135 so as to update the weight.

On the other hand, the reproduction signal output from the feed forward filter 132 is input to the timing recovery unit consisting of the timing recovery unit 140, the D / A converter 141, and the VCO 142 is used for timing recovery. The recovered clock is input to the A / D converter 150.

The operation of the conventional equalizer configured as described above will be described.

The A / D converter 150 receives an analog reproduction signal as an input and accurately digitizes and restores timing to supply a digital signal to the equalizer 130.

In this case, the timing restoration is performed by the timing restoration unit 140, the D / A converter 141, and the VCO 142.

The A / D converter 150 is input to the equalizer 130 to equalize the digitized signal by the timing recovery to have a PR4 characteristic.

The digital reproduction signal output from the A / D converter 150 is output after the feedforward filter is filtered by the feedforward filter 132, and the filter output signal y (t (t) is output from the feedforward filter 132. )) Is the sum of the values obtained by multiplying the filter coefficients after the input digital reproduction signal x (t) is delayed at sampling time intervals, as shown in Equation 2 below.

Equation (2) can be briefly expressed internally of the vector as shown in Equation (3).

y (t) = X ^t W = W ^t X

In Equation 3 above, t is a transpose of a vector or matrix, and w and x (t), which are N-dimensional column vectors, are defined by Equation 4 below.

W = [w _0, w _1, w _2, ... , w _n-1 ] ^t

X (t) = [(t), x (t-1),... , x (t-n + 1)] ^t

The output of the equalizer 130, that is, the output y (t) of the feedforward filter 132 is determined by the level determiner 133 as a three-level signal d (t) and the error detector 134. ) Is entered.

That is, in order to update and determine the weight w shown in the above equation, the output y (t) of the feedforward filter 132 is input to the level determiner 133.

The three level signal d (t) whose level is determined by the level determiner 133 is the feedforward filter to a subsequent sampling clock by a sampling time interval in the error detector 134 as shown in Equation 5 below. An output signal of 132 and its difference is calculated and output as an error signal e (t).

e (t) = d (t) -y (t)

W _nw = W _old + μe (t) X (t)

Where w _nw is the updated new weight value and w _old is the previous weight value.

The error signal e (t) output from the error detector 134 is input to the weight updater 135 and used for weight update as shown in Equation 5 above.

That is, the weight updater 135 outputs the digital reproduction signal x (t) output from the A / D converter 150 and the delayed previous weight w _old output from the delay unit 136. And update the weight according to the error signal e (t) output from the error detector 134 and output the updated weight to the feedforward filter 132 through the delayer 136 to update the updated weight w _nw . Output for use.

Meanwhile, the data y (t) equalized and output from the equalizer 130 may be inputted to a Viterbi detector, which is a data detector, to effectively search for a desired signal.

On the other hand, as shown in Equation 5 above, in order to filter and converge the digital reproduction signal, the weight must be updated to update the new weight. The scaling factor μ is fixed so that the weight is updated only by the error value e. Is done.

However, this equalizer operates in synchronization with the system clock of 41.85MHz, but the system clock itself is applied to the equalizer with a clock count of 41.84 + αMHz because of its inaccuracy.

As a result, when the system is not synchronized correctly, the error itself is not correct when updating the weight due to the detected error, thereby causing unnecessary updates, which causes a decrease in reliability and malfunction of the system.

Accordingly, in order to solve the above problem, the present invention interpolates invalid data when the reproduction data is not synchronized with the system clock, and then adjusts the weight value of the equalizer when the number of data interpolation is a certain number or more. Its purpose is to provide an equalizer for digital VRLs that can be initialized to prevent unnecessary updates.

To achieve the above object, the present invention, as shown in Figure 3, the A / D converter 200 for converting the analog reproduction signal reproduced from the magnetic channel into a digital signal; When the reproduction signal output from the A / D converter 200 is not synchronized with the system clock CLK, the invalid data is interpolated and output to the unsynchronized position, and the invalid data is interpolated at the interpolated position. An interpolation filter 300 for generating a corresponding invalid data signal IVD; After the feed forward filtering of the reproduction signal output from the interpolation filter 300 as an input, an error between the previous reproduction signal and the current reproduction signal is detected, and then the weight is updated by the detected error to update the previous reproduction signal and the current reproduction. An equalizer 400 for equalizing the signal; A data detector 600 for detecting and outputting only the reproduction data from the rounded reproduction signal output from the equalizer 400; Based on the error (e) detected by the equalizer 400, a timing recovery unit for restoring the timing by synchronizing the data detected by the data detector 600 with the system clock CLK and outputting the timing to the interpolation filter 300 ( 700); The weight control unit 500 may be configured to receive an invalid data signal IVD output from the interpolation filter 300, count the number of times, and initialize the update value of the equalizer 400 when a predetermined number of times is generated. do.

1 is a structural diagram of a PR4 channel used for general magnetic recording and reproduction;

2 is a block diagram of a conventional DVCR equalizer

3 is a block diagram of an equalizer according to the present invention

4 is a detailed block diagram of a weight controller of FIG.

Explanation of symbols on the main parts of the drawings

200: A / D converter 300: interpolation filter

400: equalizer 500: weight control unit

510: Inverter 520: Pulse generator

530: cumulative calculation unit 531: adder

532: delay 540: counter

550: comparison unit 560: initialization unit

561: address generator 562: ROM

600: data detector 700: timing recovery unit

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The equalizer of the digital VR of the present invention includes an A / D converter 200, an interpolation filter 300, an equalizer 400, a weight controller 500, a data detector 600, and a timing recovery unit 700. .

The A / D converter 200 converts an analog reproduction signal read out from the magnetic tape into a digital reproduction signal.

The interpolation filter 300 inserts interpolation data, that is, invalid data when the digital reproduction signal and the system clock CLK are not synchronized, and generates an invalid data signal at a position where the invalid data is interpolated.

The equalizer 400 updates and equalizes the digital reproduction data input from the interpolation filter 300 by the detected error between previous and current data.

The weight control unit 500 accumulates the number of occurrences of the invalid data signal IVD output from the interpolation filter 300, and initializes the weight of the tunable unit 400 when it occurs more than a specified number of times. An inverter 510 for inverting the input invalid data signal IVD as shown in the figure; A pulse generator 520 for generating a clock of one clock cycle every predetermined time; A cumulative calculation unit 530 which calculates a difference between the outputs of the inverter 510 and the pulse generator 520 and accumulates the number of occurrences of the difference; A counter 540 for resetting the accumulation calculator 530 every predetermined time; A comparator 550 for comparing the cumulative number of times output from the cumulative calculating unit 530 with a preset number of sum_count and generating a reset signal according to the result; When the reset signal (reset) is generated from the comparator 550 is configured to be initialized 560 to generate and output the initialization data for initializing the equalizer.

Meanwhile, the accumulation calculator 530 obtains the difference between the inverted signal of the invalid data signal IVD output from the inverter 510 and the pulse generator 520 and then outputs the delayed signal from the delayer 532. An adder 531 which adds a previous difference value and outputs a accumulated difference result value; The delayer 532 outputs the delayed output of the adder 531 by a predetermined time.

In addition, the initialization unit 560 may include an address generator 561 which generates an address for designating each system when a reset signal is generated from the comparator 550; A ROM 562 receives an address of the address generator 561 and outputs initialization data corresponding to the address.

In this case, the ROM 562 stores the initialization data corresponding to each system constituting the equalizer for each address.

The data detector 600 searches and detects only the actual data DATA by a Viterbi algorithm or the like.

The timing recovery unit 700 synchronizes the data detected by the current data detector 600 with the system clock CLK based on an error e between the previous and current data detected by the equalizer 400 to adjust the timing. The restoring is output to the interpolation filter 300.

The operation of the present invention configured as described above will be described in detail.

The A / D converter 200 receives an analog reproduction signal as an input, converts the analog reproduction signal into a digital reproduction signal in synchronization with the system clock CLK, and outputs the digital reproduction signal to the interpolation filter 300.

At this time, since the system clock CLK may be a system clock of 41.85 + αMHz rather than 41.85MHz, synchronization may not occur correctly.

Therefore, when the digital reproduction signal output from the A / D converter 200 is not accurately synchronized with the system clock CLK, the interpolation filter 300 outputs a system clock output from the timing recovery unit 700. The data is interpolated and output as much as the size of the data whose timing is restored in units of CLK.

In other words, if the data converted to the digital signal and the system clock CLK are not synchronized, the invalid data is interpolated at the position and output to the equalizer 400, and the invalid data indicating the position at which the invalid data is interpolated is invalid. The data signal IVD is output to the weight controller 500.

The equalizer 400 receives the output data of the interpolation filter 300 to which the invalid data is interpolated, performs feedforward filtering, and then determines the filtered signal as a three-level signal.

The signal determined as three levels, the feed forward filtered signal, and the error signal (e) whose difference is calculated are output to the timing recovery unit 700, and the current weight of the feed forward filter is based on the error signal (e). The value will be updated.

The newly updated data is applied to the data detector 600, and the desired data is detected and output by the Viterbi algorithm.

Meanwhile, the timing recovery unit 700 receives the error signal e output from the equalizer 400 and the detected data DATA output from the data detector 600 to be timingd by the system clock CLK. It is restored to the output to the interpolation filter 300.

The weight control unit 500 accumulates the number of occurrences of the invalid data signal IVD output from the interpolation filter 300 and inputs the generated number of times, and initializes the weight of the tunable unit 400. It will be described in detail with reference to.

When the invalid data signal IVD output from the interpolation filter 300 is generated, the inverter 510 inverts it to an input and outputs it to the accumulation calculator 530, and the pulse generator 520 generates a predetermined time (41.85). One cycle of clock is generated every time, corresponding to MHz, to detect the number of times the invalid data signal IVD output from the inverter 510 occurs during the time corresponding to 41.85 MHz.

That is, the output of the inverter 510 and the output of the pulse generator 520 are applied to the adder 531 of the cumulative calculator 530 so that the difference between these two signals is calculated and then added with the previous comparison result value. The output value, that is, the accumulated difference value, is outputted. The value is inputted by the delayer 532 and delayed for a predetermined time and then outputted to the adder 531 again.

The cumulative result output from the adder 511 is applied to the comparator 550 and compared with the maximum occurrence count sum_count of the preset difference value.

The comparison unit 550 outputs a system reset signal when the occurrence frequency of the accumulated difference value output from the adder 531 and the maximum occurrence frequency sum_count of the preset difference value match.

On the other hand, the counter 540 is enabled from the time when the system is driven to generate a reset signal every predetermined time to reset the cumulative calculation unit 530.

This is to set the reset section soon to reset the accumulated difference value of the cumulative calculation unit 530 for each section.

Therefore, if the accumulated difference value generated during the period set by the counter 540 is smaller than the maximum number of occurrences (sum_count) of the difference value, the accumulated difference value does not have a significant effect on the weight update and is allowed. In this case, the comparator 550 generates a reset signal in order to prevent an unnecessary update of the system.

Therefore, the reset signal (reset) output from the comparison unit 550 is applied to the address generator 561 of the initialization unit 560, the address generator 561 applies a reset signal (reset) It generates an address that designates each system of the equalizer preset therein.

Therefore, the address data output from the address generator 561 is applied to the ROM 562 to output initialization data stored in the ROM 562.

In other words, the ROM 562 stores initialization data required by each system constituting the equalizer, and outputs initialization data designated by the address generator 561 to each element of the system.

Therefore, the equalizer in which unnecessary weights are updated by initializing each element constituting the system, that is, the equalizer, by this initialization data is initialized.

As described above, the equalizer according to the present invention interpolates invalid data when the reproduction data is not synchronized with the system clock, and then initializes the weight value of the equalizer when the number of times of data interpolation is a predetermined number or more. By preventing unnecessary updates, it is possible to improve the reliability of the equalizer and to prevent malfunctions.

Claims (4)

An A / D converter for converting an analog reproduction signal reproduced from the magnetic channel into a digital signal; An interpolation filter for interpolating and outputting invalid data at an unsynchronized position when a reproduction signal output from the A / D converter is not synchronized with a system clock, and generating an invalid data signal corresponding to the position at which the invalid data is interpolated. ; After the feed forward filtering of the reproduction signal output from the interpolation filter as an input, an error between the previous reproduction signal and the current reproduction signal is detected and the weight is updated by the detected error to equalize the previous reproduction signal and the current reproduction signal. Equalizer; A data detector for detecting and outputting only reproduction data from the rounded reproduction signal outputted from the equalizer; A timing recovery unit for restoring the timing by synchronizing the data detected by the data detector with a system clock based on the error detected by the equalizer and outputting the timing to an interpolation filter; And a weight controller configured to receive an invalid data signal outputted from the interpolation filter and count the number of times to reset the update value of the equalizer when a predetermined number of times are generated. The apparatus of claim 1, wherein the weight controller comprises: an inverter for inverting an invalid data signal input; A pulse generator for generating a clock of one clock cycle every predetermined time; A cumulative calculation unit for obtaining a difference between the outputs of the inverter and the pulse generator and accumulating the number of occurrences of the difference; A counter for resetting the accumulation calculator every predetermined time; A comparator for comparing the cumulative number of times output from the cumulative calculating unit with a preset number and generating a reset signal according to the result; And a reset unit configured to generate and output initialization data for initializing the equalizer when the reset signal is generated from the comparator. The accumulator of claim 2, wherein the accumulator calculates a difference between the inverted signal of the invalid data signal output from the inverter and the pulse generator and then adds the difference of the previous difference output from the delayer to output the accumulated difference result value. Adder; And a delay unit configured to delay the output of the adder for a predetermined time and output the delayed equalizer. 3. The apparatus of claim 2, wherein the initialization unit comprises: an address generator for generating an address for designating each system when a reset signal is generated from the comparator; And a ROM for receiving the address of the address generator and outputting initialization data corresponding to the address.