KR19990039677A - Manufacturing method of high load resistor type SRAM cell - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device for improving a method of forming a node contact in a high load resistor (SLR) type static random access memory (SRAM) manufacturing process, wherein the resistance value of a load resistance is increased. In order to provide a method for manufacturing an SRAM cell capable of lowering the resistance of the node contact, the node contact is simultaneously formed at the time of forming the bit line contact, and the second polysilicon film for forming the bit line is formed in the node contact hole, thereby forming the node connection line. Form. Then, a resistive contact hole formed through the interlayer insulating film is formed thereon to form a third polysilicon film for resistance, so that the drain of the transfer transistor, the drain of the pull-down transistor, the gate of another pull-down transistor and one side terminal of the load resistor are finally formed. It can form a connected node electrically connected.

Description

Manufacturing method of high load resistor type SRAM cell

The present invention relates to a high load resistor type SRAM cell manufacturing method for improving a method of forming a node contact in an HLR type static random access memory (SRAM) manufacturing process.

Generally, SRAM cell is composed of two transfer transistors, two pull-down N-channel (pull down) driver transistors, and two pull-up load devices.In the integrated circuit manufacturing, semiconductor devices are fabricated as devices become more integrated and smaller in size. There are many problems with the process. In order to reduce the area of the pull-up bulk transistor used as a pull-up device in SRAM by 40%, a high load resistor (HLR) type cell including a load resistor is used.

1 is an equivalent circuit diagram of a general HLR-type SRAM cell, and FIGS. 2A to 2D are cross-sectional views illustrating a method of forming a node contact of a conventional HLR-type SRAM cell, respectively.

As shown in Fig. 1, the storage node n1 electrically connects the drain of the transfer transistor, the drain of the pull-down transistor, the gate of the other pull-down transistor, and one terminal of the load resistor. In contrast, the storage node n2 electrically connects the drain of the transfer transistor, the drain of the pull-down transistor, the gate of another pull-down transistor, and one terminal of another load resistor.

A conventional method for forming a SRAM cell storage node will be described using an n1 storage node as an example.

First, as shown in FIG. 2A, a LOCOS process is performed on the silicon substrate 21 to form a field oxide film 22. A gate oxide film and a gate first polysilicon film 23 of each transistor are sequentially stacked on top of each other, and a photoresist pattern 201 for gate electrodes is formed on the gate oxide film.

Next, as shown in FIG. 2B, the first polysilicon layer 23 and the gate oxide layer are etched using the previously formed photoresist pattern 201 as an etch barrier to expose the silicon substrate 21. Ion implantation is performed in the exposed silicon substrate 21 to form the source and drain junction regions of the MOS transistor. An undoped oxide film is formed along the lower step formed in the upper part of the entire structure, and a BPSG film 24 is formed on the upper part of the second insulating film having excellent planarization characteristics. A photoresist pattern 202 using a bit line contact mask is formed thereon.

Next, as shown in FIG. 2C, the bit line exposing the source and drain junction regions formed by etching the lower BPSG 24 layer and the first insulating layer using the previously formed photoresist pattern 202 as an etch barrier. A contact hole is formed. The second polysilicon layer 25 for forming the bit line is deposited on the entire structure, and then patterned to form the bit line. A BPSG (BoroPhospho silicate glass) film 26 is formed as an interlayer insulating film thereon to maintain inter-element insulation. A photoresist pattern 203 using a mask for forming node contacts is formed thereon.

Next, as shown in FIG. 2D, the BPSG films 26 and 24 and the undoped oxide film are etched using the previously formed photoresist pattern 203 as an etch barrier to form node contact holes. Subsequently, the third polysilicon film is deposited, and then doped by ion implantation and patterned to impart conductivity to the third polysilicon film 27A in the node contact hole region. "27B" in the drawing indicates resistance.

In the conventional HLR type SRAM cell structure formed as described above, the third polysilicon film 27A formed by filling the node contact hole is formed on the sidewalls of the insulating film such as the BPSG films 24 and 26 and the undoped oxide film and the node contact hole. The part in contact is not used as a resistor, and in the third polysilicon film 27B formed on the BPSG film 26, a power supply voltage connecting part (not shown) is not used as a resistor, thereby increasing the load resistance value. There is a problem that is difficult to make.

In addition, in the conventional HLR structure, when ion implantation is performed in the node contact hole portion of the third polysilicon film, the ion is not diffused in the third polysilicon film 27A deep in the sidewall of the node contact, so that the first transistor of the driving transistor is not formed. The contact resistance is increased between the polysilicon film 23 and the junction region. In addition, since ion implantation is performed in the third polysilicon film 27A at the node contact hole, side diffusion is performed on the resistance-connected third polysilicon film 27B, thereby degrading the characteristics of the resistance.

In order to solve the problems described above, the present invention provides a high load resistor type SRAM cell capable of increasing the resistance value of the load resistance formed and lowering the resistance of the node contact when HLR type SRAM cells are manufactured. It is an object of the present invention to provide a manufacturing method.

1 is an equivalent circuit diagram of a typical HLR type SRAM cell.

2A to 2D are cross-sectional views illustrating a method for forming a node contact of a conventional SRAM cell.

3A to 3F are cross-sectional views illustrating a method for forming a node contact of an SRAM cell according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

31 silicon substrate 36 interlayer insulating film

32: field oxide film 37: third polysilicon film for node contact

33: first polysilicon film for word line 38: power supply voltage connection portion

34: interlayer insulating film

35: second polysilicon film for bit lines

In order to achieve the above object, the method of manufacturing the high-load resistor-type SRAM cell of the present invention comprises forming at least two driving transistors and at least two transfer transistors each having a gate and a source / drain junction region on a semiconductor substrate. Stage 1; A second step of forming a first interlayer insulating film on the wafer on which the first step is completed; By selectively etching the first interlayer insulating layer, a node contact hole exposing one side junction of the gate of the one driving transistor and the other driving transistor and one side junction of the one transfer transistor, and the other side junction of the transfer transistor are exposed. A third step of simultaneously forming the exposed bit line contact holes; Forming a conductive film filling the node contact hole and the bit line contact hole, and selectively etching the conductive film to bury the node contact hole and a second pattern of the conductive film filling the bit line contact hole A fourth step of forming a pattern; A fifth step of forming a second interlayer insulating film on the entire structure of the wafer where the fourth step is completed; Selectively etching the second interlayer insulating layer to expose a portion of the first pattern of the conductive layer; And a seventh step of forming a resistive layer contacting the first conductive pattern.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3A to 3F are cross-sectional views illustrating a method for forming a node contact of an SRAM cell according to an embodiment of the present invention.

First, as shown in FIG. 3A, a LOCOS process is performed on the silicon substrate 31 to form a field oxide film 32. A gate oxide film and a gate first polysilicon film 33 of each transistor are sequentially stacked on top of each other, and a photoresist pattern 301 for gate electrode is formed on the gate oxide film.

Next, as shown in FIG. 3B, the gate first polysilicon layer 33 and the gate oxide layer are etched using the preformed photoresist pattern 301 as an etch barrier to expose the silicon substrate 31. Ion implantation is performed in the exposed silicon substrate 31 to form the source and drain junction regions of the MOS transistor. A first insulating film is formed along the lower step formed in the upper part of the entire structure, and a BPSG film 34 is formed on the upper part of the second insulating film having excellent planarization characteristics to perform the planarization process. A photoresist pattern 302 using a bit line contact mask is formed thereon.

It should be noted that the open portion of the photoresist pattern 302 opens not only the bit line contact portion but also the node contact portion.

Next, as shown in FIG. 3C, a bit line exposing the source and drain junction regions formed by etching the lower BPSG 34 layer and the first insulating layer using the previously formed photoresist pattern 302 as an etch barrier. Forming a contact hole and a first contact hole for a node contact. The first contact hole for the node contact exposes the first polysilicon layer 33 forming the gate electrode of the driving transistor Q2 of FIG. 1 and the source and drain junction regions (not shown) of the transfer transistor Q3.

After the second polysilicon layer 35 is stacked on the entire structure, a photoresist pattern 303 for patterning the second polysilicon layer 35 is formed. In this case, the photoresist pattern 303 covers the bit line contact hole and the first contact hole for the node contact to form a sufficient margin during the process. In this case, a tungsten silicide film may be formed on the second polysilicon film 35 to improve conductivity.

Next, as illustrated in FIG. 3D, the bit line 35A and the node contact connection line 35B are patterned by etching the second polysilicon layer 35 using the previously formed photoresist pattern 303 as an etch barrier. . Subsequently, an undoped oxide film and a BPSG (BoroPhospho silicate glass) film 36 are formed as an interlayer insulating film to maintain inter-device insulation. Subsequently, a third polysilicon film is formed to form a resistor. Since one terminal of the resistor is connected to the node, a contact hole photoresist pattern 304 for forming a contact to the node is formed.

Next, as shown in FIG. 3E, the BPSG film 36 is selectively etched using the previously formed photoresist pattern 304 as an etch barrier to expose the lower second polysilicon film 35B for the node contact connection line. A second contact hole for the node contact is formed. After removing the photoresist pattern 304, a third polysilicon film 37 forming a load resistance is formed on the upper portion of the photoresist pattern 304, and a portion of the previously formed third polysilicon film 37 is exposed to expose the first ion. In the process, the photoresist pattern 305 for forming the power supply voltage connection portion is formed. Here, before forming the power supply voltage connecting portion, the third polysilicon layer 37 is entirely implanted with a second ion to properly adjust the resistance. The impurity dose injected during the second ion implantation process is implanted during the first ion implantation process. The adjustment is carried out so as to have a relatively small dose amount relative to the impurity dose amount.

Next, as shown in FIG. 3F, the impurity is partially implanted using the previously formed photoresist pattern 305 as an ion implantation barrier to form a power supply voltage connecting portion 38, and finally, a third layer for the resistance pattern. The polysilicon film is patterned.

According to the present invention as described above, the node contact hole is simultaneously formed in the portion where the node contact is to be formed, and the second polysilicon film for forming the bit line is formed in the node contact hole, thereby forming a node connection line. do. Then, a resistive contact hole formed through the interlayer insulating film is formed thereon to form a third polysilicon film for resistance, so that the drain of the transfer transistor, the drain of the pull-down transistor, the gate of the other pull-down transistor, and one terminal of the load resistor are finally formed. It can form a connected node electrically connected.

Accordingly, the third polysilicon film 37 contacted on the second polysilicon film 35B formed in the node contact hole can be smoothly connected to the gate electrode of the driving transistor and the node contact. ) Are all used as load resistances, so the resistance of the device can be improved by increasing the resistance value proportional to the length and area.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes are possible within the scope of the present invention without departing from the technical idea. It will be evident to those who have knowledge of.

According to the present invention as described above, when forming a node contact of an HLR-type SRAM cell, a second polysilicon film for forming a bit line is formed in a portion where a node contact hole is to be formed, and then a contact hole is again formed to form a third contact for a node contact. By forming a polysilicon film it has a larger load resistance than the conventional SRAM cells.

In addition, by forming the polysilicon film for the bit line in the node contact portion, the resistance between the third polysilicon film for the node contact and the first polysilicon film forming the gate electrode of the exposed driving transistor is kept constant, thereby improving device characteristics. Let's do it.

Claims (3)

Forming at least two drive transistors and at least two transfer transistors each having a gate and a source / drain junction region on a semiconductor substrate; A second step of forming a first interlayer insulating film on the wafer on which the first step is completed; By selectively etching the first interlayer insulating layer, a node contact hole exposing one side junction of the gate of the one driving transistor and the other driving transistor and one side junction of the one transfer transistor, and the other side junction of the transfer transistor are exposed. A third step of simultaneously forming the exposed bit line contact holes; Forming a conductive film filling the node contact hole and the bit line contact hole, and selectively etching the conductive film to bury the node contact hole and a second pattern of the conductive film filling the bit line contact hole A fourth step of forming a pattern; A fifth step of forming a second interlayer insulating film on the entire structure of the wafer where the fourth step is completed; Selectively etching the second interlayer insulating layer to expose a portion of the first pattern of the conductive layer; And A seventh step of forming a resistive layer contacting the first pattern of the conductive film Method for manufacturing a high load resistor type SRAM cell comprising a. The method of claim 1, The resistor layer comprises a polysilicon film having a predetermined amount of dopant for adjusting the resistance value. The method of claim 1, The conductive film is a high load resistor type SRAM cell manufacturing method comprising a poly silicon film or a poly side film.