KR19990037547A - Display control method and device - Google Patents

Abstract

Provided is a display control method and apparatus that can display a large number of lines of Chinese characters in a high quality without a load on the CPU, and provides dot display data of character fonts in the same manner as the character display area in the dual port RAM (6). After being developed and stored in the storage area of the configuration, it is latched in the display data latch 10 as line data according to the common counter value in the common counter 14, and the liquid crystal display 1 spans a plurality of rows. In the display control method for displaying, the line address value for storing the space line data in advance in the predetermined line addresses 30 and 31 in the RAM 6 and sequentially specifying and reading the line data from the RAM 6. By changing the correspondence between and the common counter value, the space line data was inserted between the lines on the liquid crystal display 1.

Description

Display control method and device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control method and apparatus for driving control of a display panel for character display. More particularly, the present invention relates to a method of controlling a display panel to prevent characters from being joined when characters are displayed on a plurality of lines. A display control method and apparatus for displaying.

Background Art Conventionally, a method of using a display control device having a display data RAM that stores lighting / off of each dot of a display panel when displaying characters or the like using a small display panel of a dot matrix is known. Here, one bit of the display data RAM is symmetrical to one dot of the display panel, and an interface between the display control device and the main CPU is generally a 8-bit or 4-bit parallel interface or a serial interface. Treated in bit units.

On the other hand, character font data of a certain number of dots is used as a source of character data, and in most cases, a 16-dot font is used to display Chinese characters in detail or high quality.

However, in the case of using the conventional technique, a process of simply dividing the data of a 16-dot font into 8 dots and sequentially writing the font data into the display data RAM in 8-bit units by the CPU interface is performed between adjacent lines. A state without gaps occurs, and a problem arises in that the characters of the up line and the character of the down line are joined.

In order to prevent the character joining, it is necessary to perform data shaping processing on the main CPU so that 17-bit data formed by adding 1 bit for creating a gap between 16-bit data lines of the character font is written to the 8-bit interface. There was a problem that the load on the main CPU increased.

SUMMARY OF THE INVENTION In order to solve such a problem in the related art, in the case where characters are displayed on a plurality of lines, the display control device side performs a space between lines in response to a request from the main CPU, SUMMARY OF THE INVENTION An object of the present invention is to provide a display control method and apparatus for reducing the load and making it possible to display a large number of lines of Chinese characters in a simple manner.

1 is a block diagram showing an example of an embodiment of a display control device according to the present invention;

FIG. 2 is a diagram showing a part of an address configuration diagram for explaining the state of Chinese character dot display data stored in the display data RAM shown in FIG.

Fig. 3 is a diagram showing the remaining part of the address structure diagram for explaining the state of the Chinese character dot display data stored in the display data RAM shown in Fig. 1;

4 is a detailed block diagram of the line address generator shown in FIG. 1;

5 is an explanatory diagram for explaining the operation of the line address generator shown in FIG. 4;

FIG. 6 is a diagram showing a case where a plurality of lines of character strings are displayed by the display control device shown in FIG.

<Description of Symbols for Main Parts of Drawings>

1 liquid crystal display device 1A display panel

2: Display control device 3: MPU interface

4: Command decoder 5: Display data memory block

6: display data RAM 7: input / output circuit

8 column address decoder 9 line address generator

10: display data latch 11: page address register

12: column address register 13: column address counter

14: common counter 15: liquid crystal drive circuit

16 liquid crystal power supply circuit 17 CR oscillation circuit

18: display timing circuit 91: interline decoder

92: row block decoder 93: counter value forced change circuit

94: subtraction circuit M1 to M3: character display string

SX: jump signal

A feature of the method of the present invention for solving the above problems is to receive the dot display data of a character font to be displayed, and to expand the dot display data of the character font to be displayed once in a storage area having the same configuration as that of the character display area in the display data RAM. After that, the dot display data stored in the display data RAM is read in units of line data corresponding to one line of the character display area in accordance with the common counter value of the common counter, and latched in the display data latch. A display control method in which a dot matrix display panel is displayed over a plurality of lines in synchronization with the common counter value data, wherein the space line data is stored in advance at a predetermined line address in the display data RAM, and the display is performed. Line address for sequentially specifying and reading line data in data RAM So that the line space data is inserted in between the lines on the display panel by changing a corresponding relationship between the value and the counter value is common to a point.

According to this configuration, when generating line address values for reading line data from the display data RAM based on common counter value data for driving control of the common driver of the display panel, a line address value group for specifying a plurality of line data is specified. A series of line address values are prepared by inserting the line address values in which the space line data is stored in between. The line data is sequentially read from the display data RAM according to the prepared series of line address values, expanded to a display position on the display panel, latched to the display data latch, and sent to the display panel according to the common counter value for display between lines. Space can be displayed. Therefore, it is only necessary to change the correspondence between the common counter value and the line address value, and the space can be displayed between lines without increasing the load in the CPU.

In addition, the display control apparatus according to the present invention is characterized in that the display data RAM for storing the dot display data of the character font to be displayed in a storage area having the same configuration as the character display area, the common counter for outputting a common counter value, A line address generator for generating a line address value for reading dot display data from the display data RAM as a plurality of line data corresponding to the common counter value, and a line read from the display data RAM in response to the line address value. A display control having latch means for sequentially latching data, and causing the display panel to display a required character on a plurality of lines based on line data latched by the latch means in response to the common counter value; In the apparatus, the line address generator is a common car. First discriminating means for discriminating whether or not a touch corresponds to a line address value for displaying interline space on the display panel, and whether the common counter value corresponds to the line address value for the number of lines of character data on the display data RAM. Second and second discrimination means for determining whether or not to read the character display data over a plurality of lines of a configuration in which space line data is added between lines in the display data RAM in response to the common counter value. It has a correction means for obtaining the address data by correcting the common counter value based on each determination result of the discrimination means, wherein the address data in the correction means is used as the line address value.

According to this configuration, the character font data of the required number of dots is expanded in the display form in the display data RAM and stored over a plurality of lines without taking the space between lines. The dot display data stored so as to correspond to the display form in the display data RAM is read out in line data units using line address values obtained by modifying the common counter value according to the determination results of the first and second discriminating means. As a result, characters can be displayed on a display panel by putting a space between lines over a plurality of lines.

Embodiment of the Invention

EMBODIMENT OF THE INVENTION Hereinafter, an example of embodiment of this invention is described in detail with reference to drawings.

1 to 6 show an example of an embodiment of a display control device according to the present invention for performing display control of a liquid crystal display device for displaying figures, characters, etc. by dot matrix display. In the present embodiment, the description will be given using 51com and 96seg display capacities for realizing three-line display of 16-bit fonts, but the present invention is not limited to this specific configuration example.

1 is a block diagram showing a display control device according to the present invention. 1 is a liquid crystal display. In the liquid crystal display 1, a liquid crystal is enclosed between a pair of transparent glass substrates, and a plurality of scanning lines and signal lines are formed in a matrix form on the opposite side of the pair of transparent glass substrates, and the liquid crystal is formed at each intersection between the scanning lines and the signal lines. A display dot is formed, and the scan line and the signal line are sequentially driven by driving control by the common driver and the segment driver, and charges are accumulated in the liquid crystals of the selected intersections, so that a character or an image can be displayed. Will.

2 is a display control device for driving control of a liquid crystal display 1 for displaying a character or an image on the liquid crystal display 1, wherein dot display data and instructions of characters or images for display are obtained from an external CPU (not shown). It has a MPU interface 3 for receiving, a command decoder 4 for decoding the received command, and a display data memory block 5 for preparing dot display data for storing and displaying the received dot display data.

The display data memory block 5 is composed of a display data RAM 6, an input / output circuit 7, a column address decoder 8, a line address generator 9 and a display data latch 10. The page address prepared by the page address register 11 is given to the entry / exit circuit 7, and the column address prepared by the column address register 12 and the column address counter 13 is given to the column address decoder 8.

The common counter value in the command counter 14 is input to the display data RAM 6 and to the liquid crystal drive circuit 15 to which the display data prepared for display is supplied from the display data latch 10. 16 is a liquid crystal power supply circuit, 17 is a CR oscillation circuit for generating timing pulses, and 18 is a display timing circuit.

The display data RAM 6 is a dual port (RAM), and the dot display data input through the MPU interface 3 from the outside is transferred to the page address from the page address register 11 and the column address in the column address counter 13. Store in accordance with.

2 and 3 show an example of storing dot display data of Chinese characters called "document" in the display data RAM 6. In the example shown in Figs. 2 and 3, 16-dot character font data is written as 8-bit parallel data by simply dividing it into two.

Then, dot display data of characters "referred" are stored in column addresses (00 to 07) by designation of subsequent page addresses (0, 0, 1, 0) and (0, 0, 1, 1). .

In reality, the dot display data is similarly stored after the column address 07 of the page addresses (0, 0, 0, 0) and (0, 0, 0, 1), and the page addresses (0, 0, 0, 0), The character data for the first row is stored as dot display data in the memory area determined by (0, 0, 0, 1) and the column address. Similarly, character data for the second row is stored as dot display data in the next memory area determined by the page addresses (0, 0, 1, 0), (0, 0, 1, 1) and column address.

In the memory area defined by the page addresses (0, 1, 0, 0), (0, 1, 0, 1) and column addresses (00 to 5F), the character data of the third row is similarly stored.

In the page addresses (0, 1, 1, 0), three lines of data memory area are reserved, and data for displaying interline space is stored therein.

In the display data RAM 6, the dot display data is expanded to the display position of the liquid crystal display 1 in units of 8 bits as described above, and three rows of character data are stored as the dot display data. The data thus stored is read out from the display data RAM 6 in units of one line of data up to the column addresses (00 to 5F) at the line address designated by the line address value in the line address generator 9. And latched in the display data latch 10.

4 shows a line address generator 9 for generating a set of line address values for sequentially reading dot data one line of data from the display data RAM 6 based on a common counter value output from the common counter 14. A detailed block diagram of is shown.

The line address generator 9 responds to the mode signal output from the command decoder 4, outputs a line address value for displaying Chinese characters such as Chinese characters, and displays a graphic for displaying graphics such as illustrations. It is configured to operate somewhere in the normal mode for outputting the line address value for the device.

In the normal mode, the input common counter value is output as it is as a line address value. Accordingly, as shown in Figs. 2 and 3, the stored data in the display data RAM 6 is sequentially read from above for each line data and displayed. It is stored in the data latch 10.

On the other hand, in the Chinese character mode, in order to prevent the combination of the upper and lower characters by displaying the character data of three lines as it is, the display data latch 10 displays data for displaying the characters of three lines in the form of inserting a space between each line. This mode outputs a set of line address values for preparation.

The line address generator 9 includes an interline decoder 91, a row block decoder 92, a counter value forced change circuit 93, and a subtraction circuit 94.

The interline decoder 91 forcibly changes the common counter value to a line address value for reading the interline space data when it detects that the common counter value is a value corresponding to a place that should be the interline space on the display panel surface of the liquid crystal display 1. This circuit outputs a jump signal (SX).

Here, the common counter values COM1 to COM50 and COMICON (see Figs. 2 and 3) coincide with the line address values in the normal mode. In this embodiment, 00 to 0Fh are assigned as the line address value for the first line character string, 10 to 1Fh for the second line member, and 20 to 2Fh for the third line, respectively, and the line address value of the data for the space is 30. It consists of two lines of -31h.

In response to the jump signal SX being input, the counter value forced change circuit 93 changes the common counter at that time to the line address value of the display data RAM 6 in which dot display data for interline space is stored. do. That is, since the common counter values 10h and 21h correspond to places of the interline space on the display panel, they are changed to line address values 30h and 31h for the interline space in response to the jump signal SX. (See Fig. 5).

The row block decoder 92 corresponds to a specific row block whose common counter value requires shift processing by data insertion processing for the interline space executed by the interline decoder 91 and the counter value forced change circuit 93. Determines whether it is a common counter value. In this embodiment, as is understood from the above description, it is necessary to decrease the value by 1 when the common counter value is 11 to 20 to set the line address value, and decrease the value by 2 when the common counter value is 22 to 31. In the row block decoder 92, data indicating this reduced value is output as subtracted data SY.

The subtraction data SY in the row block decoder 92 is input to the subtraction circuit 94, where the common counter value is subtracted by the subtraction data SY. In addition, when the jump signal SX is input to the subtraction circuit 94, and the jump signal SX is output, the subtraction circuit 94 is configured such that the subtraction operation is prohibited.

In Fig. 5, the common counter value, the line address value in the normal mode, and the line address value in the Chinese character mode are displayed correspondingly. The operation of the line address generator 9 will be described below with reference to FIG.

First, in the normal mode, the common counter value is output as it is as a line address value.

On the other hand, in the Chinese character mode, when the common counter value is from 00 to 0F, this is output as a line address value sequentially. When the common counter value becomes 10, the jump signal SX is output from the interline decoder 91, and the line address value 30 in which the line address value 10 indicating the first line of the second line indicates the interspace space. Is changed to). This is realized by replacing the most significant bit 1 with three. At this time, since the subtraction circuit 94 does not operate, the line address value 30 obtained by the counter value forced change circuit 93 is output from the line address generator 9 as it is.

For the common counter values 11 to 20, line address values 10 to 1F for the second character string must be assigned. In the row block decoder 92, it is determined that the common counter values 11 to 20 should be subtracted by one, and the subtraction circuit 94 processes to subtract by one the common counter values 11 to 20. Is executed, and the resulting values 10 to 1F are sequentially output as line address values.

Next, the common counter value 21 displays the position corresponding to the interline space on the display panel in the interline decoder 91, and the value in place of the value 21 in the counter value forced change circuit 93. (31) becomes the line address value there. At this time, since the subtraction circuit 94 is prohibited by the jump signal SX, 31 is output as it is as a line address value.

For the common counter values 22 to 31, line address values 22 to 2F for the third character string must be allocated. In the row block decoder 92, it is determined that the common counter values 22 to 31 should be subtracted by two, and in the subtraction circuit 94, the processing to subtract by two to the common counter values 22 to 31 is performed. The resultant values 20 to 2F are sequentially output as line address values.

Since the position of the icon is displayed on the display panel with respect to the common counter value 32, it is output as it is as a line address value.

In accordance with the line address value obtained by the line address generator 9 as described above, the line data is read from 6, so that the data in the display data RAM 6 shown in Figs. 2 and 3 adds data for interline space. In one form, it is stored in the display data latch 10. In this way, the data prepared in the display data latch 10 is sent to the liquid crystal drive circuit 15, and when the common driver operates in accordance with the common data value in the common counter 14, as shown in Fig. 6, the display panel 1A. On the upper side, character display is performed over a plurality of lines in such a manner that space lines SL1 to SL2 are inserted between the lines of the first to third character display columns M1 to M3.

Since the line address generator 9 can be realized by a simple logic circuit, 16 dots of font data are written when writing 16 dots of font data into the display data RAM 6 as compared with executing a complicated program in a CPU as in the prior art. By simply dividing the data into eight dots and writing the data into the memory area designated by each page address and column address by eight bits, the interline space can be easily inserted without burdening the CPU.

According to the present invention, when font data is written to the display data RAM, a space can be provided and displayed between lines by simply dividing the font data into predetermined dots and writing them to the memory area designated by each page address and column address in units. Therefore, the burden on the CPU when writing the font data to the display data RAM may be small.

Claims (2)

The dot display data of the character font to be displayed is received, the dot display data of the character font to be displayed is expanded and stored in the storage area having the same configuration as the character display area in the display data RAM, and then stored in accordance with the common counter value in the common counter. The dot display data stored in the display data RAM is read in units of line data corresponding to one line of the character display area, latched in a display data latch, and synchronized with the common counter value data to display a dot matrix. In the display control method which makes a panel display on multiple lines, Space line data is stored in advance at a predetermined line address in the display data RAM, and the correspondence between the line address value and the common counter value for sequentially specifying and reading line data from the display data RAM is changed. And the space line data is inserted between rows on the display panel. A display data RAM which expands and stores dot display data of a character font to be displayed in a storage area having the same configuration as the character display area, a common counter for outputting a common counter value, and a display data RAM in response to the common counter value. A line address generator for generating line address values for reading dot display data as a plurality of line data, and latch means for sequentially latching line data read from said display data RAM in response to said line address values, A display control apparatus in which a required character is displayed on a plurality of lines on the display panel based on line data latched by the latching means in response to the common counter value. First discriminating means for determining, by the line address generator, whether a common counter value corresponds to a line address value for displaying interline space on the display panel; Second discriminating means for discriminating whether or not the common counter value corresponds to a line address value for the number of lines of character data on the display data RAM; On the basis of each discrimination result of the first and second discriminating means, for reading character display data from the display data RAM over a plurality of lines in a configuration in which space line data is added between lines in response to the common counter value, And correction means for correcting the common counter value to obtain address data, wherein the address data in the correction means is used as the line address value.