KR19990036644A - Field effect transistor - Google Patents

Abstract

It is disclosed to use a Mott transition to realize a metal-insulator transition in the form of a substantially three-terminal device with the function of a field effect transistor. The device uses a molecular array as the conduction channel, where the charge carriers (holes or electrons) are strongly correlated. The Mott transition determines metal-insulator switching and is known to be controlled by an external gate electrode. In other respects, the device appears to have electrical characteristics suitable for conventional silicon-based FETs. "On" state has a typical conductance of about 10e ² / h.

From the standpoint of breakdown voltage in the "on" conductance and "off" states, the performance of this device is satisfactory in circuit environments. The device can be constructed with a smaller dimension than a conventional FET, i.e., with a linear dimension of about one order of magnitude smaller. The device can be fabricated using a self-assembly technique that enables key steps of a multi-layer structure. Thus, a considerable number of transistors per chip can be assembled without the requirement of very small design rules. This is easily accomplished by the low voltage and power requirements of the device. Thus, the Mott Transition Field Effect Transistor (MTFET) is expected to provide a solution to the problem that arises when conventional silicon techniques are scaled to extremely high transistor densities.

Description

Field effect transistor

The present invention relates generally to semiconductor switches, and more particularly to field-effect transistors, and more particularly to Mott metal-insulator (MIT) insulators within a single-layer or multi-layered film of custom-designed bistable molecules. transition based nanoscale switch. < Desc / Clms Page number 2 >

Current computer circuits, i.e., logic circuits and dynamic random access memories (DRAMs) all consist primarily of field effect transistor (FET) switches. The number of transistors per chip on the market is known as the exponentially increasing time function (Moore's Law). Therefore, the number of stored bits per DRAM chip is also increasing exponentially according to Moore's Law. Moore's Law has several formulas: for example, the transistor density increases by a factor of 10 every five years, the computation time is reduced by six times every eight years, and the computation cost is reduced by ten times every eight years It is a formula. The main factor in Moore's Law is the exponential decay of the design rule over time. Thus, the reduction in design rules appears to be incompatible with the inherent physical limitations of silicon (Si) technology. From a technical point of view, two of the most important physical properties of silicon contrary to the material, namely the long carrier mean free path and doping ability, are becoming less important at very small scales, Is because the long carrier mean free path is comparable to or greater than the device dimensions like the spacing between dopants. So far, the minimum channel length revealed by the experiment is an order of 40 nm, which is considered to be closest to the achievable minimum channel length. Therefore, new techniques are required when design rules approach the 40 nm limit, as expected to occur after 10-20 years.

While these advantages for silicon have disappeared, the disadvantage, that is, the cost of the two-dimensional circuit array is increasing, because Moore's Law on memory capacity is based on Moore's Law on design rules and the investment cost It also means. A technique that can be implemented in a multilayer without being limited to two dimensions in silicon wafer technology will avoid this pressure on the investment cost by excluding the Moore's Law effect on the number of transistors per chip from the design rule.

Taking these into consideration, physics appears to be going in the direction of selecting a system with a shorter average free path and a higher carrier concentration, ie, metal. Now, the metal switching problem becomes an issue. The present invention provides a solution to the problem of constructing a 3-terminal device with higher carrier concentration, which exhibits the properties of the metal when in the " ON " state. Switching of this device is realized through the concept of a Mott metal-insulator transition in a correlated electronic system. At the same time, it appears that a somewhat three-dimensional configuration is possible within the fabricated structure by substantially extending the standard self-assembly concept. The device appears to have predicted electrical characteristics (i.e., a zero static gate current, a high "OFF" impedance, and a low "on" impedance) consistent with existing FET-based circuits.

Owing to these features and, most importantly, their functional feasibility in very small dimensions, the devices proposed here will provide a solution to the fundamental problems that the computer industry is expected to face in the next 10 to 20 years.

For some types of conductors, the conduction band is formed from a well-defined atom or molecular orbital. In cuprate superconductors, this role is in the Cu position d _{x 2 -y 2} Symmetric orbitals. In another example, K _n C ₆₀ , a triple degenerate set of the lowest unoccupied molecular orbitals (LUMO) of C60 plays a similar role. The simplest model for describing these materials is J. J. Hubbard, Proc. Roy. (Hubbard model), which is disclosed in U.S.A. Sci. (London) A276, 238 (1963), A277, 237 (1963), A281, 401 (1963), which is incorporated herein by reference.

In an essentially ordered system, such as a cuprate CuO ₂ plane, at least two possible global states of the system, i.e., insulators and metals, have been trampled into existence. These states are the yen. Metal-Insulator Transitions by N. Mott, Mott Transition, Taylor & Francis, London, 1990, which is incorporated herein by reference.

If there is exactly one electron (fill factor n = 1) per Cu site, the electrons can localize their activity range to the Cu location, which can lead to isolation properties. This localization is mainly caused by the strong intra-site Coulomb repulsion U between the two electrons in the same orbitals. Starting from a given configuration with one electron on every position, a single hopping process in which electrons are transferred to neighboring locations involves an energy penalty U. Thus, the electrons are effectively trapped in the potential wells of depth U, so that the electrons are localized. Such an insulator is referred to as a Mott insulator. It is not an insulator in the sense of a band structure in the sense that it is in fact a half-filled conduction band, but it is an insulator due to interaction U and a specific packing coefficient of unit value (1).

It is clear that there is a tendency to break down at a temperature greater than the localized painter U. Also, generally, U needs to be larger than the hopping integration t, which is a matrix element for transmitting a single electron to the nearest site (there is an exception to a simple square grid of two dimensions, (inequality) then involves a matrix element for an adjacent site.

Even if the occupancy state deviates significantly from the half-filling state, i.e. n = 1 ± δ, where δ is based on data from the cup rate and is greater than approximately 0.1-0.15, even in a large U, Lt; / RTI >

In the insulated state, there is a gap (gap between the upper and lower Hubbard bands) within the energy spectrum of order U in the larger U. In the conductive state, there is no gap as in the case of metal. Since the conduction state is a true metal, the conductance in a two-dimensional system can not be less than the 'minimum metal conductance' given by e ² / h. This value corresponds to a two-dimensional sheet resistance of order 20 k ?.

The semiconductor device according to any one of claims 1 to 3, wherein the source of the source and the drain of the source and the drain of the source are connected to each other. Can be produced. Thus, the gate controls whether or not a conductive path exists between the source and drain terminals, thereby making the device a gate controlled switch.

Figure 1a schematically depicts a side view of a three-terminal single chromophore single-layer Mott Transition field effect transistor with a single gate,

Figure 1B is a schematic diagram of a three-terminal single chromophore single layer Mott Transistor field effect transistor with double gates,

Figure 2 schematically shows a side view of a three-terminal single chromophore multi-layer Mott Transition FET with a single gate,

Figure 3 schematically shows a side view of a dual-gate 4-terminal dual chromophore single-layered Mott-Transistor FET,

FIG. 4 shows the energy diagram for the device shown in FIG. 1, in particular, FIG. 4A shows the molecular energy level in equilibrium for a p-type enhancement mode device, Figure 4c illustrates the drain-source bias for a p-type device with connected and calculated gates and sources, which has finite gate electrodes and handles electrodes and channels as thin plates. , ≪ / RTI > a plot of energy variation of the molecular energy level along the channel when _VDS is present,

Figure 5 shows the capacitance per molecule in the array through the capacitance for a continuous layer, where the solid line is for a single gate case (uniform dielectric constant epsilon _ox = epsilon), the dashed line represents the double gate case drawing,

FIG. 6 shows a potential distribution (solid line) and a hole carrier distribution along the source-drain channel, with FIG. 6A having a weakly biased drain with V _sat = 0.5V, V _DS = -0.25V, V _sat = 0.5V, V _DS = having -0.75V | V _DS |> V _sat of the drain in the pinch region of the pinch width 2nm near-drawing having off region,

7 is a graph of a drain-source voltage in a channel under a variable gate voltage corresponding to the source-end doping determined from equation (14), a current I _DS according to V _DS (-V)

8 is a diagram showing a potential distribution of a channel when a gate voltage V _G = 1 V exists at a zero carrier concentration, in which the channel length is regarded as L = 100 nm and the width of the oxide spacer is d _ox =

9 is a phase diagram of (y _e / d) versus V _G / V _T representing the isolated (off) edge region of the molecular layer, where d is the distance between the molecular layer and the gate,

10 is a schematic cross-sectional view of a stacked array of devices of the present invention,

11 is a schematic diagram of a standard Mott-Transition field effect transistor,

12 illustrates performance characteristics of a standard Mott-Transition field effect transistor;

DESCRIPTION OF THE REFERENCE NUMERALS

18: gate insulator 20: gate

100: Mott field effect transistor 110: Mott transition layer channel

114: source electrode 116: drain electrode

118: dielectric spacer layer 120: substrate

In the monolayer configuration of the first embodiment, that is the monochromophore of the enhancement mode, the channel is formed from a molecular monolayer located in the yz plane. The molecule M constituting the monolayer includes redox centers (also referred to as chromophores or cofactors) containing unstable electrons (or holes). More specifically, the redox center is characterized by having at least one active component that participates in an electronic processor (i.e., a Mott insulator-metal transition and current flow).

Figure 1a provides a simple example of a single gate form of a three terminal device whose essential elements are shown. First, the conductive channel 10 is composed of a two-dimensional molecular array 12 which needs to be a strongly correlated field in that it has a considerably large value for the parameter U. The channel contacts the leads of the respective source 14 and drain 16 on the left and right sides. The metal electrode separated by the insulating spacer 18 from the molecular layer or channel 10 forms the gate electrode 20. Suitable materials for the spacer 18 include oxides such as SrTiO ₃ . Basic device parameters include channel length L and width W, spacer thickness d _ox , molecular radius R _mol , in-plane molecular spacing A _mol , dielectric constant of the spacer layer ε _ox , dielectric constant of the filler and layer itself, , The ionization energy of the molecule with respect to the source / drain electrode Fermi level ε ₁ . The distance orthogonal to the channel 10 (from the channel to the gate) is defined in the x direction and the distance parallel to the channel 10 (from the source to the drain) is defined as the y direction and the in-channel direction Direction) is in the z direction.

The device may also have a double gate configuration as shown in FIG. 1B, assuming that the same material is used for the insulator on both sides of the channel with a dielectric constant epsilon. d is used for the thickness of the insulator measured from the center of the channel layer.

The material for the insulator may be inorganic or organic, but the single gate form is more compatible with the oxide technology for the spacer layer (field oxide). Although not necessarily essential, the insulating layers 18, 18 'in a double gate configuration may be made of different materials including organic materials, for example, polyimide.

The array (which is the same as the term used for the channel and the molecular layer) is in either a conducting state or an insulating state depending on the degree of utilization of the moving charge (carrier). When a predetermined potential is applied to the gate electrode, the carrier of the opposite polarity tends to be attracted to the channel. The density of the carriers in the channel is determined by the equilibrium between the gate potential and the electrostatic repulsion between carriers. The relationship between the concentration of carriers and the gate voltage V _G is derived below.

In the enhancement mode device, when no gate potential is present, the molecular level is in a stable equilibrium state with the source and drain electrodes having an odd integral number of electrons per molecule. In this charge state, electrons in the layer will be localized by the Mott transition (if the conditions for hopping integration t and temperature T are met). Regarding conduction between the source and drain electrodes, the device has an " OFF " state.

When a potential is applied to a single (or dual) gate, the charge of the opposite sign will be induced on the layer. If this potential is the appropriate sign and exceeds the threshold (typically 0.1-0.15 electrons or holes per molecule), the molecular layer will switch to conduction. Then, the device is in the " ON " state.

The feature of the "on" state of the enhancement mode device is that there is a short (one or a few milliseconds) non-conductive region at the edge of the channel. The carriers must tunnel through these edge regions.

To switch to the " on " state by either positive or negative voltage depending on whether the carrier is of the electron or hole type, the device may be of two types. These configurations are similar to n-channel and p-channel MOSFET devices and can be used in CMOS circuit configurations in a similar manner.

The monolayer configuration of the depletion mode monochromatic stage, which is the second embodiment of the device, is similar to the depletion mode semiconductor FET. When the gate potential is not present, the molecular structure in the device is unstable in the electronic structure having an integral number of electrons, but the molecular layer is ionized to form a carrier of 0.1-0.15 hole (p type) or electron (n type) Concentration. The device is then " on "

Applying the appropriate sign (positive sign for p type, negative sign for n type) and size, the intrinsic carrier concentration is removed and the layer is in the mote insulated state, i.e., the odd number of electrons per molecule Is turned off. Thus, such a device is essentially an "on" state and requires a gate potential to turn it into an "off" state, similar to a depletion mode FET. Depletion mode devices are not CMOS compatible but are compatible with multiple DRAM memory cell circuits. A technical advantage of the depletion mode device is that there is no isolation region at the edge of the conductive channel when the device is on. Instead, when the device is off, there is a conductive region at the edge of the channel, which has no other physical effect other than shortening the channel.

FIG. 2 shows only a multi-layer structure of an enhancement mode unperforated chromophore according to the third embodiment. The channel may be composed of crystalline or amorphous multilayer molecular assemblies instead of monolayers. In an enhancement mode device, the gate voltage will induce a conductive layer on the surface of a molecular solid, and this conductive layer has a width of one monolayer. Thus, the conductive channel is very similar to that formed in the case of a single layer. As a result of the breakdown voltage, the gate voltage required to switch from " off " to " on ", the width of the isolation region of the channel edge in the "on" conductance, Is similar to that for a single layer enhancement mode device. Multilayer depletion mode devices are not possible because the multilayered conductors can not be switched to an insulated state.

The tomographic configuration-enhancement mode of multiple chromophore groups of the fourth embodiment advantageously employs molecules having two or more chromophores or redox centers. In Fig. 3, a plurality of chromophore devices are shown in the form of two chromophore or bicomponent molecules. Many chromophore devices are essentially four terminal devices with two independent gate voltages. Briefly, the two chromophore devices function as follows. The two chromophores that make up the molecule form a redox pair. The simplest assumption is that one molecule V has an energy level for the source-drain Fermi level at -ε _i and the other molecule C has an energy level for the source-drain Fermi level at ε _i .

When the gate voltages are tied together (in common gate mode operation, which is common in dual gate devices), the device operates in a manner similar to the operation of a single chromophore MTFET. The gate voltages of? _i / e or? _i / e will each lead to a molecular layer to obtain n-type or p-type carriers. The gate voltage required for a 0.1-0.15 conductance threshold per molecule depends on the calculation of C _mol , as in the case of a single chromophore.

However, in the case of operation in the sifferential mode, if the gate is of the opposite polarity to the source and the drain (taken at the same zero voltage), the redox center C is directed upward, the redox center V is directed downward This polarity pushing will keep the layer insulated. However, the opposite polarity, which generally pushes the C and V levels together at a threshold for an integrated potential greater than 2ε _i , will inject an n-type carrier from V to the C-center and inject the p-type carrier from C to V-center. In addition, the conductance threshold is controlled by capacitive considerations.

The two chromophore devices have a phase space sufficient to control the " on " and " off " states. A major potential advantage is that CMOS circuits can be realized by a mode of merely connecting the gates in the differential mode, and no separate n-type and p-type devices are required.

The molecule M may have various forms and may have various chemical properties. In their simplest form, these molecules are true molecules, such as members of the Heme family (e.g., Fe switching between Fe ²⁺ and Fe ³⁺ states). More complex "molecule" is (X ⁺ TCNQ ^-) and includes a like charge transfer complexes (charge transfer complexes), wherein X is an alkali metal, an organic TCNQ tetrahydro-dicyano (tetracyano) -p- quinolyl nodi methane (quinodimethane ), And TCNQ is an active ingredient that switches between TCNQ ^- and TCNQ by hole injection.

More generally, the complexes for the enhancement mode device have a

1) a hole-based system X ⁺ A, wherein A is an organic acceptor such as TCNQ and C ₆₀ , and X is an alkali metal.

2) an electron-based system D ⁺ Y, where D is an organic donor (e.g., TTF, tetrathiofulvalene) and Y is a halogen.

3) a hole or electron based system D ⁺ A ^- where D is an organic donor such as bis-ethylenedithio-tetrathiofulvalene (BEDT-TTF) N ', N'-tetramethyl-p-phenylenediamine), and A is an organic acceptor such as TCNQ. There is no reason to exclude the conductive polymer as a useful material for the molecule M.

To further illustrate the device of the present invention, consider the device of FIG. 1A of a p-type enhancement mode. If no gate potential is present, the molecules of layer 10 become mote-insulated. In such a p-type enhancement mode device, when a sufficient negative voltage is applied to the gate, the molecules become positive charges and switch from the Mott insulator to the metal state, allowing conduction to the source and drains. In such a device, a material suitable for layer 10 comprises a charge transport complex between an alkali metal and a TCNQ.

On the other hand, if the device of Fig. 1A is an n-type enhancement mode device, the molecules of layer 10 are also in a mote-insulated state if no gate potential is present. When a sufficient positive voltage is applied to the gate, the molecules become negatively charged and switch from the Mott insulator to the metal state, allowing conduction to the source and drain. In such a device, a suitable material for layer 10 comprises a charge transfer complex between TTF and a halogen.

When the device of FIG. 1A is a p-type depletion mode device, the molecules of layer 10 become a metal conduction state if no gate potential is present, and when a sufficient positive voltage is applied to the gate, the molecules become positive charges, .

The case where the device remains in the "off" state when no external potential is present and the hole is a charge carrier in the conducting state (ie, the "on" state) instead of the electron will be used to characterize the device of the present invention. The characteristics of the device in isolation and conduction state will be described with a mechanism whereby the charge carrier can be controlled by the external gate voltage. The metal-insulator transition in the device enables switching between an " on " state and an " off " state.

First, to demonstrate that the device's "off" state is a mote isolated state, the device is designed to have one electron on average at each location in the array in equilibrium, if Equation 1 below is met. 4A, all of the electrons occupy a single degenerate energy level, which is defined as the energy < RTI ID = 0.0 _{> 1 < / RTI >} less than the Fermi level of the adjacent Fermi seas in the lead . Electrons in strongly correlated layer molecules receive strong coulomb repulsion when they approach each other. In particular, a state that allows two electrons on a single location has a very high energy U (U >> k _B T or some other energy scale). As a result, any dual occupancy is not efficiently allowed in this state, and electrons in the lead can not penetrate or pass through the array. In other words, the state that enables any double occupancy per position is eliminated by the gap of degree U (FIG. 4A). When the following equation (1) holds, the system maintains the mote insulator state in the thermal equilibrium state.

k _B T << ε ₁ and K _B T << U-ε ₁

With the application of the drain-source voltage, the system can not be easily driven into the metal state. 4C is a diagram showing an electronic energy diagram for the system in the presence of a negative bias voltage V _DS = -V. In practice, the negative drain-source voltage raises the energy of the electrons in the array adjacent to the drain end. When approaching the drain electrode, the variation of the electrostatic energy of Figure 4c follows the following analytical form.

Here, V _G is the gate voltage, δy is the distance from the drain electrode, d is (almost be considered to be a thin plate of infinity), the drain electrode and the distance between the gate electrode (that is almost considered to be a thin plate of infinity), oil Constants are taken as unit values. The singularity of the square root of this approximation is obvious in the numerical solution of Figure 4c.

The above calculation assumes a unit dielectric constant. When a uniform dielectric constant &lt; RTI ID = 0.0 &gt; epsilon &lt; / RTI &gt; is introduced, the voltage variation in the insulator of Figure 4c is reduced by a factor epsilon, but a potential jump appears at the electrode surface. This modified picture does not change the following description.

Even though the molecular energy level adjacent to the drain increases, electron transfer between the array and the drain or source is not allowed due to the in-situ Hubbard barrier under the condition of the following equation (fulfilled by the parameters shown in Figure 4C) .

e | V _DS | <U-ε ₁

In the case of electrons at the ionization level, in order to transfer certain electrons from the array to the source on the left side, it is necessary to call the predetermined state with double occupancy in the intermediate process, which requires energy of order U. Also, since the drain Fermi level is still below the upper Hubbard band, it is impossible for electrons to tunnel from the drain to the affinity level (upper Hubbard band). Thus, the system holds the Mott insulator while the condition of equation (3) is met. By replacing the continuous model of layers with a discontinuous model, the above description will not change qualitatively.

By applying a negative voltage between the overlapping gate electrode and the substrate, the array switches to the metal state once the ionization energy level (lower Hubbard band) moves above the Fermi level of the lead. The actual density of available charge carriers in the array at a given gate voltage also depends on the Coulomb interactions in the array.

It is assumed that the device is under negative gate voltages -V _G , V _G > 0 while the system remains in equilibrium. When the layer ionization level at the zero-carrier density e (V _G -ε ₁ ) relative to the source-drain Fermi level becomes positive, electrons in the array tend to be released into the leads, filling the layer with a positive charge. This charging tendency is contrary to the build up of electrostatic energy in the layer. The total electrical energy per molecule can be expressed as:

Where δ is the fractional positive charge per molecule (0 <δ <1), and C _mol is defined as:

In Equation 5, V _tot is the total potential (direct potential + induced potential) of the molecule of r ₀ generated in the molecule of r _i .

The potential derived from the molecule itself of r ₀ is not included in equation (5). This potential acts to renormalize ε ₁ (this potential reduces ε ₁ from the gas-phase value), but does not affect the second term in equation (4). It is assumed that the result of renormalization is defined as the value of δ ₁ .

If the dielectric constants of both regions are equal and equal to? Of the single gate case shown in FIG. 1A, equation (5) can be expressed as:

Here, the molecular layer is defined as being located in the yz plane, and _Rmol is the radius of the molecules in the layer.

When the intermolecular spacing a _mol much less than the distance between the molecule and the surface, which leads to continuous extreme value C of the C _{cont mol.} Then, the standard result is derived as follows.

Where n is the concentration of molecules per unit area.

In the case of a high dielectric functional oxide of epsilon _ox > e, Equation (6) can also be used at other extreme values. Now, if the amount of d _ox + R _mol is reduced to the molecular radius R _mol itself, then equation (6) becomes as follows.

As only a very accurate when the approximate interpolation between equation 6 and equation (8) is an intrinsic R _mol >> d _ox, is obtained by replacing the d _ox by the equation (6) to Equation (9).

With this equation, it is possible to roughly estimate C _mol for a predetermined value of d _ox in FIG. 1A.

5 is a diagram showing the value of C _mol as a function of the ratio of d = d _ox + R _mol to a _mol or d = R _mol to a _mol when the molecular arrays are dense monolayers. The ratio of d / a _mol may be less than 1/2 in equation (8), and C _mol may be much larger than the continuous limit of equation (7).

In the case of the double gate configuration shown in FIG. 1B, Equation 4 for the total static energy per molecule is still maintained, except that the capacitance per molecule is changed as follows.

Where p varies across all integers that sum up the infinite number of image charges.

The value of C _mol is also shown in FIG.

If Equation (4) is minimized for?, the following equation is derived as an equation to connect the gate voltage V _G to the ratio of carriers per molecule?.

V _G = V _T + e? / C _mol

Therefore, V _T = e ^-1 ε ₁ defines the minimum gate voltage required for the concentration of charge carriers in the molecular layer to be non-zero. The " on " gate voltage required for various parameter sets can be specified if &lt; RTI ID = 0.0 &gt; = &lt; / RTI &gt; = 0.15 is the typical carrier ratio required to be in an appropriately &quot; on & A value of order 0.25 eV (~ 10 k _e T at 300 K) is allowed for ε ₁ . These results are shown in Tables 1 and 2 for both single and double gate configurations.

d R _mol a _mol ε ε _ox δ V _G ^ES (V) V _G (V) 20 5 10 4 20 0.15 0.428 0.678 20 5 10 4 100 0.15 0.228 0.478 20 5 15 4 10 0.15 0.271 0.521 20 10 20 4 10 0.15 0.214 0.464 20 10 20 4 100 0.15 0.103 0.353 20 10 30 4 10 0.15 0.080 0.330

d a _mol ε δ V _G ^ES (V) V _G (V) 20 10 4 0.15 0.488 0.738 20 15 4 0.15 0.187 0.437 20 20 4 0.15 0.085 0.335

Summarizing these results, it is possible to operate on gate voltages between 0.4V and 0.8V. Assuming that U is in the order of 1-2 eV, this range is suitable to ensure that equation (3) is satisfied when the gate is driven by the source-drain voltage, and that the proposed device, according to a suitable design, Is considered to be.

For the sake of future engineering analysis, which relies on continuous processing of the array, the following definition is introduced for convenience (where n means the concentration of molecules per unit area in the array).

C ' _T = nC _mol'

Q ' _h = ne?

It should also be noted that the maximum number of holes available is limited to? 1. That is, the hole density in the array will remain unchanged at n for the gate voltage V _G ≥ V _T + ne / C ' _T. To illustrate this fact more clearly, V _G ⁰ Is defined as V _T + ne / C ' _T , Equation (11) is expressed again by Equation (14) below.

Note that the threshold voltage V _T is derived under the assumption that the hole distribution is uniform over the conduction channel in the device. If the device has a spacer with variable thickness over the channel from source to drain, this would be inaccurate. The hole distribution will also change when a finite drain-source bias voltage is applied. In this latter case, the situation is further complicated by the current flow through the conduction channel. In addition, when creating the static energy equation, i.e., equation (4), the edge effect at the array-lead contact on both sides is neglected but will be described in detail below.

In addition to neglecting the edge effect, the effect of the internal hopping constant t was also neglected. It is unlikely that t will be significantly greater than 100 mV for the molecular layer and that the kinetic energy effects (~ t) are small over the scale of the energy induced in Table 1, Do.

By applying an appropriate gate voltage, the interrelated field in the array can be switched from " off " to " on " Now, consider the current-voltage characteristic of the metal state when a drain-source voltage is present.

For a linear region, first consider that the device is at a low drain-source voltage V _DS . Under this condition, the gate-array bias and hence the charge (hole) distribution are substantially uniform along the entire conduction channel from the source 14 to the drain 16. The moving charge density of this system is approximately given by Equation (14).

The steady-state current driven by V _DS flows along the y-axis (i.e., source-drain direction). Therefore, according to Ohm's law, it can be expressed as follows.

Here, μ _h = eτ / m _h is a hole mobility assumed to be a constant. Therefore, at a given gate voltage, the channel conductance is constant at G _L = ∂I _DS / ∂V _DS . The dependence on V _G in equation (15) is entirely due to the variation of the available moving holes in the array. Now, there is an upper limit (one hole per position) in the hole density, as noted when deriving equation 14, which is a conventional insulator (contrary to motes), of the array being empty. Thus, the most effective channel conductance is between δ = 0 and δ = 1.

In the non-linear region, if the value of the drain-source voltage increases until it becomes negligible relative to the gate voltage V _G , the above-described analysis is no longer maintained. The finite drain-source voltage acts to vary the potential distribution along the conduction channel. Thus, the voltage between the gate and the channel, and the actual charge density, will be a function of the position y traveling from the source to the drain. In particular, when the drain is negatively biased with respect to the source, the threshold charge potential rises and effectively reduces the available hole density.

In order to obtain a quantitative picture of the current-voltage characteristic for any V _DS , a so-called gradual-channel approximation, which is widely used in semiconductor device physics, is used. In this approximation, it is assumed that the field in the current flow direction is much smaller (also slowly changing) than the field perpendicular to the array. Within this approximation, the voltage drop that increases with the channel as a function of (steady state) channel current is expressed as:

I _DS ∂y = μ _h WQ ' _h (y) ∂V _y

Here, Q ' _h (y) is the hole density at position y in the channel, which also varies from source to drain assuming that the mobility μ _h is constant, as deduced from the cuprate data. When the drain is negatively biased and V _DS = -V (V > 0), the hole-to-molecule ratio per molecule within the gradual channel approximation can be approximated by Equation 11, where V _T is the position- The voltage is replaced by V _T + V _y , and V _y changes at (0, V). The total charge carrier density per unit length along the channel at location y can be expressed as:

Q ' _h (y) = C' _T (V _G -V _T -V _y )

By combining equations (17) and (16), it becomes possible to evaluate the potential V _y at an arbitrary position y in the channel as a function of the uniform current I _DS as shown in the following equation.

The change in V _y and Q ' _h (y) according to the source-drain channel is shown in Figs. 6A and 6B, respectively, for a suitable and strong bias voltage. This also allows the integration path to be expressed as a function of the applied voltage, as in the following equation, by extending the entire path from the source to the drain.

Now, the current I _DS is a nonlinear function for the drain-source voltage V _DS (= -V). When the drain is negatively biased, the current gradually increases as the V _DS value increases, eventually reaching a maximum at -V _DS = V _SAT = V _G -V _{T as} in the following equation:

In the case of a conventional MOSFET, as can be readily seen from equation (17), when the drain is biased at -V _sat , the drain voltage is affected by the negative gate voltage to the associated electron near the drain end (Q ' _h (L) = 0) because there is no moving charge (hole) available.

When the drain is further biased such that | V _DS | > V _sat , a so-called pinch-off region appears near the drain electrode where there is no available carrier as shown in FIG. 6B. The current in the channel is maintained by injecting a charge carrier across the pinch-off region where strong electric fields are present. Of the current as shown in equation (19) size, the pinch-held at I _sat not reduced by the well-known negative feedback phenomena in silicon MOSFET environment current is cut off and the pinch zone itself disappears when the off region will be too wide Or slightly larger. 7 is a graph showing current-voltage characteristics at various gate voltages. In Fig. 7,? = 0.1-0.5 (representing from the bottom curve to the top curve). The current I _DS and the voltage V _DS appearing in the curves are respectively scaled for I ₀ = G _Tmax V ₀ and V ₀ = e / C _mol . The gate voltage is negative in the enhancement mode device and its value increases as it moves from the bottom to the top curve, and decreases as it moves from the bottom to the top curve in the depletion mode.

As can be seen from the expression (20), the hole current in the saturation region, I _sat , changes in a quadratic function according to the gate voltage. As the gate voltage becomes negative (or as V _G increases), the drain saturation voltage V _sat and the available charge carriers in the channel all increase linearly with V _G. Therefore, the transconductance defined by G _T = ∂I _sat / ∂ V _G is a linear function for the gate voltage as follows:

Where I refers to the average free path for charge carriers, n _h = k _f ² / 4π Is the hole concentration in the layer, and k _f is the corresponding waveform vector. For a system with I for some order of intermolecular distance, the transconductance G _T is on the order of some quanta of conductance. Because it corresponds to one of the two it is approximately 26KΩ resistance of the conductance e ² / h, thus the conventional saturation transconductance may correspond to kilograms Ω.

In a linear region under a small drain bias, the transconductance can not increase indefinitely as V _G increases, as the system becomes a conventional band insulator when the carrier density? Reaches one hole per molecule. Thus, G _T will reach a maximum at a predetermined intermediate doping value 0 <? ₀ <1. Assuming that the average free path is at a distance of several intermolecular distances, the maximum conductance is

Of the car. That is, it becomes several K?.

Thus, when a positive bias voltage is applied to the drain (V _DS > 0), the pinch-off region will not be generated and there will be no saturation region in the current-voltage curve under the positive drain-source bias. However, as the coupling effect of the gate and drain voltages becomes too strong, there is a possibility that the hole density will reach the upper limit in the channel near the drain end. Beyond these limits, the current will decrease rapidly, and the system will eventually become a conventional band insulator.

Focusing on the p-type enhancement mode device characteristics, an analysis for the n-type enhancement mode device can be performed along the same line. However, in the latter case, as shown in Fig. 4B, the energy level is reversed with the energy of the p-type device. That is, the upper Hubbard band is now involved in metal-insulator switching, and electrons become charge carriers instead of holes. Likewise, the device is in an " off " state at a zero gate voltage and is switched to an " on " state when a sufficiently large positive gate voltage is applied.

When conducted at V _G biasing the channel to the metal region in a low V _DS , tunneling through the edges, which may not be conductive, may limit the overall device conductivity. Continuous analysis of the effect can be done as follows.

In Fig. 8, the potential distribution of the channel is shown in which the channel is still in an insulated state (delta = 0) when a normal gate voltage is applied. The potential change at both ends can be approximated as follows.

Where? Y is the distance measured from the source (or drain) electrode and d is the distance between the molecular layer and the gate electrode. Equation 25 is still accurate even when the channel is conducted as long as? Y is very close to the electrode. Thus, it is expected that a small insulating region will be present at the edge of the molecular layer close to the source and drain electrodes.

9 is a phase diagram for determining the width of the insulating region at the edge. In the equilibrium state under a predetermined gate voltage -V _G , the part of the molecule layer which is in a conducting state has a potential -V _T. The phase diagram is shown in the y _e / dV _G / V _T parameter space, where y _e is the width of the insulating edge region. From FIG. 9, it should be noted that the insulating region tends to be confined only within one or more of the molecular diameters for a suitable and strong gate voltage. On the other hand, the entire layer is insulated with respect to the gate voltage V _G lower than the threshold voltage V _T , and the insulating region grows sharply as the gate voltage V _G approaches V _T from above, It is clear that the gate voltage must be sufficiently larger than the threshold voltage to prevent the effect. For example, when V _G = 2V _T , the edge area is ~ 10A for a 20A wide spacer.

Since the edge region is generally an order of one or two molecular diameters, while the barrier to the charge carrier (hole) is?? 0.25 eV, tunneling can easily occur and the edge region is very limited It is expected to have only an effect.

Assuming that the charge carrier confronts a triangular barrier in the edge region with an effective field of order ε = V _G / y _e , where y _e is the maximum barrier width determined from the phase diagram in FIG. 9, the tunneling conductance through the barrier is Can be easily calculated as shown in the following equation.

To calculate the order of magnitude of the conductance, it is assumed that? _F = 0.5 eV and device width W = 100 nm. Even for the undesirable selection of the parameters ε ₁ = 0.5 eV, V _G = 1.0 V (y _e ≈ 17 Å for d = 40 Å as can be seen from FIG. 8), the tunneling conductance is ~ ³ e ² / h Can be calculated to be large. On the other hand, assuming that? ₁ = 0.25 eV and V _G = 0.6 V, the barrier width becomes y _e ? 11 Å for d = 30 Å, and the conductance reaches ~25 _e ² / h.

To more precisely analyze the tunneling conductance, it is necessary to consider the barrier lowering effect of a substantial change in the potential of the edge area, as shown in equation ^{_{25, V im = -e 2 /}} 2πεδy image force that can be described as (force) have. The barrier height is expected to be lower by 3 (eV _G ) ^2/3 (2e ² / epsilon) ^1/3 / 2 pi, which is very large compared to the barrier height of? _L. Thus, for barrier widths of one or two molecular distances, as determined from the phase diagram of FIG. 8, the image force further increases the tunneling current and consequently reduces the possible edge effect. Consequently, the edge effect results in the device not having a significant effect on proper operation.

In addition to the enhancement mode version of the above-described single-layer transconductance switch, there is also a depletion mode version of the device, but such a depletion mode device is not suitable for CMOS applications because its gate potential is outside the range of source and drain potentials. However, depletion mode devices are expected to be useful because depletion mode versions are well suited for designing multiple DRAM memory cells.

Since the p-type depletion mode device is realized by making the molecular energy level? ₁ negative, the molecule tends to be ionized even without the gate potential. The zero-V _G carrier concentration is controlled by Equation 11, i.e.,? ₁ = -δ / C _mol , where V _G = 0.

For an " on " hole concentration of delta = 0.15, the required value of [epsilon] _l can be read from column 7 of Table 1. [

By making the gate voltage positive, the device can be put into the " off " state. The required voltage swing is the same as the last column in Table 1.

Thus, apart from the different tuning of &lt; RTI ID = 0.0 &gt;# ₁ &lt; / RTI &gt; and shift of the gate voltage (which is determined by Equation 11 from the carrier concentration), the device operates according to the characteristics of FIG.

An advantage of the depletion mode device is that there is no tunneling impedance at the edge of the channel. Since the channel is in the " on " state when there is no gate field, the molecule at the screen edge is always in the "on" state. Thus, whether the rest of the channel is in the " on " or " off " state, the edge molecule is in the conducting state and only in the " off " In memory applications, this advantage has been determined to be very important.

In the fabrication of a single gate device, metal electrodes and oxides (if present) are formed in the heat treatment. The molecular layer is then applied through a standard self-assembly process. This oxide process is limited to 2D technology, because if another oxide heat treatment occurs during the deposition of the next layer thereon, the molecular layer will probably be subjected to heat.

Double gate devices can be fabricated using organic insulators such as polyimide in all organic processes. This process can be used to build multi-layered structures. If the gate length is a 100 nm order (array of 100 x 100 molecules) and the number of layers is 32, then a storage capacity of order 10 ¹¹ bits is possible, and the capacity can be a risk for conventional technical resources.

The molecules making up the conduction channel in the device may be in the form of a single layer, or in the case of enhancement mode devices, in the form of an amorphous three-dimensional molecular array in which only the molecular layer closest to the crystalline or gate visible is forming a channel.

The surface of the insulator, which can be an oxide, must be ready to accept molecules. It needs to be in a flat state with a low step density. The surface can be cleaned or, in particular, in the case of a single-layer channel form of the device, such as " An Introduction to Ultrathin Organic Films, from Langmuir Blodgett to Self-Assembly ", A. Ulman, Academic Press, Boston (1991) May have a chemically active group selected to be suitable for the molecule to be assembled thereon as disclosed in J.Am. Chem. Soc., 117, 9529, 1995, the above-mentioned articles being incorporated herein by reference.

The process of assembling the molecules can be done by dissolving or vapor deposition, or by molecular beam or other process.

The self-assemblies of the monolayer are conducted using chemically incorporated groups within the molecule so that a monolayer can be attached to the surface or to a pre-attached chemical group.

The molecules may be attached by a Langmuir-Blodgett process or by a process that exposes the surface to a solution in which they are dissolved, or by other means. The dense and possibly ordered molecular layer is thereby attached to the surface in a highly adapted manner. Molecules should include a redox-active center that plays an important role in the function of the MTFET device in addition to the group that binds them to the surface.

Thus, a three-terminal device with a single-layer channel has been described which operates through a Mott transition referred to as a Mott-Transition Field Effect Transistor (MTFET). The device uses an array of molecules as the conduction channel, where the charge carriers (holes or electrons) are strongly correlated. The Mott transition determines metal-insulator switching and is known to be controlled by an external gate electrode. In other respects, the device appears to have electrical characteristics corresponding to conventional silicon-based FETs. "On" state has a typical transconductance ~10e ² / h.

An important criterion when selecting potential candidate molecules for the molecular layer is (on-site) Coulomb repulsion U. The proper operation of the MTFET within the logic environment requires that the Coulomb interaction U in the device environment be at least 1.5-0.75 eV for each molecule within the radius range 0.5-1 nm.

In summary, the Mott-to-Transition field-effect transistor has the following features and advantages. A feature of the Mott Transition device is that it allows a relatively short average free path of about four lattice spacings using a high carrier density. Since a high purity ordered material is not required as in the silicon technique, the manufacturing process can be simplified. The device can operate with a minimum absolute magnitude value of the Carrier Average Free Path Carrier if there is an available carrier greater than one. Thus, a minimum size for a 4x4 array order (e.g., 4nm x 4nm with lattice spacing) should be possible. The number of carriers in a 4x4 array is at a time of two carriers at any time, which is also close to the lower limit of device operation. This minimum size provides a 100 times greater mounting density than a typical minimum size FET. The " on " resistance is independent of magnitude, for example orders of magnitude of the quantum conductance of several K [Omega], which is considered appropriate in logic and memory applications. The operating voltage is about 0.5V, which will significantly reduce the ohmic heating below the current state while still at room temperature for noise. The device can be fabricated in n- and p-type, etc., enabling the implementation of CMOS techniques.

Depletion mode devices that are unsuitable for CMOS applications are still well suited for DRAM environments. The advantage is that there is no edge effect in the "on" state, and this edge effect appears in the "off" state, which is harmless. The depletion mode configuration can be selected and used in response to a significant edge problem.

The device can be constructed as a stacked array by successively applying a monolayer from a solution, for example by a standard self-assembly technique, as shown in Fig. 10, after which an insulator and an electrode are deposited thereon. The array of this device (as previously defined) is in the yz plane, and the stack of arrays is in the x-direction. This process type is particularly practical for dual-gate, all organic type devices. The bit density achievable with the stacked array DRAM technique is expected to be in the range of 10 ¹¹ -10 ¹² , depending on the boldness of the design rule. Stacked array logic devices are also possible. Excitations across the HOMO-LUMO gap in the molecule are not required for device functionality (as distinguished from organic LEDs), thus increasing device lifetime. In FIG. 10, layer 22 is planarizing the insulator, and layer 24 is a grounded screening plane that prevents interference between devices in the stack. A single gate variant of the stacked array is formed by removing the gate 20 and the second oxide layer 18 'adjacent thereto.

Figure 11 shows a cross-sectional view of the type shown in Figure 2 (i.e., multilayer, single gate) having source electrode 114, drain electrode 116, gate electrode 120, gate insulator 118 and channel 110 Lt; RTI ID = 0.0 &gt; 100 &lt; / RTI &gt; As described above, the cup rate forms some of the materials that exhibit the mart metal-insulator transition. This forms a cuprate suitable for use as the molecular layer of Figs. 1A, 1B and 2. In addition, the cup-rate, Fig. 1a, 1b, and a high dielectric constant as shown in Fig strontium titanate is a suitable material for use as a gate insulator (18) of 2 (SrTiO ₃₎ and Ba _1-x Sr _x TiO ₃ oxide and It is very appropriate to be integrated together. The standard device 100 shown in Fig. 11 is opposite to the production sequence described below.

The device 100 is grown on a niobium doped strontium titanate (Nb-SrTiO ₃ ) substrate 120. Niobium doping causes the substrate 120 to be in a conducting state. Substrate 120 is the gate electrode in device 100. The dielectric spacer layer 118, which is approximately 1800A thick, has grown epitaxially on the substrate 120 by a standard self-assembly process of laser-stripping single crystal deposition of strontium titanate in a vacuum deposition chamber. It has been found that a deposition process must be performed with oxygen in order to obtain good dielectric properties, such as high breakdown voltage, low leakage current, and high dielectric constant, for the gate insulator spacer layer 118. The oxygen pressure for standard device 100 was approximately 300 milliTorr. Without removing the device from the laser evacuation vacuum deposition chamber, a 200 angstrom thick Mott Transition Layer channel 110 consisting of a cuprate Y _0.5 Pr _0.5 Ba ₂ Cu ₃ O _7-δ was injected onto the device with an oxygen partial pressure (here approximately 4 milliTorr ) Epitaxially grown on the gate insulator layer 118 by a standard self-assembly process of laser ablation single crystal deposition. This allows control of the stoichiometry of the Mott Transition Layer channel 110 having the desired properties and having a layered sheet resistance. Thereafter, the source electrode 114 and the drain electrode 116 were deposited on the cuprate-mart transition layer 110 by electron beam divergence through a contact mask. The source electrode 114 and the drain electrode 116 have a thickness of 2000 angstroms and are platinum of 50 microns by 50 microns. Standard device 100 has a channel length of 5 microns and a channel width of 50 microns. Since the ratio of the source and drain electrode regions to the thickness of the cuprate layer is large, the conduction to the cuprate mobility transition layer is most affected by the layer in the gate field, i.e. the cuprate / titanate interface.

A performance test of a standard Mott-Transition FET was performed with a grounded source electrode 114. The drain current was determined as a function of the drain voltage for the variable gate voltage. The performance of the standard Mott-Transition FET is shown in Fig. In Figure 12, the drain current is again indicated by the drain voltage. Each curve in Fig. 12 represents a different gate voltage. The performance data of Fig. 12 clearly shows the switching of the device from the off state (high resistance) at the positive gate voltage to the on state (low resistance) at the negative gate voltage.

Although the physical parameters of a standard device are not considered to be appropriate, standard devices clearly show that the motto transition device is practical and can perform key switching.

As a result of the proven epitaxial growth in the standard device, it becomes now possible to build a three-dimensional stacked array of the device type shown in Fig. In such a structure, for example, the source, drain and gate electrodes can be formed by selective ion implantation of the insulating spacer layer by techniques known in the art. Such an array is not found in conventional silicon techniques because it is difficult to epitaxially grow good quality silicon channels on top of the oxide material.

La ₂ CuO ₄ and Y _0.6 Pr _0.4 Ba ₂ Cu ₃ O _{7 -δ} are suitable materials to be used as the moth transition channel 110. Thus, it is possible to use a wide range of materials including those having the general molecular formula Y _{1 -X} Pr _x Ba ₂ Cu ₃ O _7-δ , La _2-x Sr _x CuO ₄ and La _2-x Ba _x CuO ₄ (where 0 ≦ _x ≦ 1) Lt; RTI ID = 0.0 &gt; 10 &lt; / RTI &gt;

All of this allows multilayer (i.e., low cost), low power, and small size fabrication for the FET technology described above. These are the specific requirements for future technologies, and extrapolation of existing silicon technology will not meet them.

The present invention occurs when scaling to extremely high transistor density in existing silicon techniques, using a Mott transition to realize a metal-insulator transition in the form of a substantial three-terminal device with the function of a field effect transistor Provides a solution to the problem.

Claims (74)

A field effect transistor comprising a source electrode, a drain electrode, and a gate electrode having a conduction channel between the source electrode and the drain electrode, Wherein the conduction channel comprises a two-dimensional array of at least one molecular layer, The channel is separated from the gate electrode by an insulating spacer layer, Wherein a metal metal-insulator transition in the molecule can occur. The method according to claim 1, Wherein the molecule is a redox centers comprising an a labile electron. 3. The method of claim 2, Wherein the molecule is a D ⁺ Y ^- type, D ⁺ is an organic donor, and Y ^- is a halogen ion. 3. The method of claim 2, Wherein the molecule is a D ⁺ A ^- type, D ⁺ is an organic donor, and A ^- is an organic acceptor. The method of claim 3, Wherein D ⁺ is TTF and Y ^- is Br. 5. The method of claim 4, Wherein D ⁺ is BEDT-TTF, and A ^- is TCNQ. The method according to claim 1, Wherein the molecule is a redox center comprising unstable electrons. 8. The method of claim 7, Wherein the molecule is of the X ⁺ A ^- type, X is an alkali metal, and A is an organic acceptor. 8. The method of claim 7, The molecule is D ⁺ A ^- type is, D ⁺ is an organic donor and A ^- is an organic acceptor is a field effect transistor. 9. The method of claim 8, Wherein X ⁺ is an alkali metal, wherein the A ^- C ₆₀ is a field effect transistor. 9. The method of claim 8, Wherein X ⁺ is an alkali metal, and A ^- is TCNQ. 10. The method of claim 9, Wherein D ⁺ is TMPD, and A ^- is TCNQ. The method according to claim 1, Wherein the insulating spacer layer is an oxide. A field effect transistor comprising a source electrode, a drain electrode, and a first gate electrode and a second gate electrode having a conduction channel between the source electrode and the drain electrode, Wherein the conduction channel comprises a two-dimensional array of at least one molecular layer, The channel being separated from the first gate electrode by a first insulating spacer layer and separated from the second gate electrode by a second insulating spacer layer, Wherein a metal-insulator transition can occur in the molecule. 15. The method of claim 14, Wherein the molecule is a redox center comprising unstable electrons. 16. The method of claim 15, Wherein the molecule is a D ⁺ Y ^- type, D ⁺ is an organic donor, and Y ^- is a halogen ion. 15. The method of claim 14, The molecule is D ⁺ A ^- type is, D ⁺ is an organic donor, A ^- is a field effect transistor an organic acceptor. 16. The method of claim 15, Wherein D ⁺ is TTF and Y ^- is Br. 18. The method of claim 17, Wherein D ⁺ is BEDT-TTF, and A ^- is TCNQ. 15. The method of claim 14, Wherein the molecule is a redox center comprising unstable electrons. 21. The method of claim 20, Wherein the molecule is of the X ⁺ A ^- type, X is an alkali metal, and A is an organic acceptor. 21. The method of claim 20, The molecule is D ⁺ A ^- type is, D ⁺ is an organic donor and A ^- is an organic acceptor is a field effect transistor. 22. The method of claim 21, Wherein X ⁺ is an alkali metal, wherein the A ^- C ₆₀ is a field effect transistor. 22. The method of claim 21, Wherein X ⁺ is an alkali metal, and A ^- is TCNQ. 23. The method of claim 22, Wherein D ⁺ is TMPD, and A ^- is TCNQ. 15. The method of claim 14, Wherein the molecule is multichromophores. 27. The method of claim 26, Wherein the molecule is a dual chromophore. 15. The method of claim 14, Wherein the first insulating layer is an oxide and the second insulating layer is an oxide. 29. The method of claim 28, Wherein the oxide of the first and second insulating layers is the same. 30. The method of claim 29, Wherein the oxides of the first and second insulating layers are different. 14. The array of claim 14 wherein the transistors are stacked. 32. The method of claim 31, Wherein the array is a logic device. 32. The method of claim 31, Wherein the array is a memory device. An array in which the transistors of claim 1 are stacked. 35. The method of claim 34, Wherein the array is a logic device. 35. The method of claim 34, Wherein the array is a memory device. 3. The method of claim 2, Wherein the material is a cuprate. 16. The method of claim 15, Wherein the material is a cuprate. 39. The method of claim 37, The cup rates _{Y 1-X Pr x Ba 2} Cu 3 O 7-δ (0≤X≤1) is a field effect transistor. 39. The method of claim 38, The cup rates _{Y 1-X Pr x Ba 2} Cu 3 O 7-δ (0≤X≤1) is a field effect transistor. 39. The method of claim 37, The cup rate _{La 2-X Sr x CuO 4} (0≤X≤1) is a field effect transistor. 39. The method of claim 38, The cup rate _{La 2-X Sr x CuO 4} (0≤X≤1) is a field effect transistor. 39. The method of claim 37, The cup rate _{La 2-X Ba x CuO 4} (0≤X≤1) is a field effect transistor. 39. The method of claim 38, The cup rate _{La 2-X Ba x CuO 4} (0≤X≤1) is a field effect transistor. 40. The method of claim 39, Wherein the cup rate is Y _0.5 Pr _0.5 Ba ₂ Cu ₃ O _{7 -δ} . 41. The method of claim 40, Wherein the cup rate is Y _0.5 Pr _0.5 Ba ₂ Cu ₃ O _{7 -δ} . 42. The method of claim 41, Wherein the cup rate is La ₂ CuO ₄ . 43. The method of claim 42, Wherein the cup rate is La ₂ CuO ₄ . 14. The method of claim 13, SrTiO ₃ and the oxide is a field effect transistor. 14. The method of claim 13, Wherein the oxide is Ba _1-X Sr _x TiO ₃ . 29. The method of claim 28, SrTiO ₃ and the oxide is a field effect transistor. 29. The method of claim 28, Wherein the oxide is Ba _1-X Sr _x TiO ₃ . A field effect transistor comprising a substrate, a source electrode, a drain electrode, and a gate electrode having a channel between the source electrode and the drain electrode, The channel comprising an array of at least one layer of material from which a metal-insulator transition can occur, The channel being separated from the gate electrode by an insulating spacer layer, Wherein the electrode, the insulating spacer, and the channel are epitaxially grown. 54. The method of claim 53, Wherein at least one layer of the material comprises a redox center comprising unstable electrons. 54. The method of claim 53, Wherein at least one layer of the material is a cuprate. 56. The method of claim 55, The cup rates _{Y 1-X Pr x Ba 2} Cu 3 O 7-δ (0≤X≤1) is a field effect transistor. 56. The method of claim 55, The cup rate _{La 2-X Sr x CuO 4} (0≤X≤1) is a field effect transistor. 56. The method of claim 55, The cup rate _{La 2-X Ba x CuO 4} (0≤X≤1) is a field effect transistor. 57. The method of claim 56, Wherein the cup rate is Y _0.5 Pr _0.5 Ba ₂ Cu ₃ O _{7 -δ} . 58. The method of claim 57, Wherein the cup rate is La ₂ CuO ₄ . 54. The method of claim 53, SrTiO ₃ and the oxide is a field effect transistor. 54. The method of claim 53, Wherein the oxide is Ba _1-X Sr _x TiO ₃ . 53. An array of claim 53 wherein the transistors are stacked. A field effect transistor comprising a substrate, a source electrode, a drain electrode, and a first gate electrode and a second gate electrode each having a channel between the source electrode and the drain electrode, The channel comprising an array of at least one layer of material from which a metal-insulator transition can occur, The channel being separated from the first gate electrode by a first insulating spacer layer and separated from the second gate electrode by a second insulating spacer layer, Wherein the electrode, the insulating spacer, and the channel are epitaxially grown. 65. The method of claim 64, Wherein at least one layer of the material comprises a redox center comprising unstable electrons. 65. The method of claim 64, Wherein at least one layer of the material is a cuprate. 67. The method of claim 66, The cup rates _{Y 1-X Pr x Ba 2} Cu 3 O 7-δ (0≤X≤1) is a field effect transistor. 67. The method of claim 66, The cup rate _{La 2-X Sr x CuO 4} (0≤X≤1) is a field effect transistor. 67. The method of claim 66, The cup rate _{La 2-X Ba x CuO 4} (0≤X≤1) is a field effect transistor. 68. The method of claim 67, Wherein the cup rate is Y _0.5 Pr _0.5 Ba ₂ Cu ₃ O _{7 -δ} . 69. The method of claim 68, Wherein the cup rate is La ₂ CuO ₄ . 65. The method of claim 64, SrTiO ₃ and the oxide is a field effect transistor. 65. The method of claim 64, Wherein the oxide is Ba _1-X Sr _x TiO ₃ . 64. The array of claim 64 wherein the transistors are stacked.