KR19990031016A - Device for continuous data transmission of data processing system - Google Patents

Abstract

The present invention relates to an apparatus for controlling 16 bytes of data between a CPU and a pair of data memories (DRAM) in a continuous transfer mode in a data processing system. The apparatus includes an up counter 410 that performs an up count operation according to an input clock CLK. The up counter is a counter initialization signal ( Receive the up counter 410 initialized to the value of the pair of binary signals provided to the up counter, the pair of binary signals and the output signal of the counter 410, and at every clock period. And a multiplexer 420 that alternately selects the pair of binary complementary signals and the count output signal of the counter in response to a variable output selection signal CAS to generate as the sequential address generation signal. The address decoder 50 alternately generates an address signal for selectively accessing each of the first and second DRAMs in response to the sequential address generation signal provided from the multiplexer 420, thereby generating 16 bytes of data every 5 clock cycles of the CPU. Continuous transmission of data is possible.

Description

Device for continuous data transmission of data processing system

The present invention relates to data transfer in a data processing system, and more particularly, to a data continuous transfer control apparatus for continuously transferring data in a DRAM by accessing a DRAM at a high speed in accordance with an operating clock speed of a CPU in a data processing system.

In general, since a DRAM, which is a data storage medium, has a significantly slower operation speed than a CPU, which is a control device, a pair of module DRAMs are used in a data processing system. The capacity of such DRAM is represented by 2 ⁿ * m, where n is the number of address bits and m is the bit data word stored at each storage location in the DRAM selected by the address. Data transfer operations such as data access, cache line filling, and cache line push performed by the CPU to DRAM are available in two ways: burst-inhibit transfer and continuous transfer. (Burst Transfer).

For example, assuming that the number of address bits is 22, and the bit data word is 32 bits, and the CPU has 16 bytes access to the DRAM, the discontinuous transfer method transfers the 32 bit data word once every two clocks, and 16 8 clocks are required for byte transfers. On the other hand, in the continuous transmission method, 32-bit data transmission occurs once per clock, and 16 clocks require 5 clocks. In the prior art, when the CPU accesses the DRAM, the DRAM is selected using the most significant bit of the address to secure the memory space. This conventional technique is easy to expand the memory, but the access speed of the DRAM is fixed, so that when the CPU operating frequency is increased, continuous transfer cannot be performed when 16 bytes are accessed, and the continuous transfer must be performed. In the case of discontinuous transmission, the CPU unnecessarily waits.

Therefore, the present invention uses DRAM pairs of least significant bits of the address generated by the CPU of the data processing system to alternately select a pair of DRAMs so that the DRAM data can be continuously transferred in the DRAM without degrading the operation speed of the CPU. It is an object to provide a control device.

In the data processing system according to the present invention for achieving the above object, a data continuous transmission control apparatus between a CPU and a data memory includes: a pair of first and second DRAMs respectively transmitting predetermined data for each clock; Addressing means for alternately generating an address signal for selectively accessing each of said first and second DRAMs in response to a sequential address generation signal; An up counter for performing an up count operation according to an input clock, wherein the up counter is initialized to a value of a pair of binary signals provided to the up counter according to a counter initialization signal; Receiving the pair of binary signals and the output signal of the counter, and alternately selecting the pair of binary signals and the count output signal of the counter in response to an output selection signal that is variable every clock cycle, thereby generating the sequential address. And a multiplexer provided to the addressing means as a generation signal.

1 is a schematic block diagram of a DRAM data continuous transfer control apparatus of a data processing system constructed in accordance with the present invention;

FIG. 2 is a detailed block diagram of the DRAM data continuous transfer control device shown in FIG. 1;

3 is a continuous transfer timing diagram of a DRAM data continuous transfer control apparatus of a data processing system according to the present invention;

<Description of Symbols for Main Parts of Drawings>

40: continuous transmission control signal generator 50: address decoder

410: up counter 420: multiplexer

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Referring to Fig. 1, a block diagram of a DRAM data continuous transfer control device of a data processing system constructed in accordance with the present invention is shown.

As illustrated, the DRAM data continuous transfer control apparatus according to the present invention includes a CPU 10, a pair of DRAMs 20 and 30 each configured as a module RAM, a continuous transfer control signal generator 40, and an address decoder 50. It includes.

The capacity of each DRAM 20, 30 is 2 ⁿ * m, where n is the number of address bits and m is the bit data word stored at each storage location in the DRAM selected by the address. In the embodiment of the present invention, it is assumed that the number of address bits n is 22 and the bit data word m is 32 bits.

The CPU 10 reads / writes signals to perform 16 byte access, cache line filling, and cache line push operations for continuously reading 16 bytes from each of the DRAMs 20 and 30 in a continuous transfer manner. ) Is provided to the DRAMs 20 and 30, and the address signals A0 to A31, the line size signals SIZ0 and SIZ1, and the transfer start signal ( A control signal such as) is generated to the continuous transmission control signal generator 40.

The continuous transmission control signal generator 40 controls the control signal provided from the CPU 10 ( In response to SIZ0, SIZ1, A2, and A3, a DRAM selection signal ELA2 and a sequential address generation signal ELA3 are generated. The DRAM selection signal ELA2 and the sequential address generation signal ELA3 are provided to the address decoder 50 of the next stage.

The address decoder 50 typically designates the memory location of each DRAM 20, 30 using 11 bits A [4 ... 24] of the address signals A0-A31 provided from the CPU 10. As a means for generating an address, a signal for selecting each of the DRAMs 20 and 30 is generated according to the DRAM selection signal ELA2, and a column address signal MA [0] generated in response to the sequential address generation signal ELA3. 10] are alternately provided to each of the first and second DRAMs 20, 30 so that the first and second DRAMs 20, 30 are selectively accessed.

FIG. 2 is a detailed configuration diagram of the continuous transmission control signal generator 40 shown in FIG. 1, and the continuous transmission control signal generator 40 includes an up counter 410 and a multiplexer 420.

The two least significant bit address signals A2 and A3 are input to the two input terminals D0 and D1 of the up counter 410 and the first input terminals A0 and A1 of the multiplexer 420. The transfer start signal TS from the CPU 10 is input to the control signal load terminal LD of the up counter 410. The up counter 410 performs an up count operation according to the input clock CLK, and transmits a start signal. ) Is used as a signal to initialize the up counter 410 with the value of a pair of input (A2, A3) bits provided to the up counter 410. The count value output by the up counter 410 is input to the second input terminals B0 and B1 of the multiplexer 420.

On the other hand, the AND gate 450 logically operates the column address strobe signal CAS via the (SIZ0, SIZ1) and the inverter 440 provided from the CPU 10. The column address strobe signal CAS is a signal generated by the address output of the CPU 10 and the clock CLK. The column address strobe signal CAS is a column address for each DRAM when the low level is asserted as described below. It is used to generate the latching (or strobe) signal DCASB [0-7]. This signal CAS is repeatedly generated opposite to the row address strobe signal RAS latching the row address every clock cycle. Thus, this signal CAS is used as a selection control signal that causes the multiplexer 420 to alternately select two inputs. The output of the AND gate 450 is provided to the enable terminal EN of the up counter 410 to be used as a signal for enabling the up count 410, and also to the select terminal S0 of the multiplexer 420. An output is provided to the multiplexer 420 to perform an input signal selection operation.

The multiplexer 420 selects the output of the least significant bit address signals A2 and A3 provided to the first input terminals A0 and A1 and the up counter 410 provided to the second input terminals B0 and B1 according to the selection signal S0. And output as (ELA2, ELA3) through the output terminals Z0, Z1. The (ELA2) signal is provided as DRAM selection signals DCASB [0-3] and (DCASB [4-7]) for sequentially selecting the DRAMs 20 and 30, and (ELA3) is an address decoder (Fig. 1). 50 as a sequential address generation control signal. Since the signals ELA2 and ELA3 count up every clock CLK, ELA2 is toggled every clock. Thus, two DRAMs 20 and 30 are selected one by one every clock. Therefore, one DRAM is alternately accessed two clocks once.

Hereinafter, the operation of the continuous transmission control unit 40 of the present invention will be described in detail as follows with reference to the timing diagram of FIG. 3.

As shown in the timing diagram of FIG. 3, the continuous transfer operation starts in cycle C1. During the first half cycle of cycle C1, CPU 10 generates valid address signals A0-A31 via address bus 60, and read / write signals ( ) Is generated in a high state, and the size signals SIZ0 and SIZ1 are generated. The least significant two bits A2 and A3 of the valid address signals A0 to A31 are provided to the continuous transmission control signal generator 40.

The CPU 10 transmits a transfer start signal (notifying the start of the bus cycle during the cycle C1). Assert). This signal ( ) Is maintained for one cycle of the first half cycle period of cycle C2 after cycle C1.

Transmission start signal used as counter initialization signal ( The up counter 410 is initialized to the bit values (1, 0) of the address signals A2 and A3 as a result of applying the up counter, and performs an up counting operation from the initialization value according to the clock CLK. At this time, the output of the AND gate 450 outputs an alternating signal which repeats 0 and 1 according to the column address strobe signal CAS, and this alternating signal becomes invalid after the cycle (SIZ0.SIZ1) signal C5. It is valid for 4 cycles (C2-C5).

On the other hand, the multiplexer 420 receiving the bit values 1 and 0 of the address signals A2 and A3 and the output of the counter 410 has its output terminals Z0 and Z1 in accordance with the alternating output signals of the AND gate 450. The bit values 1 and 0 of the address signals A2 and A3 and the output values of the counter 410 are generated as bits ELA2 and ELA3 of the DRAM selection signal and the sequential address generation control signal. The two bit signals ELA2 and ELA3 are generated as (1, 0), (0, 1), (1, 1), (0, 0) for four cycles. The address bits A2 and A3 are not predetermined values but the head address values that the CPU 10 attempts to access 16 bytes. Thus, the values of the address bits A2 and A3 do not change until the transfer is completed and are sequentially increased as illustrated at the bottom of the timing diagram of FIG. For example, if the (A3, A2) bits are (0, 0), the (ELA3, ELA2) bits are (0, 0), (0, 1), (1, 0), (1, 1), and ( If A3, A2) bit is (1, 0), (ELA3, ELA2) bit becomes (1, 0), (1, 1), (0, 0), (0, 1), and (A3, A3) Bit is (1, 1), the (ELA3, ELA2) bits will be (1, 1), (0, 0), (0, 1), (1, 0).

Therefore, the address decoder (see Fig. 1) alternately provides an address signal to each of the DRAMs 20 and 30 in accordance with the DRAM selection signal and the sequential address generation control signals ELA2 and ELA3. As a result, the DRAMs 20 and 30 are alternately selected one by one every two clocks as the operating frequency of the CPU 10, and the CPU 10 accesses 32 bits of data once per clock so that the 16-byte access operation is five. It can be performed every cycle.

However, when the CPU does not perform continuous transfer of 16 byte access, the output of the AND gate 450 is generated because (SIZ0, SIZ1) is generated from the CPU 10 as an invalid signal, that is, a low level ("0"). The up counter 410 does not perform the count operation. Therefore, the multiplexer 420 passes the address signals A2 and A3 as it is and performs normal operation.

According to the present invention, if the DRAM has an access time of at least twice the operating frequency period of the CPU, operations such as 16 byte access, cache line filling, and cache line push can be used as continuous transfers, thereby reducing unnecessary latency of the CPU. It can be effective.

Claims (3)

In the data continuous transfer control device between the CPU and the data memory in the data processing system, A pair of first and second DRAMs each transmitting predetermined data for each clock; Addressing means for alternately generating an address signal for selectively accessing each of said first and second DRAMs in response to a sequential address generation signal; An up counter for performing an up count operation according to an input clock, wherein the up counter is initialized to a value of a pair of binary signals provided to the up counter according to a counter initialization signal; Receiving the pair of binary signals and the output signal of the counter, and alternately selecting the pair of binary signals and the count output signal of the counter in response to an output selection signal that is variable every clock cycle, thereby generating the sequential address. And a multiplexer provided to said addressing means as a generation signal. The method of claim 1, The counter initialization signal is a transfer start signal that is asserted during a half period of the first clock generated from the CPU. Data continuous transmission control device characterized in that. The method of claim 1, And said pair of binary signals are a pair of least significant address signals (A2, A3) generated from said CPU during data continuous transfer control between said CPU and said data memory.