KR19990030207A - Selective hemispherical grain electrode for increasing capacitance - Google Patents

Abstract

An integrated circuit is provided that includes at least one capacitor 10. Capacitor 10 includes a first capacitor contact 12 and a capacitance increasing layer 16 disposed outwardly from the first capacitor contact. The capacitive enhancement layer 16 includes a material that is lattice mismatched to silicon. The capacitor 10 further includes a second capacitor contact 20 disposed outwardly from the first capacitor contact and separated from the first capacitor contact by a capacitor dielectric layer 18.

Description

Selective hemispherical grain electrode for increasing capacitance

BACKGROUND OF THE INVENTION The present invention relates generally to electronic devices, and more particularly to methods and apparatus for increasing capacitance.

Capacitors are now becoming an important device for integrated circuits, particularly devices such as DARM cells. Downscaling DRAM cells makes it difficult to ensure sufficient capacitance in the small cell area available. As devices grow smaller and memory capacity increases, it is desirable to provide large capacitance storage devices that take up minimal board space. One approach to increasing capacitance per unit area of a substrate is to extend storage nodes vertically from the substrate. While this approach increases the capacitance per unit area of the substrate, it introduces difficulties in patterning and optical delineation problems.

Another approach to increasing the capacitance per unit area of the substrate is to deposit a rough hemispherical grain polysilicon layer out of the storage node. This approach provides increased storage capacitance by increasing the effective surface area of the storage node through the formation of hemispherical grains at nucleation sites along the storage node surface. There are some problems with this method. The hemispherical grain polysilicon is formed outward from the storage node and is located between the hemispherical grain polysilicon and the silicon of the storage node before it is deposited on the storage node. It is difficult to control the quality and thickness of the pure oxide layer. This difficulty may reduce the repeatability of the hemispherical grain structure. In addition, the rough hemispherical grain polysilicon layer is formed in a non-selective manner. That is, the coarse hemispherical grain polysilicon is formed on the isolation regions of the oxide between the storage nodes as well as the preformed storage nodes. Added etching is used to remove the coarse hemispherical grain polysilicon between the storage nodes to prevent shorting of two or more storage nodes. This added etching can cause damage to storage nodes, especially including complex shapes such as crowns. The extra etching step also adds time and cost to the production of this device. Another problem with this method is that the texture of the hemispherical grain polysilicon is strongly dependent on the polysilicon deposition temperature. Hemispherical grain polysilicon has a very narrow range of temperatures at which hemispherical grains are properly formed. This narrow temperature range increases the complexity of manufacturing the device and potentially limits design choices.

Selectively forming hemispherical grain polysilicon outward from the storage node provides another approach. Selective hemispherical grain polysilicon is typically formed from amorphous silicon at very low pressures on the order of 10 ^-8 torr. This is followed by a high vacuum annealing that causes the silicon of the amorphous storage node to migrate to nucleation sites on the surface. However, this method has some disadvantages. One problem with this method is that the choice of material used to form the storage node is generally limited to amorphous silicon. In addition, high vacuum annealing adds time and cost to the manufacturing process.

In accordance with the teachings of the present invention, an integrated circuit includes at least one capacitor. The capacitor includes a first capacitor contact and a capacitance increasing layer disposed outward from the first capacitor contact. The capacitance increasing layer comprises a material that lattice mismatches to silicon. The capacitor further includes a second capacitor contact disposed outwardly from the first capacitor contact and separated from the first capacitor contact by a capacitor dielectric layer.

The present invention has several technical advantages. The capacitance increasing layer is selectively deposited to prevent the formation of the capacitance increasing layer between the storage nodes. Selective deposition reduces or eliminates the need to etch the capacitive enhancement layer between the storage nodes. Due to the lattice mismatch between the capacitance increasing layer and the silicon of the storage node, the present invention does not require the use of pure oxide layers. As a result, the present invention provides a more repetitive hemispherical grain structure than the conventional method using a pure oxide layer. The capacitance increasing layer of the present invention facilitates the growth of hemispheres over a wide temperature range. In addition, the high vacuum heat treatment associated with other methods can be omitted, reducing the complexity and cost in the manufacturing process. In addition, the present invention can be used for storage nodes formed from amorphous silicon as well as polysilicon.

1 is a cross-sectional view of a capacitor made in accordance with the present invention.

2 is a chart showing the occurrence of hemisphere growth as a function of deposition temperature and alloy concentration in accordance with the present invention.

3 is a schematic diagram of an exemplary DRAM cell constructed in accordance with the present invention.

4 is a cross-sectional view of an integrated circuit including a DRAM cell constructed in accordance with the present invention.

Explanation of symbols for the main parts of the drawings

10: capacitor

12: first capacitor contact

14: first intermediate structure

16: capacitance increase layer

18: capacitor dielectric layer

20: second capacitor contact portion

100: DRAM cell

110: capacitor

112: first capacitor contact portion

116: capacitance increase layer

118: capacitor dielectric layer

120: second capacitor contact portion

130: pass-gate transistor

132 word line

134: bit line

136: substrate

138: source

140: drain

142: gate

144: sidewall spacers

146: dielectric layer

1 is a cross-sectional view of a capacitor made in accordance with the present invention. Capacitor 10 includes a first capacitor contact 12 disposed outward from first intermediate structure 14. For example, the first capacitor contact layer comprises doped polysilicon or doped amorphous silicon. The first capacitor contact can include various configurations. In this embodiment, the first capacitor contact 12 includes a plug disposed in the trench of the first intermediate structure 14. The first capacitor contact 12 may alternatively include any configuration suitable for the function, such as a plate, crown, finger, or the like. For example, the first intermediate structure 14 may be one or the like, such as oxide, nitride, oxynitride or a heterostructure comprising an alternative layer of oxide and nitride. It includes the above dielectric material.

The capacitance increasing layer 16 may be formed outward from the first capacitor contact layer 12. The capacitive enhancement layer 16 includes a material that is lattice mismatched to silicon. The capacitive enhancement layer 16 includes, for example, Si _1-x Ge _x in which the value of _x is selected to optimize the device's properties depending on the particular application. For example, the capacitance increasing layer 16 may include germane and silane, germane and disilane, germane and dichlorsilane, germane and trisilane, digerman ( chemical vapor deposition using compounds of deposition gases including, but not limited to, digermane and silane, digermane and disilane, digermane and dichlorsilane, or digermane and trisilane Can be deposited by (CVD). Materials other than Si _1-x Ge _x that are lattice mismatched to silicon can also be used without departing from the scope of the present invention. Capacitor dielectric layer 18 may be formed outward from capacitive enhancement layer 16. Capacitor dielectric layer 18 includes any dielectric material, such as an oxide, nitride, oxynitride, tantalum oxide, barium strontium titanate, or a heterostructure including an alternative layer of the dielectric. do. The second capacitor contact 20 includes, for example, doped polysilicon or doped amorphous silicon. Any material suitable for forming a capacitor contact can be used for the second capacitor contact 20 without departing from the scope of the present invention.

The first capacitor contact 12, the capacitance increasing layer 16, the capacitor dielectric layer 18, and the second capacitor contact 20 form the capacitor 10. As described above, the capacitance increasing layer 16 comprises a material that lattice mismatches to silicon. For example, germanium is about 4.2% lattice mismatch to silicon. By varying the concentration of germanium in the Si _1-x Ge _x alloy, the degree of lattice mismatch between the capacitance increasing layer 16 and the first capacitor contact 12 can be controlled. Depositing the lattice mismatched material outward from the first capacitor contact 12 causes stress between the silicon of the contact 12 and the capacitance-increasing material deposited thereon. The deposition of the capacitive enhancement layer 16 at a temperature where the mobility of the deposited material is high causes the hemispherical growth of the capacitive enhancement layer 16. This hemispheric growth relieves interstitial stress. As the hemispherical growth of the capacitance increasing layer 16 increases, the effective surface area of the capacitance increasing layer 16 increases, and the capacitance of the capacitor 10 also increases.

The capacitance increasing layer 16 may be formed by various methods. For example, a material lattice mismatched to silicon is deposited directly on the outer surface of the first capacitor contact 12. The present invention provides the advantage of facilitating the direct deposition of the capacitive enhancement layer 16 on the surface of the first capacitor contact 12 thereby eliminating the need for a native oxide layer to separate the capacitive enhancement layer from the contact. For example, this can be done by introducing a gas comprising a lattice mismatched material to the outer surface of the first capacitor contact 12. The capacitive enhancement layer 16 can be made conductive by introducing a gas containing a dopant, such as phosphine, at the same time as the in situ doping of the material that is lattice mismatched. Alternatively, the capacitive enhancement layer 16 may be subjected to a doping treatment after deposition.

2 is a chart showing the occurrence of hemispherical growth as a function of deposition temperature and alloy concentration in accordance with the present invention. See p.31, Selectively Deposited Si _1-x Ge _x Alloy Diffusion Sources for ULSI Compatible Deep Submicron p ⁺ -n and n ⁺ -p Junctions, a Ph.D. dissertation written by DT Grider in 1993. . 2 shows that the growth of the hemispheres can be controlled by the temperature and alloy concentration in the capacitance increasing layer 16. As shown in the chart, the growth of hemispheres is facilitated through a wide range of temperatures and various alloy concentrations. Preferred hemispherical grains can be formed, for example, by using germanium at a rate of about 30% at an deposition temperature of approximately 800 ° C.

Referring again to FIG. 1, proper selection of the lattice mismatched material facilitates selective deposition of the capacitive enhancement layer 16. For example, germanium reacts rapidly with oxides in the dielectric layer 14. As such, the deposition of Si _1-x Ge _x outward from the first capacitor contact 12 and dielectric layer 14 results in a capacitance-increasing layer outward from first capacitor contact 12 and not from dielectric layer 14. Allow for selective deposition of (16). This feature provides the advantage of facilitating control over the formation area of the capacitance increasing layer 16, thereby reducing or alleviating the need to etch away the capacitance increasing layer 16 from the area between the capacitors 10. Let's do it.

As the density of DRAM cells increases, the need to provide sufficient storage capacitance in the reduced area becomes more important. The invention can be used to increase the capacitance of a cell in a DRAM cell without requiring additional substrate area. 3 is a schematic diagram of an exemplary DRAM cell. The DRAM cell 100 includes a pass-gate transistor 130 coupled to a word line 132 and a bit line 134. Capacitor 110 is also coupled to pass-gate transistor 130. In operation, a row decoder (not explicitly shown) selects a particular row by increasing the voltage of the word line 132 so that all transistors of the selected row are conductive and each storage capacitor of every cell in the selected row is selected. The bit line 134 is connected. When the transistors in the selected row become conductive, each capacitor 110 is effectively connected in parallel with a bit line capacitance. At read time, the voltage across capacitor 110, which stores a logic level of 1, causes a positive increase in bit line capacitance. The change in the bit line voltage is detected and amplified by a column sense amplifier (not explicitly shown). The amplified signal is then applied to capacitor 110 to restore the signal to an appropriate level. In this way, all cells in the selected row are refreshed. At the same time, the output signal of the sense amplifier of the selected column is supplied to the data output line of the chip. The write operation proceeds similarly to the read, except that the data bits to be written are applied to the bit lines selected by the column decoder. This data bit is stored in the capacitor 110 of the selected cell. At the same time, all other cells in the selected row are refreshed.

4 is a cross-sectional view of an integrated circuit including a DRAM cell constructed in accordance with the present invention. Integrated circuit 200 includes one or more DRAM cells 100. The DRAM cell 100 includes a pass-gate transistor 130 formed on a semiconductor substrate 136. The pass-gate transistor 130 includes a source region 138 and a drain region 140 opposite the source region 138. The source region 138 and the drain region 140 may be formed in the substrate 136. Alternatively, increased source and drain regions can be implemented without departing from the scope of the present invention. The pass-gate transistor 130 further includes a gate 142 disposed between the source region 138 and the drain region 140 outward from the substrate 136. Gate 142 is separated from substrate 136 by a gate dielectric. Sidewall spacers 144 may be formed outwardly from the sidewalls of the gate 142. The dielectric layer 146 may be disposed outward from the pass-gate transistor 130. Dielectric layer 146 includes, for example, a heterostructure including oxides, nitrides, or alternative layers of oxides and nitrides. Any other structure may be used to form the pass-gate transistor without departing from the scope of the present invention.

The first capacitor contact 112 can be deposited outward from the dielectric layer 146 and is coupled to the source region 138 of the pass-gate transistor 130. The first capacitor contact 112 is similar in structure and function to the first capacitor contact 12 shown in FIG. 1. The first capacitor contact 112 includes, for example, doped polysilicon or doped amorphous silicon. The first capacitor contact 112 includes any form such as a plate, crown, finger, etc. suitable for the capacitor contact. Capacitive enhancement layer 116 may be deposited outward from capacitor contacts 112. The capacitance increasing layer 116 is similar in structure and function to the capacitance increasing layer 16 shown in FIG. Capacitor dielectric layer 118 may be formed outward from capacitive enhancement layer 116. Capacitor dielectric layer 118 is similar in structure and function to capacitor dielectric layer 18 shown in FIG. The second capacitor contact 120 can be formed outward from the capacitor dielectric layer 118. The second capacitor contact portion 120 is similar in structure and function to the second capacitor contact portion 20 of FIG. 1. The first capacitor contact 112, the capacitance increasing layer 116, the capacitor dielectric layer 118, and the second capacitor contact 120 may form the capacitor 110 of the integrated circuit 200.

While specific embodiments have been described with reference to specific embodiments for a complete and clear disclosure of the invention, it is to be understood that the appended claims are not limited thereto and that any person skilled in the art may practice within the scope of the basic knowledge described herein. It should be understood to include modifications and alternative embodiments.

In accordance with the present invention, the capacitance increasing layer is selectively deposited to prevent the formation of the capacitance increasing layer between the storage nodes. Selective deposition reduces or eliminates the need to etch the capacitive enhancement layer between the storage nodes. Due to the lattice mismatch between the capacitance increasing layer and the silicon of the storage node, the present invention does not require the use of pure oxide layers. As a result, the present invention provides a more repetitive hemispherical grain structure than the conventional method using a pure oxide layer. The capacitance increasing layer of the present invention facilitates the growth of hemispheres over a wide temperature range. In addition, the high vacuum heat treatment associated with other methods can be omitted, reducing the complexity and cost in the manufacturing process. In addition, the present invention can be used for storage nodes formed from amorphous silicon as well as polysilicon.

Claims (10)

An integrated circuit comprising at least one capacitor, The capacitor is A first capacitor contact; A capacitance increasing layer disposed outwardly from the first capacitor contact, the capacitance increasing layer comprising a material that is lattice mismatched to silicon; And A second capacitor contact disposed outwardly from the first capacitor contact and separated from the first capacitor contact by a capacitor dielectric layer Integrated circuit comprising The method of claim 1, Wherein said capacitance increasing layer comprises Si _1-x Ge _x . The method of claim 1, And the first capacitor contact portion comprises a material selected from the group consisting of doped polysilicon and doped amorphous silicon. The method of claim 1, And the capacitance increasing layer is in direct contact with an outer surface of the first capacitor contact. A method of forming an integrated circuit having at least one capacitor, the method comprising: Forming a first capacitor contact; Forming a capacitance increasing layer disposed outwardly from the first capacitor contact, wherein the capacitance increasing layer comprises a material that is lattice mismatched to silicon; Forming a capacitor dielectric layer disposed outwardly from the first capacitor contact; And Forming a second capacitor contact disposed outwardly from the capacitor dielectric layer How to include. The method of claim 5, Forming the capacitance increasing layer comprises forming an Si _1-x Ge _x layer disposed outwardly from the first capacitor contact. The method of claim 5, The forming of the capacitance increasing layer may include a compound of germane and silane, a compound of germane and disilane, a compound of germane and dichlorsilane, and germane and trisilane. a gas selected from the group consisting of a compound of trisilane, a compound of digermane and silane, a compound of digerman and disilane, a compound of digerman and dichlorsilane, and a compound of digerman and trisilane And depositing material outwardly from the first capacitor contact. The method of claim 5, Forming the capacitance increasing layer Introducing a gas comprising a material lattice mismatched with silicon to an outer surface of the first capacitor contact; In situ doping the capacitive enhancement layer by simultaneously introducing a gas containing a dopant with the inlet of the gas comprising a material that is lattice mismatched with silicon How to include. The method of claim 5, Si to form a _1-x Ge _x layer comprises the step of controlling the deposition temperature and Si concentration of germanium in the _1-x Ge _x to maximize the hemisphere growth of the Si _1-x Ge _x layer . The method of claim 5, Forming the capacitance increasing layer comprises depositing Si _1-x Ge _x, where x is about 0.3- at a deposition temperature of about 800 ° C. ₃ .