KR19990021993A - How to Mount a Chip Interconnect Carrier and Spring Contacts in a Semiconductor Device - Google Patents

Abstract

A plurality of free standing spring elements 512 are mounted to the surface 510a of the carrier substrate 510. The carrier substrate 510 is mounted to the surface 502a of the semiconductor device 502. The bond pad 504 of the semiconductor device is connected to the spring element 512 by a bond wire 520 extending between the bond pad 504 and the terminal 516 associated with the spring element. Alternatively, the carrier is a flip-chip soldered back to the semiconductor device. The carrier substrate 510 is suitably mounted to one or more semiconductor devices 532, 534 before the semiconductor device is unified from the semiconductor wafer on which the semiconductor device is formed. The elasticity for making a pressurized connection to the semiconductor device 502 is provided by a spring element 512 extending from the carrier substrate 510 itself. Therefore, the carrier substrate 510 maintains moderate rigidity with respect to the semiconductor device 502. Advantageously, the carrier substrate 510 is prepared in advance by mounting the spring element 512 to the carrier substrate before mounting the carrier substrate to the semiconductor device.

Description

A method of mounting a chip interconnect carrier and a spring contactor to a semiconductor device

Typically, individual semiconductor (integrated circuit) devices (dies) are produced by creating several identical devices on a semiconductor wafer using known techniques such as photolithography, deposition, and the like. In general, these processes seek to create a plurality of fully functional integrated circuit devices prior to singulating (cutting) individual die into a semiconductor wafer.

Generally, after unifying the semiconductor die (device) from the wafer, they are packaged (final assembly). Several techniques are known for attaching a semiconductor die to other elements, including (a) wire bonding, (b) tape automatic bonding (TAB), and flip-chip bonding.

It is generally desirable to be able to ascertain which of the plurality of dies on the wafer are good dies prior to the packaging of the dies, preferably before the dies are unified from the wafer. To this end, a wafer tester or probe is advantageously used to generate a plurality of separate pressurized connections for the same plurality of separate terminals (bond pads) on the die to provide a signal (including power) to the die. Can be employed. In this manner, the semiconductor die can be exercised (tested and burned-in) before the die is unified from the wafer.

Usually, interconnections between electronic components fall into two categories: relatively permanent and easily separable.

One example of a relatively permanent one is a solder joint. Once the two parts are soldered, the process of removing the solder must be used to separate these parts. Wire bonding is also an example of a relatively permanent connection.

One example of what can be easily separated is a rigid pin of another electronic component that is received by an elastic socket element of one electronic component. The socket element exerts a contact force (pressure) on the pins of sufficient magnitude to ensure a reliable electrical connection between the electronic components.

Interconnect elements in pressure contact with the terminals of the electronic element are referred to herein as springs or spring elements or spring contacts. In general, any minimum contact force is required to make reliable pressurized contact with the electronic elements (eg, terminals on the electronic element). For example, about 15 grams (including less than 2 grams per contact and greater than or equal to about 150 grams) to make a reliable electrical connection to a terminal of an electronic element that may be contaminated by a film on the surface or have corrosive or oxides on the surface. Contact (load) forces may be required. The minimum contact force required of each spring requires an increase in the yield strength of the spring material or an increase in the size of the spring element. As a general proposition, the higher the yield strength of the material, the more difficult it is to work (eg, puncture, bend, etc.). And the demand to make the springs smaller basically makes it impossible to make the cross sections of the springs larger.

Numbers, including, but not limited to, alignment, probe force, overdrive, contact force, equilibrium contact force, cleaning, contact resistance, and planarization, in order to achieve reliable pressurization to semiconductor devices, in particular to probe the device. Attention should be paid to the two parameters. A general discussion of these parameters can be found in US Pat. No. 4,837,622, which is incorporated herein by reference, which is named High Density Probe Card.

The following U.S. patents incorporated by reference herein are cited as being of general interest for connecting to electronic elements, in particular for pressurized connections. U.S. Patent No. 5,386,344 (Flex Circuit Card Elastomer Cable Connector Assemblies), 5,336,380 (Spring-Adjustable Tapered Contact Elements for Electrical Connectors and Integrated Circuit Packages), 5,317,479 (Plated Flexible Leads), 5,086,337 (connection structures of electronic components and electronic devices using the structures), 5,067,007 (semiconductor devices having leads for mounting on the surface of printed circuit boards), 4,989.069 (with conductors deviating from the support) Semiconductor packages), 4,893,172 (connection structures for electronic components and methods of manufacturing them), 4,793,814 (electrical circuit board interconnections), 4,777,564 (leadforms for use with surface-mounted elements), 4,764,848 (Surface Mount Array Strain Relief), 4,667,219 (Semiconductor Chip Interface), 4,642,889 (Flexible Interconnect and Manufacturing Method), 4,330,165 (Pressure Contact Interconnect) Connectors), 4,295,700 (interconnect connectors), 4,067,104 (methods for manufacturing flexible metal interconnect arrays for joining microelectronic elements), 3,795,037 (electric connector devices), 3,616,532 (multilayer printed circuit electrical Interconnect devices), and 3,509,270 (interconnects for printed circuits and methods of manufacturing the same).

It is advantageous to provide a semiconductor device itself having a mechanism for performing a pressurized connection. A limited number of techniques have been proposed in the prior art to provide a semiconductor chip assembly having terminals that are biased away from the surface of the semiconductor die (chip). US Pat. No. 5,414,298, which is a semiconductor chip assembly and element having a pressure contact, describes that such an assembly may be super-intensive and may only occupy an area slightly larger than the area of the chip itself.

BRIEF DESCRIPTION OF THE INVENTION (Summary)

It is an object of the present invention to provide a technique for mounting an elastic contact structure (spring contact) to a semiconductor device.

Another object of the present invention is to provide a semiconductor with the necessary elastic and / or flexible elements (ie, spring elements) staying on the semiconductor die, rather than requiring the probe card to be provided with an elastic contact structure extending from the probe card. It is a technique to probe a semiconductor die before the die is unified (separated) from the semiconductor wafer.

Another object of the present invention is to provide an improved spring contact element (elastic contact structure) which can be mounted on a plurality of semiconductor devices.

Another object of the invention is to provide interconnecting elements suitable for pressurized connection to electronic elements.

It is an object of the present invention to provide a technique for temporary and permanent connection to electronic elements such as semiconductor dies, using the same interconnect structure.

It is a further object of the present invention to provide a technique for temporarily interconnecting dies to perform burn-in and / or testing of the dies before the die is unified from the wafer or after the die is unified from the wafer.

According to the present invention, a plurality of original elastic contact structures (spring elements) are mounted on a carrier substrate, the carrier substrate is mounted on a semiconductor device, and the spring elements are connected to one of the bond pads on the semiconductor device by a bonding wire or the like. Is connected to a corresponding mating pad. The spring elements provide by themselves the required elasticity without requiring other means. The carrier substrate remains fixed with respect to the electronic component (for example, semiconductor device) on which the carrier substrate is mounted, in other words, the carrier substrate is not elastically mounted to the semiconductor device. Preferably, the carrier substrate is rigid.

In other embodiments of the invention, the spring elements are mounted to a lead of a leadframe, which serves as a spring contact carrier.

Among the advantages of providing a semiconductor device having a spring contact on a carrier substrate (including the lead of the leadframe);

(a) By fabricating and manufacturing the spring contacts on the carrier substrate rather than mounting the spring contacts directly to the semiconductor device, any problems with the manufacture and production of usable (good) spring contacts are evident before handling the semiconductor device;

(b) the spring contacts can reliably and temporarily contact the test substrate, which can be as simple and straightforward as a conventional printed circuit board;

(c) the same elastic contact structure can be reliably pressed against the circuit board when held in place by a spring clip or the like;

(d) The same elastic contact structure can be reliably and permanently connected to the circuit board by lead dams or the like.

According to one aspect of the invention, the spring contact element may serve a dual role as a temporary connection or as a permanent connection to an electronic component such as a semiconductor die.

Preferably, the spring contact element carrier is mounted to the semiconductor die before the semiconductor die is unified (separated) from the semiconductor wafer. In this way, a plurality of pressurized contacts can be made to one or more unsingulated semiconductor die (devices) using a simple test substrate to power a semiconductor device or the like. As used herein, a simple test substrate is a substrate having a plurality of terminals or electrodes as compared to a conventional probe card, which is a substrate having a plurality of probe elements extending from the surface. Simple test substrates are less expensive and can be configured more easily than conventional probe cards. Moreover, certain physical limitations inherent in conventional probe cards are not encountered when using a simple test substrate to make the required pressurized contacts with the semiconductor device assembly of the present night. In this manner, a plurality of ununited semiconductor dies can be exercised (tested and / or burned in) before the semiconductor die is unified (separated) from the wafer.

According to one aspect of the invention, the same spring contact element mounted to a semiconductor die and used to practice operating the semiconductor die may be used to make permanent or pressurized connections to the semiconductor die after the semiconductor die has been unified from the wafer. .

According to one aspect of the invention, the spring contact element is preferably formed as a composite interconnect element manufactured directly on the terminal of the carrier substrate. The composite (multilayer) interconnect element mounts a long core element, which may be a wire (wire stem) or ribbon, to a terminal of the carrier substrate, shapes the core element to have a spring shape, and the physical ( For example, it is produced by overcoating the core element to improve the spring) properties or to securely fix the resulting composite interconnect element to the carrier substrate.

The use of the term compound as disclosed herein and throughout the description is equivalent to the generic meaning of the term (eg, consisting of two or more elements), and any use of the compound word in other fields, eg, glass It is not to be confused with being applied to a material such as other fibers supported on a matrix such as carbon or resin.

As used herein, the term spring shape refers to any shape of an elongated element such that the end (tip) of the elongate element exhibits elastic (resilient) movement with respect to the force acting on this tip. It also includes elongate elements of substantially shaped shape with one or more bends.

As used herein, the terms contact areas, terminals, pads, and the like refer to any conductive area on any electronic component to which the interconnect element is mounted or in contact with.

Typically, the composite interconnect element (spring element) is shaped after the end of the core is mounted to the terminal on the carrier substrate.

In addition, the core element is formed prior to mounting on the electronic component.

In addition, the core element is mounted or part of a sacrificial substrate that is not an electronic component. The sacrificial base layer is removed after molding and before or after overcoating. According to aspects of the present invention, tips having various topography may be arranged at the contact ends of the interconnecting elements (see also FIGS. 11A-11F of the parental source).

In one embodiment of the present invention, the core is a soft material having a relatively low yield strength and overcoated with a hard material having a relatively high yield strength. For example, a soft material such as gold wire is attached to the bonding pad of the semiconductor device (by wire bonding or the like) and overcoated with hard material such as nickel and its alloy (by electrochemical plating or the like).

Core facing overcoating, single and multilayer overcoating, coarse overcoating with fine protrusions (see FIGS. 5C and 5D of the source) and overcoating over the entire length or only a portion of the core are described. In the case of overcoating the entire length or only a portion of the core, the tip of the core may be properly exposed to make a connection to the electronic component (see FIG. 5B of the application).

In general, plating herein is used as an example of several methods for overcoating core elements. Within the scope of the present invention, all known processes for precipitating materials and depositing materials from aqueous solutions, electrolytic plating, electroless plating, chemical vapor deposition (CVD), physical vapor deposition (PVD), separation of liquids, solids or gases, The core element can be overcoated by any suitable process, including the method.

Usually, in order to overcoat the core with a metal material such as nickel, an electrochemical process, in particular electrolytic plating, is preferred.

In another embodiment of the present invention, the spring element is an elongate element of rigid material, which is essentially suitable for acting as an elastic contact structure (ie without overcoating as in the case of the composite interconnect element). This monolithic spring element can be overcoated to improve the properties of the electrical contact of the spring element or to securely secure the spring element (in a similar manner to the composite interconnect element) to the terminal on which the spring element is mounted. In the case of overcoating for fixing, it is only necessary to couple the spring element to the terminal by soldering, gluing, penetrating the end of the spring element into the soft part of the terminal, and the like. It is also within the scope of the present invention that a plurality of rigid spring elements are mounted to a sacrificial substrate for subsequent delivery to electronic components.

Preferably, the core is in the form of a wire. Alternatively, the core is a flat tab (conductive metal ribbon) or long material ribbon.

Representative materials for core and overcoating will be described.

The following describes a method of implementation with a relatively soft (low yield strength) core that is generally very small in dimension (eg 3.0 mil or less). Soft materials such as gold that easily adhere to metallization of semiconductor devices have sufficient elasticity to function as springs. (These soft metal materials exhibit predominantly plastic rather than elastic deformation.) Other soft materials that are easily attached to semiconductor devices and have adequate resilience are electrically non-conductive as in the case of most elastomeric materials. In both cases, the required structural and electrical properties can be imposed on the composite interconnect element by overcoating applied over the core. Composite connection elements can be made very small while exhibiting adequate contact force. In addition, the plurality of the composite connection elements may have a fine pitch even if they have a length (eg, 100 mils) that is much larger than the distance to adjacent composite connection elements (the distance between adjacent connection elements is called a pitch). For example, 10 mils).

The composite interconnect elements of the present invention exhibit excellent electrical properties, including conductivity, solderability, and low resistance. In many cases, deformation of the interconnecting element in response to the applied force results in a wiping contact, which helps to make a reliable connection.

Another advantage of the present invention is that the connection made with the interconnect elements of the present invention can be easily separated. Soldering to make interconnects to the terminals of electronic components is optional and generally undesirable at the system level.

According to one aspect of the present invention, a method of manufacturing an interconnect element having a controlled impedance is described. These methods involve coating (eg, electrophoretic) the conductive core or the entire composite interconnection element with a dielectric material (insulating layer) and overcoating the dielectric material with an outer layer of conductive material. By grounding the outer conductive material layer, it is possible to effectively shield the interconnection element and to easily control its impedance (see FIG. 10K of the present application).

According to one aspect of the invention, the interconnecting elements can be prefabricated as individual units for subsequent attachment to the electronic component. Several methods have been described for achieving this purpose. Although not specifically described herein, it takes a relatively straight line to manufacture a machine that handles mounting of a plurality of individual interconnect elements to a substrate or suspending a plurality of individual interconnect elements to an elastomer or support substrate yarn. It is supposed to be.

It should be clearly understood that the composite interconnect elements of the present invention are very different from the interconnect elements of conventional methods that are coated to enhance the conductive properties and to improve the resistance to corrosion.

The overcoating of the present invention is particularly intended to enhance the fastening of the interconnect elements to the terminals of the electronic component and / or to impart the necessary elastic properties to the composite interconnect elements. In this way, the stress (contact force) is directed to the parts of the interconnecting element that are adapted to absorb this stress.

It should also be appreciated that the present invention provides new techniques for manufacturing spring contacts. In general, the actuated structure of such springs is a product by plating rather than bending and shaping operations. This makes it possible to use different materials to form the spring shape and to use the desired process for attaching the scaffold of the core to the electronic components. Overcoating functions as a superstructure on the scaffolding of the core, both of which are originally used in the field of civil engineering.

A distinct advantage of the present invention is that a freestanding spring contact (spring element) can be mounted on the fragile semiconductor device without requiring additional disadvantageous techniques such as soldering or brazing.

According to one aspect of the invention, any elastic contact structure can be formed as at least two composite interconnection elements.

Among the advantages of the present invention;

(a) the composite interconnect elements (spring contacts) are all made of metal, allowing burn-in to be carried out at elevated temperatures and consequently within a short time;

(b) the composite interconnection element is free standing and is not limited by the bond pad arrangement of the semiconductor device;

(c) The composite interconnect element of the present invention is configured to have a tip at a larger pitch (interval) than at the base, thereby distributing a pitch from a semiconductor pitch (eg, 10 mils) to a wiring board pitch (eg, 100 mils). The process is initiated immediately (eg at the initial level interconnect) to facilitate this.

Other objects, features and advantages of the present invention will become apparent in light of the following description.

FIELD OF THE INVENTION The present invention relates to the creation of temporary pressure connections between electronic elements, and more particularly to a technique for mounting an elastic contact structure (spring contact) to a semiconductor device.

[CROSS REFERENCE TO RELATED APPLICATION]

This patent application is part of a pending US patent application Ser. No. 08 / 452,255 filed on May 26, 1995, filed under US Patent Application No. 08 / 452,255, filed hereafter. Is a co-owned, pending US Patent Application No. 08 / 340,144 filed November 15, 1994 (state: pending application) and its PCT Patent Application No. PCT / US94 /, filed November 16, 1994 Part of a continuing application of 13373 (published May 26, 1995 as WO 95/14314), both of which are jointly owned US patent application Ser. No. 08 / 152,812, filed November 16, 1993 (1995). US Patent No. 5,476,211, filed Dec. 19, filed on December 19, 2008.

In addition, this patent application is part of a continuing, pending US patent application of a common ownership.

08 / 526,246 filed September 21, 1995 (PCT / US95 / 14843, November 13, 1995);

08 / 533,584, filed Oct. 18, 1995 (PCT / US95 / 14842, Nov. 13, 1995);

08 / 554,902, filed November 9, 1995 (PCT / US95 / 14844, Nov. 13, 1995;

08 / 558,332, filed November 15, 1995 (PCT / US95 / 14885, November 15, 1995);

08 / 573,945, filed December 18, 1995;

08 / 584,981, filed January 11, 1996;

08 / 602,179, filed February 15, 1996;

60 / 012,027, filed February 21, 1996;

60 / 012,040, filed February 22, 1996;

60 / 012,878, filed March 5, 1996;

60 / 013,247, filed March 11, 1996; And

60 / 005,189, filed May 17, 1996.

All patent applications are part of the above-described parent application, which is incorporated herein by reference.

Preferred embodiments of the present invention will be described with reference to the accompanying drawings. Although the present invention will be described in terms of preferred embodiments, the present invention is not limited to the above embodiments.

In the side view presented here the parts are often presented in cross-section for clarity of illustration. For example, in many figures the wire stem is shown completely in bold lines and the overcoat is shown in real section (often without hatching).

In the drawings presented herein, the size of certain elements is often exaggerated (unscaled in comparison to other elements in the figure) for the sake of clarity.

1A is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with one embodiment of the present invention.

1B is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with another embodiment of the present invention.

1C is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with another embodiment of the present invention.

1D is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with another embodiment of the present invention.

1E is a cross-sectional view of a longitudinal portion including one end of an interconnection element in accordance with another embodiment of the present invention.

2A is a cross-sectional view of an interconnecting element mounted to a terminal of an electronic component and having a multilayer shell in accordance with the present invention.

2B is a cross-sectional view of an interconnecting element having a multilayer shell in which the intermediate layer is of dielectric material in accordance with the present invention.

2C is a perspective view of a plurality of interconnecting elements mounted to an electronic component (probe card insert) in accordance with the present invention.

2D is a cross-sectional view illustrating an exemplary first step of a technique for manufacturing an interconnect element in accordance with the present invention.

2E is a cross-sectional view illustrating exemplary additional steps of the technique of FIG. 2D to fabricate an interconnect element in accordance with the present invention.

2F is a cross-sectional view illustrating exemplary additional steps of the technique of FIG. 2E to fabricate an interconnect element in accordance with the present invention.

2G is a cross-sectional view illustrating an exemplary plurality of individual interconnection elements manufactured according to the techniques of FIGS. 2D-2F in accordance with the present invention.

FIG. 2H is a cross-sectional view of an exemplary plurality of interconnecting elements manufactured in accordance with the techniques of FIGS. 2D-2F in accordance with the present invention and associated in a predetermined spatial relationship with one another.

2I is a cross-sectional view illustrating one alternative embodiment of interconnect element fabrication, showing one end of an element in accordance with the present invention.

3A is a side view of a wire having a free end coupled to a metal layer applied to a substrate, through an opening in a photoresist layer, in accordance with the present invention.

3B is a side view of the substrate of FIG. 3A with wire overcoated, in accordance with the present invention.

3C is a side view of the substrate of FIG. 3B with the photosensitive corrosion resistant layer removed and the metal layer partially removed in accordance with the present invention.

3D is a perspective view of a semiconductor device formed in accordance with the techniques shown in FIGS. 3A-3C, in accordance with the present invention.

4 is a perspective view of a semiconductor device of the prior art.

5 is a side view of a carrier substrate having a spring element mounted to a semiconductor die, in accordance with an embodiment of the invention.

5A is a side view of a carrier substrate having spring elements mounted to two ununited semiconductor dies, in accordance with an embodiment of the invention.

5B is a side view of a carrier substrate of the type shown in FIG. 5 in accordance with an embodiment of the present invention.

6 is a side view of another embodiment of a carrier substrate having a spring element mounted to a semiconductor die, in accordance with the present invention.

6A is a side view of the carrier semiconductor assembly of FIG. 6, in accordance with the present invention.

6B is a side view of another embodiment of the carrier assembly of FIG. 6, in accordance with the present invention.

7A-7F are side cross-sectional views of another embodiment of a carrier substrate of the present invention.

8A is a perspective view of another embodiment of a chip-scale (chip interconnect) carrier of the present invention.

8B is a side cross-sectional view of the chip-scale carrier of FIG. 8A.

9A is a partial side cross-sectional view of an embodiment of a spring carrier, in accordance with the present invention.

9B is a partial perspective view of an embodiment of a composite leadframe, in accordance with the present invention.

9C is a partial perspective view of an embodiment of a composite leadframe, in accordance with the present invention.

10 is an exploded side sectional view of another embodiment of a spring element carrier according to the present invention.

11 is a perspective view of a spring element carrier mounted to a silicon (semiconductor) wafer, in accordance with the present invention.

The present patent application is directed to testing semiconductor devices (including practice operations and performing burn-in) while semiconductor devices are on a semiconductor wafer (ie, before the semiconductor device is unified from the wafer) and / or with semiconductor devices (printed circuits). The present invention relates to a technique for providing a spring contact to an electronic component such as a semiconductor device so as to perform a pressure connection between the electronic component such as a substrate.

As will be apparent from the description below, this technique involves fabricating an elastic contact structure on a carrier substrate attached to a semiconductor device, pressurizing it against the elastic contact structure to test the semiconductor device, and the semiconductor die from the wafer. Using the same elastic contact structure to connect to the semiconductor die after being unified. Preferably, the elastic contact structure is implemented as a composite interconnect element as described in the specification of U.S. Patent Application No. 08 / 452,255, filed on May 26, 1995, incorporated herein by reference. This patent application summarizes some of the techniques described in the parent application in the discussion of FIGS. 1A-1E and 2A-2I.

The principal aspects of the preferred technology of practicing the present invention are: (1) to establish the mechanical properties of the resulting composite interconnection elements and / or (2) to interconnection elements when mounted on the terminals of the electronic component. In order to securely fasten to the terminals, a composite interconnect element can be formed by starting with a core (which can be mounted to a terminal of an electronic component) and overcoating the core with a suitable material. In this way, an elastic interconnect element (spring element) can be manufactured starting with a core of soft material that is easily molded into an elastic shape and easily attached to even the most fragile electronic components. In view of the prior art of forming a spring element from a hard material, it is not clear and almost certainly not intuitive that a soft material can form the basis of a spring element. In general, such composite interconnect elements are preferred forms of elastic contact structures for use in embodiments of the present invention.

1A, 1B, 1C and 1D show various shapes of a composite interconnect element according to the invention in a general manner.

The following mainly describes composite interconnect elements exhibiting elasticity. However, it will be appreciated that the inelastic composite interconnection element also falls within the scope of the present invention.

Also described is a composite interconnect element having a soft core overcoated by a hard (spring) material (which can be easily shaped and attached to an electronic component by a preferred process). However, within the scope of the present invention, the core can be made of a rigid material, where the overcoating mainly serves to securely secure the interconnect element to the terminal of the electronic component.

The electrical interconnect element 110 in FIG. 1A is a core 112 of soft material having a yield strength of less than 2812 kg / cm 2 (40,000 psi), and a rigid having a yield strength of greater than 5,624 kg / cm 2 (80,000 psi). A shell 114 of material. Core 112 is a long element that takes the shape (appearance) of a substantially straight cantilever beam and has a diameter of 0.00127-0.00762 cm (0.0005-0.0030 inch), (0.001 inch = 1 mil ≒ 25 micron (μm)). It may be a wire having. Shell 114 is applied over preformed core 112 by a suitable process, such as a suitable plating process (eg, electrochemical plating).

1A shows a simple example of a spring shape for an interconnecting element of the present invention, wherein the straight cantilever beam is positioned at an angle with respect to the force F applied to its tip 110b. When this force is exerted by the terminals of the electronic component where the interconnect element is in press contact, the downward deflection (as seen in the drawing) of the tip is evident in the tip (wiping movement) moving across the terminal. This wiping contact makes the connection between the interconnecting element and the contacted terminals of the electronic component reliable.

The shell 114 imparts some elasticity to the entire interconnection element 110 by controlling its hardness and its thickness (0.00025-0.00500 inch). In this manner, an elastic interconnect element between electronic components (not shown) is formed between two terminals 100a and 110b of the interconnect element 110. (In FIG. 1A, reference numeral 110a represents the end portion of the interconnect element 110, and the opposite end of the end 110b is not shown.) When connecting the terminals of the electronic component, the interconnect element 110 is indicated by an arrow. As shown by (F), a contact force (pressure) is applied.

It is generally preferred that the thickness of the overcoat (whether single layer or multilayer overcoat) is thicker than the diameter of the overcoated wire. From the fact that the total thickness of the contact structure to be made is the sum of the thickness of the core and twice the thickness of the overcoat, an overcoat having the same thickness as the core (eg 1 mil) is itself a collection of the thickness of the core. It is clear that it has two times.

The interconnect element (eg 110) is deflected in response to the applied contact force, which deflection (elasticity) is determined in part by the overall shape of the interconnect element and is excellent (with respect to the core) of the overcoating material. High) yield strength in part and partly in thickness of overcoating material.

As used herein, the term cantilever and cantilever beam are mounted (fixed) at one end with a long structure (such as, for example, overcoated core 112), and the other end is generally transversely transverse to the longitudinal axis of the long element. It is used to indicate that it is free to move in response to an acting force. The use of these terms does not imply any other specific or restrictive meaning.

The electrical interconnect element 120 in FIG. 1B includes a soft core 122 and a hard shell 124. In this embodiment, it can be seen that the core 122 takes the shape with two bends and thus takes the S shape. In this manner as in the embodiment of FIG. 1A, an elastic interconnect element between electronic components (not shown) is formed between the two ends 120a, 120b of the interconnect element 120. (In FIG. 1B, reference numeral 120a represents an end portion of the interconnect element 120, and the opposite end of the end 120b is not shown.) When connecting the terminals of the electronic component, the interconnect element 120 The contact force (pressure) is applied as shown by the arrow (F).

The electrical interconnection element 130 in FIG. 1C includes a soft core 132 and a hard shell 134. In this embodiment, it can be seen that the core 132 takes the shape with one bend and therefore takes the U shape. In this manner as in the embodiment of FIG. 1A, an elastic interconnect element between electronic components (not shown) is formed between the two ends 130a, 130b of the interconnect element 130. (In FIG. 1C, reference numeral 130a represents an end portion of the interconnect element 130, and an opposite end of the end 130b is not shown.) When connecting the terminals of the electronic component, the interconnect element 130 is indicated by an arrow. As shown by (F), a contact force (pressure) is applied. Alternatively, interconnect element 130 may be used to form a connection at a location other than its end 130b as shown by arrow F '.

1D illustrates another embodiment of an elastic interconnect element 140 having a soft core 142 and a hard shell 144. In this embodiment the interconnect element 140 necessarily comprises a simple cantilever (unlike FIG. 1A) with a curved tip 140b that receives a contact force F across its longitudinal axis.

1E illustrates another embodiment of an elastic interconnect element 150 having a soft core 152 and a hard shell 154. In this embodiment the interconnect element 150 takes a C-shape with a slightly curved tip 150b and is suitable for making a pressurized connection as shown by arrow F. FIG.

The soft core can easily be formed into any spring shape, ie the shape will form an elastically deflected interconnect element in response to a force applied to the tip. For example, the core may be formed in a coil shape. However, the coil shape is undesirable because it has a bad effect on circuits operating at high frequencies (speeds) due to the total length of the interconnect elements and their associated inductances.

At least one of the material of the shell or the multilayer shell (described later) has a significantly higher yield strength than the material of the core. Thus, the shell influences to achieve the mechanical properties (eg elasticity) of the interconnect structure. The yield strength ratio of shell to core is preferably at least 2: 1, including at least 3: 1, 5: 1, highest 10: 1. This ensures that at least the outer layer of the shell or multilayer shell is conductive, which is more pronounced when the shell covers the ends of the core. (However, in the case of the parent application, the case where the end of the core is exposed and the core must be conductive is described.)

From an academic point of view, only the spring (shape) portion of the composite interconnect element overcoated with a hard material is needed. In this respect, the two ends of the core to be overcoated are not necessary. In practice, however, it is desirable to overcoat the entire core. Particular reasons and advantages of overcoating the ends of the cores that are secured (attached) to the electronic components will be described in detail later.

Suitable materials for the cores 112, 122, 132, 142 include, but are not limited to, gold, aluminum, copper, and alloys thereof. These materials are alloys with small amounts of other metals such as beryllium, cadmium, silicon and magnesium in order to obtain the required physical properties. Moreover, silver, palladium, platinum, or its alloys, such as a metal of a platinum group, can also be used. Lead, tin, indium, bismuth, cadmium, antimony and alloys thereof may also be used to form solder.

The wire is made of any bendable material (using temperature, pressure and / or ultrasonic energy to perform the bending) for bonding by attaching the core to the terminals of the electronic component (discussed later). Suitable for It is also within the scope of the present invention to use any material in the core that is bendable, including non-metallic materials, for overcoating (eg, plating).

Suitable materials for the shells 114, 124, 134, and 144 (and materials suitable for the individual layers of the multilayer shell as described later) include nickel and its alloys, copper, cobalt, iron and its alloys, good current carrying capacity and good Gold (particularly hard gold) and silver exhibiting contact resistance properties, elements of the platinum group, rare metals, semi-rare metals and alloys thereof, in particular the platinum group includes urea and its alloys, tungsten and molybdenum, but are not limited thereto. . Tin, lead, bismuth, indium and their alloys can be used when soldering finishes are required.

The method of choice for applying the coating material on the various core materials is different in each case as described later. Electrolytic plating and electroless plating are generally good methods. However, according to one aspect of the present invention, when plating a nickel shell on a gold core (particularly, electrolytic plating), it is preferable to first apply a thin copper starting layer on the gold wire stem to facilitate the plating initiation operation.

Exemplary interconnect elements as shown in FIGS. 1A-1E have a core diameter of about 0.001 inch (0.00254 cm) and a shell thickness of 0.00254 cm (0.001 inch), thus the interconnect elements have a diameter of about 0.00762 cm (0.003 inch; Ie core diameter plus twice the shell thickness). In general, the thickness of the shell is 0.2-5.0 times the core thickness (diameter).

Some examples of parameters of a composite interconnect element are:

(a) A gold wire with a diameter of 1.5 mils takes the shape of a C-shaped curve (different from Figure 1E) with a total height of 40 mils and a radius of 9 mils, nickel plated to a thickness of 0.75 mils (full Diameter = 1.5 + 2 x 0.75 = 3 mil), optionally accepting a final overcoating of gold 50 microinches thick (to lower and enhance contact resistance). The composite interconnection element thus formed exhibits a spring constant (k) of about 3-5 grams / mil. In use, a deformation of 3-5 mils results in a contact force of 9-25 grams. This embodiment is useful in the case of spring elements for interposers.

(b) A gold wire with a diameter of 1.0 mil has a height of 35 mils in total and has a curved cantilever shape, nickel plated to a thickness of 1.2 mils (total diameter = 1.0 + 2 × 1.25 = 3.5 mils), 50 microinches Optionally accepts the final overcoat in gold in thickness. The composite interconnection element thus formed exhibits a spring constant (k) of about 3 grams / mil and is useful for probe spring elements.

(c) A gold wire with a diameter of 1.5 mils takes the shape of an S-shaped curve with a total height of 20 mils and a radius of about 5 mils and is nickel or copper plated to a thickness of 0.75 mils (total diameter = 1.5 + 2 × 0.75 = 3 mil). The composite interconnection element thus formed exhibits a spring constant (k) of about 2-3 grams / mil and is useful for spring elements for semiconductor devices.

The core need not have a round cross section, but may be a flat tab (having a rectangular cross section) extending from the sheet. As used herein, it should be understood that the term tab should not be confused with the term Tape Automated Bonding (TAB).

Multilayer shell

2A shows a specific example 200 of an interconnect element 210 mounted to an electronic component 212 having a terminal 214. In this embodiment, the soft (eg gold) wire core 216 is coupled (attached) to the terminal 214 at one end, extending from the terminal and taking a spring shape (other than the shape shown in FIG. 1B) and It is cut | disconnected to have the free end 216b. Joining, shaping, and cutting wires in this manner is accomplished by using wire bonding equipment. Coupling at the end 216b of the core covers only a relatively small portion of the exposed surface of the terminal 214.

The shell (overcoat) is disposed over the wire core 216 shown in this embodiment as having an inner layer 218 and an outer layer 220 which are multi-layered and appropriately applied by the plating process. One or more layers of the multilayer shell are formed of a hard material (eg, nickel and its alloys) to impart the required elasticity to the interconnect element 210. For example, the outer layer 220 may be a hard material, and the inner layer may be a material that acts as a buffer or a blocking layer (or an active layer or an adhesive layer) when the hard material 220 is plated on the core material 216. Alternatively, inner layer 218 may be a hard material, and outer layer 220 may be a material (eg, soft gold) that exhibits excellent electrical properties, including conductivity and solderability. If soldering or brazing connection is required, the outer layer of the interconnect element may be made of lead-tin solder or gold-tin brazing material, respectively.

Fixation to terminal

Figure 2A illustrates another key feature of the present invention in a general manner, showing that the elastic interconnect element can be securely fixed to the terminal on the electronic component. The attachment end 210a of the interconnection element is subjected to significant mechanical stress, causing a compressive force F applied to the free end 210b of the interconnection element.

As shown in FIG. 2A, the overcoats 218, 219 cover the core 216 and in the continuous (non-interruptible) manner the entire remaining exposed surface of the terminal 214 adjacent to the curl 216 (ie, the engagement portion ( 216a)). This securely and reliably secures the interconnect element 220 to the terminal, and the overcoating material contributes to securing the interconnect element to the terminal (eg, at least 50%). In general, the overcoating material is only required to cover at least a portion of the terminal adjacent the core. However, the overcoating material preferably covers the entire remaining surface of the terminal. It is preferable that each layer of a shell becomes metallic.

In general, the relatively small area where the core is to be attached (coupled) to the terminal is not suitable for receiving the stresses arising from the contact force F imposed on the interconnection element. The entire interconnect structure is firmly attached to the terminal by a shell covering the entire exposed surface of the terminal (other than a relatively small area comprising the core end 216a attachment to the terminal). The ability to respond to the adhesion strength and contact force of the overcoat is very good compared to the ability at the core end itself.

As used herein, the term electronic component (eg, 212) refers to semiconductor wafers and dies of any suitable semiconductor material, such as interconnect and interposer substrates, silicon (Si) or gallium arsenide (GaAs), and interconnects. Connection sockets, test sockets, sacrificial elements, elements and substrates as described in the parent application, semiconductor packages including ceramic and plastic packages and chip carriers, connectors, including but not limited to.

The interconnect elements of the invention are particularly suitable for the following applications.

Interconnection elements mounted directly to the silicon die without the need to have semiconductor packages;

An interconnecting element (described in detail later) extending from the substrate as a probe to test the electronic component;

Interconnection elements of the interposer (described in detail later).

The interconnect elements of the present invention are unique and have the advantage of obtaining the mechanical properties (eg high yield strength) of the hard material without being limited by the bad bonding properties typical of the hard material. As described in the parent application, this offers the possibility that a shell (overcoating) is possible as a superstructure on the falsework of the core, the two terms being mainly used in the field of civil engineering. This is very different from the prior art plated interconnect elements in which plating was used as a protective (eg, corrosion resistant) coating and could not impart certain mechanical properties to the interconnect element. It is also significantly different from nonmetallic corrosion resistant coatings such as benzotriazole (BTA) applied to electrical interconnects.

Among the several advantages of the present invention, a plurality of free upright interconnect castings are easily formed on a substrate such as a PCB having separate capacitors at different heights from the common height above the substrate such that their free ends are located in a common plane with each other. In addition, the electrical and mechanical properties (eg plasticity and elasticity) of the interconnection elements according to the invention are easily obtained in special applications. For example, in certain applications it is desirable for the interconnect elements to exhibit plastic and elastic deformation. (The plastic deformation preferably accommodates the parts interconnected by the interconnecting elements in a non-planar form as a whole.) If elastic properties are required, the interconnecting elements need to generate the minimum contact force required to make a reliable connection. There is. In addition, the tip of the interconnecting element makes a wiping contact with the terminals of the electronic component due to the occasional contamination film on the connecting surface.

As used herein, the term elastic refers to an elastic structure (interconnection element), which is mainly applied to a contact structure and exhibits elastic behavior in response to an applied load (contact force), and the term compliant refers to an applied load (contact force). ) Means a contact structure (interconnection element) that exhibits both elastic and plastic behavior. The following contact structure used here is an elastic contact structure. The composite interconnect element of the present invention is a special case which is either a follower or elastic contact structure.

The parent application has several features: a method of manufacturing an interconnect element on a sacrificial substrate, a method of transferring a plurality of interconnect elements into an electronic component singly, a method of providing a contact tip with a rough surface finish on the interconnect element, A method of using an interconnect element on an electronic part to make a temporary connection to the electronic part and then to make a permanent connection, a method of arranging the interconnect element to have a different space at one end rather than opposite ends, to manufacture an interconnect element How to manufacture and arrange spring clips in the same process steps, how to use interconnect elements to accommodate thermal expansion differences between connected parts, how to eliminate the need to separate semiconductor packages (for SIMMs), A method of selectively soldering an elastic interconnect element (elastic connection structure) is described. , It is not limited.

Controlled impedance

2B shows a composite interconnection element 220 with multiple layers. The innermost part of the interconnect element 220 (inner long conductive element 222) is an uncoated or overcoated core as described above. Tip 222b of innermost portion 222 is masked with a suitable masking material (not shown). The dielectric layer 124 is applied over the innermost portion 222 by an electroless process or the like. The outermost portion 226 of the conductive material is applied over the dielectric layer 124.

In use, electrically grounding the outer side 226 causes the interconnect element 220 to have a controlled impedance. One example of the dielectric layer 124 material is a polymeric material and is applied in any suitable method and thickness (eg, 0.1-3.0 mil).

The outer layer 226 may be multilayered. For example, if the entire interconnection element needs to be elastic when the innermost portion 222 is an uncoated core, at least one layer of the outer layer 226 is made of spring material.

Changing pitch

2C illustrates a plurality (only six) of interconnection elements 251,..., 256 mounted on the surface of an electronic component 260, such as a probe card insert (an assembly conventionally mounted to a probe card). Example 250 is shown. Terminals and conductive traces of the probe card insert are not shown in the figures for clarity. Attachment ends 251a, ..., 256a of interconnecting elements 251, ..., 256 form a first pitch (space), such as 0.127-0.254 cm (0.05-0.10 inch). Interconnect elements 251, ..., 256 take shape and orientation such that their free ends (tips) are at a second finer pitch, such as 0.0127-0.0254 cm (0.005-0.010 inch). An interconnect assembly that interconnects from one pitch to another is called a space transformer.

As shown, the tips 251b, ..., 256b of the interconnect elements are in two parallel rows to make a connection (for testing and / or burn-in) to a semiconductor device having two parallel rows of coupling pads (contacts). Are arranged. The interconnect elements are arranged to have different tip patterns to make connections to electronic components having different contact patterns as an array.

In general, although only one connection element is shown in the embodiments described herein, the present invention manufactures a plurality of interconnecting elements and spaces the plurality of interconnecting elements apart from each other such that they have a predetermined distance from each other, such as a circumferential pattern or a rectangular array pattern. The same applies to arranging.

Use of Sacrificial Bases

Mounting the interconnection element directly to the terminal of the electronic component has been described above. In general, the interconnect elements of the present invention may be fabricated or mounted on any suitable surface of any suitable substrate, including a sacrificial substrate.

Referring to Fig. 11A through Fig. 11F, a method of manufacturing a plurality of interconnect structures (e.g., elastic connection structures) as a separating and dividing structure for continuous mounting on electronic components with reference to Figs. 11A to 11F, and Figs. Referring to 12C, a method of mounting a plurality of interconnecting elements on a sacrificial substrate (carrier) and then transferring them all at once to an electronic component is described.

2D-2F illustrate a method of fabricating a plurality of interconnect elements having a preformed tip structure using a sacrificial base layer.

2D shows a first step of a method of applying a patterned layer of masking material 252 to the surface of sacrificial base layer 254. The sacrificial base 254 is, for example, thin (1-10 mil) copper or aluminum foil, and the masking material 252 is a conventional photoresist. Masking layer 252 takes a pattern to have a plurality of openings (shown in three halves) needed to fabricate interconnect elements at locations 256a, 256b, and 256c. The positions 256a, 256b and 256c are compared to the terminals of the electronic component. Positions 256a, 256b, and 256c are preferably treated at this stage to have a rough or characteristic surface texture. As shown, the method is mechanically accomplished by an embossing tool 257 that forms a recess in the foil 254 at locations 256a, 256b, 256c. Alternatively, the surface of the foil at these locations may be chemically etched to have surface texture. Any method suitable for achieving this overall purpose, for example sandblasting and pinning, is also within the scope of the present invention.

Then, a plurality (only one) of conductive tip structures 258 are formed at each position (eg, 256b) in the manner shown in FIG. 2E. This is accomplished by using any suitable method, such as electrolytic plating, and may include a tip structure having a multilayer material. For example, tip structure 258 has a thin (eg, 10-100 microinches) nickel barrier layer applied on the sacrificial base layer, a thin (10 microinches) soft gold layer, thin (20 microinches) hard It is applied with a gold layer, a relatively thick (200 microinches) nickel layer, and finally a thin (100 microinches) soft gold layer. In general, the first thin barrier layer of nickel protects subsequent gold layers that are neutralized by the material of base layer 254 (eg, aluminum, copper), and the relatively thick nickel layer gives strength to the tip structure, The most thin thin gold layer provides a surface that allows for easy bonding. The present invention is not limited to any particular way in which the tip structure that will vary with use is formed on the sacrificial base layer.

As shown in FIG. 2E, a plurality (only one) of cores 260 for interconnect elements are formed on tip structure 258 by any method or the like that couples a soft wire core to a terminal of an electronic component as described above. May be The core 260 is then overcoated with a hard material 262, preferably in the manner described above, and the masking material 252 has been removed and mounted to the surface of the sacrificial base layer as shown in FIG. 2F. Only three freestanding interconnection elements 264 are formed.

Similar to the overcoating material covering at least the adjacent region of the terminal 241 described in connection with FIG. 2A, the overcoating material 262 also firmly secures the core 260 to their respective tip structures 258 and is required. Accordingly imposes elastic properties on interconnect element 264. As described in the parent application, a plurality of interconnecting elements mounted on the sacrificial base may be transferred all at once to the terminals of the electronic component. Alternatively, it may take two widely diverged passageways.

It is to be understood that the silicon wafer can be used as a sacrificial base from which the tip structure is made, and that the tip structures so produced can be connected (eg, soldered or brazed) to an elastic contact structure already mounted on the electronic component. Is within the category of.

As shown in FIG. 2G, the sacrificial base layer 254 may be simply removed by any suitable process, such as selective chemical etching. Since most chemical etching processes are etched with one material at a much higher rate than other materials, the other material is only slightly etched in this process, which eliminates the sacrificial base layer while simultaneously removing the thin nickel barrier layer of the tip structure. Preferably used. However, if desired, the thin nickel barrier layer can be removed in each subsequent step. This allows a plurality of (only three) individual discrete monolithic interconnect elements 264 as shown by the dashed lines and then mounted (by soldering or brazing, etc.) to the terminals on the electronic component.

The overcoating material may be slightly thinner in the process of removing the sacrificial base layer and / or the thin barrier layer. However, it is preferable that this phenomenon does not occur.

In order to prevent overcoating from thinning, it is desirable to apply a thin gold layer or a layer of soft gold, for example 10 microinches, applied over hard gold of about 20 microinches, as the final layer on overcoating material 262. This gold outer layer is intended to have good conductivity, contact resistance and solderability and exhibits high impermeability to most etching solutions intended to be used to remove thin barrier and sacrificial base layers.

Alternatively, a thin plate having a plurality of (only three) interconnection elements 264 on its own upon removal of the sacrificial base 254 prior to removal of the sacrificial base 254 as shown in FIG. 2H. It is also possible to fix each other in a predetermined spaced relationship by any suitable supporting structure 266 or the like. The support structure 266 may be a dielectric material or a conductive material overcoated with the dielectric material. Subsequent processing steps (not shown) may then be performed, such as mounting the plurality of interconnect elements to an electronic component such as a silicon wafer or a printed circuit board. In addition, in some applications it is necessary to stabilize the tip of the interconnect element 264 (opposite to the tip structure) to prevent it from being removed, especially when a contact force is applied thereto. To this end, it is necessary to limit the movement of the tip of the interconnect element to a suitable sheet 268, such as a mesh having a plurality of holes formed of dielectric material.

Another advantage of the method 250 described above is that the tip structure 258 may be formed of any desired material and any desired tissue. As described above, gold is an example of a rare metal that exhibits excellent electrical properties, low contact resistance, solderability and corrosion resistance. In addition, because gold is a good material, it is well suited for the final overcoating applied on the interconnect elements described herein, in particular the elastic interconnect elements. Other rare metals likewise exhibit desirable properties. However, some materials, such as rhodium, exhibit good electrical properties but are not suitable for overcoating the entire interconnection element. For example, rhodium is brittle and difficult to perform with final overcoating on elastic interconnect elements. In this regard, the method illustrated by method 250 easily addresses this limitation. For example, the first layer of the multilayer tip structure (see 258) can be made of rhodium (rather than gold as described above) to provide excellent electrical properties for making connections to electronic components without compromising the mechanical properties of the interconnect elements. Indicates.

2I illustrates a modification embodiment 270 for manufacturing an interconnect element. In this embodiment, the masking material 272 is applied to the surface of the sacrificial base layer 274 and patterned to have a plurality of (only one shown) openings 276 in a manner similar to the method described above with respect to FIG. 2D. . The opening 276 defines the area of the interconnect element that is to be manufactured as a free upright structure. (As generally described herein, the interconnect element has one end coupled to the terminal or sacrificial base of the electronic component and the opposite end of the interconnect element becomes free standing when not coupled to the electronic component or sacrificial base.)

The area within the opening is shaped in any suitable manner to have one or more recesses as shown by a single recess 278 extending to the surface of the sacrificial base layer 274.

The core (wire stem) 280 is bonded to the surface of the sacrificial base layer in the opening 276 to take any suitable shape. In this embodiment only one end of the interconnect element is shown for clarity. The other end (not shown) may be attached to the electronic component. It can be seen that the method 270 differs from the method 250 described above that the core 280 is attached directly to the sacrificial base 274 rather than the tip structure 258. By way of example, the gold wire core 280 is easily bonded to the surface of the aluminum base layer 274 using conventional wire bonding methods.

In the next step of the method 270, a gold layer 282 is applied (by plating) on the core 280 and on the exposed area of the base layer 274 in the opening 276 included in the recess 278. Is applied. The main purpose of this layer 282 is to form a connection surface at the end of the interconnect element (after the sacrificial base layer is once removed).

Next, a layer 284 of relatively hard material of nickel or the like is applied over the layer 282. As described above, one main purpose of the layer 284 is to impart certain mechanical properties (elasticity) to the composite interconnection element. In this embodiment, another purpose of layer 284 is to enhance the durability of the connection surface fabricated at the bottom of the interconnect element. A final layer of gold (not shown) is applied to layer 284 to enhance the electrical properties of the interconnect element.

In the final step, the masking material 272 and the sacrificial base 274 are removed, thereby allowing a plurality of unified interconnect elements (different from Fig. 2G) or a plurality of interconnections spaced apart from each other in a predetermined relationship (different from Fig. 2H). Form an element.

This embodiment 270 illustrates an example of a method of manufacturing a patterned connection tip on an end of an interconnect element. In this case, an excellent example of gold over nickel has been described. However, other similar contact tips may be fabricated at the ends of the interconnect elements within the scope of the present invention in accordance with the methods described above. Another feature of this embodiment 270 is that the contact tip is made entirely on top of sacrificial base 274 rather than being manufactured within the surface of sacrificial base 254 as in previous embodiment 250.

Direct mounting of the spring interconnect element into the semiconductor device

3A, 3B, and 3C are similar to FIGS. 1C-1E of the parent application and illustrate a technique 300 for fabricating a composite interconnect directly on a semiconductor device including an ununited semiconductor device. The technique is similar to the technique disclosed in US patent application Ser. No. 08 / 558,332, which is co-pending with the co-owned present application described above.

According to conventional semiconductor processing techniques, the semiconductor device 302 has a patterned conductive layer 304. The layer 304 is typically bonded to the die as formed by the openings 306 in the insulating layer (e.g., a passivation layer) 308 (typically nitride). May be an upper metal layer. In this manner, a bond pad is formed having an area corresponding to the area of the opening 306 in the passivation layer 308. Typically (ie according to the prior art), the wire is bonded to the bond pad.

In accordance with the present invention, a blanket layer 310 of a metallic material (eg, aluminum) includes a passivation layer 308, including dipping in the opening 306 to electrically contact the layer 304. The conductive layer 310 is deposited (by sputtering or the like) on the surface in accordance with the surface shape of the layer 308. A patterned layer 312 of masking material (eg, photoresist) is applied over the openings 314 aligned over the openings 306 in the passivation layer 308. A portion of the blanket conductive layer 310 is covered by the masking material 312, and other portions of the blanket conductive layer 310 are exposed (not covered) in the opening 314 of the masking material 312 layer. The exposed portions in the opening 314 of the blanket conductive layer 310 serve as pads or terminals (compare 314) and may be plated with gold (not shown).

An important feature of the technique is that the opening 314 is larger than the opening 306. This makes the bonding area (defined by the opening 132) larger than the bonding area (defined by the opening 306) present on the semiconductor die 302, as will become apparent in the future.

Another important feature of the present technology is that the conductive layer 310 acts as a shorting layer to prevent damage to the device 302 during the electronic flame off processing of the wire stem (core) 320.

End 320a of inner core (wire stem) 320 is coupled to an upper surface (shown) of conductive layer 310 in opening 314. The core 320 is configured to extend from the semiconductor die to have a springable shape and is cut to have a tip 320b in the manner described above (eg, by electron flame off). Next, as shown in FIG. 3B, the molded wire stem 322 is overcoated with one or more layers of conductive material 310 as described above (compare FIG. 2A). In FIG. 3B, it can be seen that the overcoating material 322 also completely covers the wire stem 320 and also covers the conductive layer 310 within the area defined by the opening 314 in the photoresist 312.

Then, the photoresist 312 is removed (by chemical etching or cleaning, etc.), and the substrate is subjected to selective etching (eg, chemical etching) and covered by a material 322 that overcoats the wire stem 320. All material is removed from the conductive layer 310 except for the portion 315 (eg, pad, terminal) of the layer 310. The portions of the blanket conductive layer 310 previously covered by the masking material 312 and not overcoated with the material 322 are removed in this step, while the blanket conductive layer was not overcoated by the material 322. The remaining portions of 310 are not removed. This results in the structure shown in FIG. 3C, in which the resulting composite interconnection element 324 (eg, in the prior art) has a contact area (eg, an opening 306 in the passivation layer 308) of the bond pad. There is a significant advantage that it can be firmly fixed (by the coating material 322) to an area (which has been defined by the opening 314 in the photoresist) that can be easily larger than what is considered to be.

Another important advantage of the present technology is that a hermetically sealed (fully overcoated) connection is made between the contact structure 424 and the terminal (pad) 315 to which it is mounted.

The above-mentioned techniques generally present a novel method of making composite interconnect elements that are easily custom-made so that their physical characteristics exhibit a desired degree of elasticity.

In general, the composite interconnect elements of the present invention have a tip (e.g., 320b) of the interconnect elements (e.g., 320b) that are easily at the same plane and at which they begin (e.g., a bond pad). Are easily mounted to (or fabricated on) the substrate (partially a semiconductor die) in a manner that can be of different (eg, larger) pitch.

Openings are formed in the photoresist (eg, 314) in which the elastic contact structure is not mounted within the scope of the present invention. Rather, these openings can be advantageously employed to connect (by conventional wire bonding or the like) to another pad on the same semiconductor die or another semiconductor die. This gives the manufacturer the ability to customize the interconnect with a common arrangement of openings in the resist.

As shown in FIG. 3D, within the scope of the present invention, the masking layer 312 additionally includes semiconductors (ie, in addition to providing openings 314 on which the interconnect elements 324 are mounted and not overcoated). It can be patterned to leave additional conductive lines or regions on the face of the device 302. This is illustrated in this figure by the long openings 324a and 324b extending to the openings 314a and 314b, respectively, and the region openings selectively extending to the openings 314c (as shown). In the figure, elements 304, 308, 310 are omitted (for clarity). As discussed above, overcoating material 322 is deposited in these additional openings 324a, 324b, 324c and prevents portions of conductive layer 310 underlying the openings from being removed. In the case of such long region openings 324a, 324b, 324c extending into the contact openings 314a, 314b, 314c, the long region openings are electrically connected to the corresponding contact structures. This is useful in that it provides (routing) conductive traces between two or more (interconnect) terminals 315 directly on the face of the electronic component (eg, semiconductor device) 302. This is also useful for providing a ground and / or power plane directly above the electronic component 302. This provides a tight (eg, interleaved) long area (which becomes a line at the time of plating), such as long areas 324a, 324b that can serve as on-chip 302 capacitors. This is also useful. Additionally, providing openings in the masking layer 324 at a location other than the location of the contact structure 324 may help to homogenize deposition of subsequent overcoating material 322.

Within the scope of the present invention, the contact structure 324 is prefabricated, for example, in the manner of FIGS. 2D-2F described above, and at the terminal 315 with or without a tip 258 having a controlled surface shape. It is brazed. This involves mounting prefabricated contact structures on a one-to-one (from semiconductor wafer) ununified semiconductor die or on several semiconductor dies at a time. Additionally, the surface shape of tip structure 258 is described in US Patent Application No. 95-554, co-pending with the parent patent and co-owned application filed November 15, 1995. Z-axis conductive adhesive 868 may be controlled to be flat to create an effective press connection.

Practice operation of semiconductor devices

Known procedures among integrated circuit (chip) manufacturers are burn-in and functional testing of the chip. These techniques are typically performed after packaging the chip and are collectively referred to herein as practicing.

Today's integrated circuits typically produce several, typically identical, integrated circuit dies (typically as square or rectangular die sites) on a single (usually round) semiconductor wafer, and then the dies (chips) to each other. Manufactured by scribing and slicing a wafer for separation (unification, dicing) from the wafer. An orthogonal grating in the scribe line (cutting line) region extends between adjacent dies and sometimes includes test structures to evaluate the manufacturing process. These scribe line regions and any contained within these regions will be destroyed after the die is separated from the wafer. The separated dies are finally packaged individually, such as wire bonded connections between the bond pads on the die and the conductive traces in the package body.

Burn-in is simply a process of supplying power to a chip (die) (static burn-in), or supplying power and signaling the functionality of the chip to a significant extent (dynamic burn-in). In both cases, burn-in is typically performed by temporarily (or removably) connecting to the chip at high temperature, the purpose of which is to identify the defective chip before packaging the chip. Burn-in is typically performed one-to-one after dies are unified (diced) from the wafer, but it is also known to perform burn-in before separating dies. Typically, a temporary connection to the die is made by a test probe with a flying wire.

In addition, a functional test can be performed by temporarily connecting to the die. In some cases, each die is provided with a built-in self test (self-start, signal generation) circuit arrangement that exercises some of the functionality of the chip. In some cases, a test jig can be made for each die, with the probe pins aligned precisely with the bond pads on the particular die requiring the test. These test jigs are relatively expensive and require excessive manufacturing time.

As a general suggestion, package leads are optimized for burn-in (or not functional testing) assembly and often experience thousands of cycles (ie, typically one cycle per die to be tested). Moreover, different dies require different burn-in substrates. Burn-in boards increase the overall manufacturing cost and are expensive, which can only be depreciated for large scale operation of certain equipment.

If the die was partially tested before the die was packaged, the die is packaged so that the packaged die can be connected to external system components. As described above, packaging typically involves permanently connecting to the die by a bonding wire or the like. (Sometimes such a permanent connection may or may not be performed, but this is generally not desirable.)

As a result, the temporary connection required for burn-in and / or pre-packaging testing of the die is often different from the permanent connection required to package the die.

Mounting of spring elements on carriers mounted and connected on electronic parts

As described above (eg with reference to FIGS. 3A-3C), it is possible to mount the elastic contact structure of the present invention directly on a semiconductor die (on). This is particularly important in view of prior art wire couplings disposed in some kind of package that require external interconnect structures (eg, pins, leads, etc.).

In some cases it may not be advantageous or only possible in some cases to mount the spring contacts directly to the terminals of the semiconductor die. This requires a technique for placing spring contacts on the semiconductor die. Such techniques are disclosed herein.

4 illustrates a semiconductor device 400 including a semiconductor die 402 having a plurality of coupling pads (terminals) 404 arranged in a row along the centerline of the die 402. (In this figure and subsequent figures, the bond pads are shown in a stylized manner on top of the semiconductor die surface.) For example, there may be more than 100 such bond pads arranged at 5 mil pitch. . The semiconductor device 400 is typically a 64 megabit memory device. As is known, the connection to the device 400 is lead on chip with a plurality of leadframe fingers 412 extending across the top surface 402a of the die 4020 towards each coupling pad 404. Leadframe 410. Leadframe fingers 412 are connected to respective mating pads 404 by mating wires 414. Often, such devices 400 are otherwise not otherwise. In order to make the non-functional devices functional, there is provided a surplus opening (not shown) or window within the passivation layer (not shown) that exposes the upper metallization layer of the semiconductor device to reconfigure any connection internal to the device. do.

Mounting the contact structure on the bond pad 404 in the manner described above with respect to FIGS. 3A-3C seems seemingly plausible. However, often in such a device 400 the surplus exposing the upper metallization layer of the semiconductor device to reconfigure any connection internal to the device, in order to make the non-functional devices otherwise functional. An opening (not shown) or window is provided in the passivation layer (not shown). These excess windows (and exposed metallizations) essentially inhibit deposition (spreading) of the blanket conductive layer, and by the intermediate resist treatment (not shown) or by applying a polyamide coating (not shown) It must be protected from contact.

It is an object of the present invention to provide a technique for mounting an elastic contact structure (spring element) in a semiconductor device without requiring deposition of a blanket conductive layer on the semiconductor device.

According to the present invention, a plurality of elastic contact structures (spring elements) are mounted to the rigid carrier substrate, the carrier substrate is mounted to the semiconductor device, and the spring elements are electrically connected to corresponding mating pads on the semiconductor device.

FIG. 5 is a side view of a semiconductor device assembly 500 in accordance with the present invention, with somewhat similarity to FIGS. 16E and 16F of the parent source.

16E and 16F are side views of a technique for fabricating an elastic contact structure in a suitable manner for stacking chips (semiconductor dies) up and down according to the present invention.

16E and 16F are side views of a technique 1650 for fabricating an elastic contact structure in a manner suitable for stacking chips (semiconductor dies) up and down in accordance with the present invention. A sacrificial structure 1652 (compare 1602) is disposed on top of the first electronic component 1662 (compare 1612). A wire 1658 is coupled to the pad 1664 on the first electronic component 1662 at one end 1658a, configured to have an elastic retention shape (in a manner similar to FIG. 16A), and an intermediate portion of the wire 1658. 1658c is coupled to the sacrificial structure 1652 (not cut). As shown, the sacrificial structure 1652 is provided with a contact tip 1654 (compare 1026 in FIG. 10C) to which the middle portion of the wire is coupled. The wire is also shaped to extend from the sacrificial structure 1652 of an elastic retaining shape (eg, as compared to the S-shape of FIG. 2E) and cut to have a free end 1658b. The molded wire stem may be plated before (as compared to FIG. 16B) or after (as compared to FIG. 16D) removing the sacrificial element 1652 to be an elastic contact structure, at its free end 1658b a surface-shaped contact. (Compare with reference numeral 1026) may be applied.

After the sacrificial structure 1652 is removed, a second electronic component 1672 is disposed between the first electronic component 1662 and the intermediate portion 1658c of the elastic contact structure (overcoated with a wire stem) to form a second electron. Interconnect between the terminal 1674 of the component 1672 and the first electronic component 1662. The technique also has the advantage that the interconnect (overcoated wire stem portion between 1658c and 1658b) extends from the second electronic component 1672 to connect to an external system (other electronic component). As an example the first electronic component 1662 is a microprocessor and the second electronic component 1672 is a memory device.

The semiconductor device 500 includes a semiconductor die 502 (compare 402) with a plurality of bonding pads 504 (compare 404) on its top surface 502a (compare 402a). It is similar to the semiconductor device 400 in that it is. The bond pads 504 may be arranged in a row below the centerline of the semiconductor die 502.

Rigid carrier substrate 510 is mounted to face 502a of die 502 on a die region that is not occupied by bond pad 504 using any suitable adhesive.

The carrier substrate 510 is formed of any suitable rigid material, such as ceramic, silicon, PCB material (such as Kevlar), or metal with an insulating coating. The carrier substrate may also be formed of a copolymer.

The adhesive can be any suitable adhesive such as thermoplastic or cyanide esters. The adhesive does not need to be elastic or allow the carrier substrate 510 to be pressed towards the semiconductor die 502. However, in the case of a carrier substrate having a coefficient of thermal expansion substantially different from that of the semiconductor die, it is advantageous to select an adhesive that accommodates such a difference in coefficient of thermal expansion (by low shear strength or the like). The adhesive to be used to attach the carrier (eg, 510) to the substrate (eg, 502) is preferably thermoplastic, cyanide ester, epoxy, silicone, or flexible epoxy.

It should be understood that the term stiffness applied to a carrier (eg, 510) does not need to be elastic and is inherently rigid. However, the term rigid carrier also applies to flexible carriers that are attached to rigid substrates (eg, 502) without intervening means to allow / encourage bending of the carriers.

Prior to mounting the carrier substrate 510 to the semiconductor die 502, a plurality of elastic contact structures (spring elements) 512 are provided with a plurality of first terminals on the top surface 510a (shown) of the carrier substrate 510. A corresponding terminal of 516; A plurality of second terminals 516 are also provided on the top surface 510a of the carrier substrate 510 and connected to corresponding terminals of the plurality of first terminals 512 of the conductive line 518. Thus, the carrier substrate 510 is recognizable as one type of wiring substrate, where terminal 514, terminal 516 and line 518 may all be patterned from a single conductive layer. Elastic contact structure (spring element) 512 is mounted to terminal 514 in any suitable manner to have any desired elasticity / compliance properties as described above (eg, as compared to FIG. 2A).

After mounting the rigid carrier substrate 510 to the surface 502a of the semiconductor die 510, the elastic contact structure (spring element) 512 is coupled to a bond wire extending between the bond pad 504 and the terminal 516. 520 is connected to the corresponding pad of the bond pad 504. In this manner, a technique is provided for mounting an elastic contact structure (spring element) on a semiconductor device without requiring deposition of a blanket conductive layer on the semiconductor device. Moreover, a carrier substrate having spring contacts made thereon can be prefabricated for later mounting into a semiconductor die. In addition, engineering changes in the placement and interconnection of terminals on the carrier substrate are readily performed prior to mounting the carrier substrate to the semiconductor die.

As noted above, the rigid carrier substrate may be located anywhere on the die and not on top of the bond pads. If there is a surplus opening (window) in the passivation layer of the die, the rigid carrier substrate can be designed and arranged so as not to overlap the surplus window, and can be easily manufactured to avoid such collisions, but this is absolutely It is not essential. For example, if the die has already been probed (tested) and the necessary modifications to it have been made (eg, by fusion of the wiring layer of the die to reset the signal path), then the carrier has already been used. Overlapping on redundant windows can be tolerated. In general, carriers may be superimposed on the redundant window when they are no longer needed.

Generally, in the embodiment of FIG. 5 and the following embodiments, a carrier substrate (eg, reference numeral 510) is disposed between the spring element 512 and the semiconductor die (eg, 502), the spring element of the semiconductor die. Extend away from the front face (eg, 502a). This forms what can be called a semiconductor assembly.

The technique of FIG. 5 can easily be extended to the wafer level. 5A shows two adjacent plurality of semiconductor dies 532, 534 that have not been unified (separated) from the semiconductor wafer. Each die 532, 534 (compared to 504) is provided with a plurality of engagement pads 536, 538, respectively. A single rigid carrier substrate 540 (compare 510) is disposed on both tops of adjacent semiconductor dies 532, 534 to bridge (cross) at least two ununified semiconductor dies. In other words, the rigid carrier substrate 540 is suspended for either edge of the two dies.

In a manner similar to that described above with respect to FIG. 5, prior to mounting the rigid contact structure 540 to the faces of the dies 532, 534, the elastic contact structures (spring elements) 542, 555 (compare with 512). ) Is mounted to the first plurality of terminals 546, 548 (compare 514), and the terminals 546, 548 are connected to the plurality of conductive lines 550, 552 (compare 518). Two terminals 554 and 556 (compare 516), respectively, and the plurality of second terminals are connected to the mating pads 536 and 638 by a coupling wire 558 and 520 (compare 520). Each is connected.

In this manner, each semiconductor die is provided with a plurality of spring elements 642, 546 connected to its coupling pads 536, 538, which spring elements extend upwards (shown) from the surface of the die. This can be done on every die on the wafer or on selected portions of the die on the wafer. In general, where an ununited die has a central row of bond pads, only one carrier substrate is required for every two ununited dies on the wafer. However, within the scope of the present invention, a single rigid substrate may span any number of ununited dies on a wafer (eg, by being placed at the intersection of four ununited dies). In general, it is desirable to select and place one carrier per die (on a wafer) or to mount a single, very large carrier to the entire wafer of undieed die. This generally applies to all carrier elements disclosed herein.

As a result, when attempting to unify dies 532 and 536 (such as for final assembly or packaging thereof), a suitable mechanism (eg, wafer saw, laser, etc.) to slice along line 570 between adjacent ununified dies. ) Can be used.

As disclosed in US Patent Application No. 08 / 558,332, co-owned and pending with this application;

Mounting the elastic contact structure on an ununited die allows the arrangement or die of the die, with the necessary elasticity and / or followability inherent on the semiconductor die, rather than requiring a probe card with an elastic contact structure extending from the probe card. A technique is provided for testing (practice operation and / or burn-in) a semiconductor die before being unbound (separated) from the semiconductor wafer without being constrained by the placement of the bond pads on the substrate, the same elastic contact as for finally packaging the semiconductor device Use of the structure is permitted. Furthermore, by mounting an elastic contact structure (spring element) to the die, preferably prior to unifying (separating) the semiconductor die from the semiconductor wafer, one or more ununified semiconductor die ( A plurality of pressure contacts can be made to the device). (A simple test substrate is a substrate having a plurality of terminals or electrodes as opposed to a conventional probe card 'in which a plurality of probe elements extend from its surface.) A simple test card is cheaper and more expensive than a conventional probe card. It is easily configured. Moreover, certain physical corners inherent in conventional test cards do not appear when using simple test substrates with desired pressure contact with the semiconductor die. In this manner, a plurality of ununited semiconductor dies can be exercised (tested and / or burned in) prior to unifying (separating) the semiconductor die from the wafer. It is a great advantage that the same spring contact elements mounted to the semiconductor die and used to practice the operation of the semiconductor die can be used to permanently connect them to the semiconductor die after unifying them from the wafer.

The technique presented in FIG. 5A can be performed by selection and placement equipment that mounts the die to the carrier, or vice versa, and is best suited for semiconductor die with a central row of bond pads.

5B illustrates features 580 of the present invention, wherein the carrier of FIG. 5 is mounted to an electronic component 502 (eg, a semiconductor die) in the manner described above, and extends from the surface of the electronic component in a final step. A composite interconnect (spring) covering the surface of the semiconductor die 502, covering the carrier substrate 510, covering the interconnect 520 between the semiconductor device 502 and the carrier substrate 510. Encapsulant 582 encapsulates the base of element 512. A sufficient amount of encapsulant is required to achieve this desired purpose, but the application of encapsulant 582 need not be carefully controlled. This technique 580 may be performed before unifying the semiconductor die from the semiconductor die or after unifying them.

6 illustrates an alternative technique 600 that can provide a spring element to a semiconductor die and apply to an ununited die or a unified die. As shown in this figure, a rigid carrier substrate 610 (compare 510 or 540) is mounted to the surface 602a of the semiconductor die 602 (by a suitable adhesive as described above). The semiconductor die 602 has a plurality of bonding pads 604 disposed on its surface 602a, and the rigid carrier substrate 610 has a plurality of corresponding terminals 612 disposed on its upper surface (shown). do. For each bond pad 604, a bond wire 618 is joined to the bond pad without extending the bond wire 618, extending and mating to the corresponding terminal 612. This forms a connection between the bond pad 604 and the corresponding terminal 612. For each terminal 612 the bond wire 618 is further extended (as part 620 of the bond wire) to extend from the surface of the carrier substrate 610, forming and cutting in the manner described above (compare FIG. 2A). do. Wire stem 620 abuts coupling wire 618 (ie, the wire stem is one continuous wire coupled to terminal 612 at its middle).

As described above in connection with providing a blanket conductive layer 310 to the semiconductor die, plating (overcoating) the entire assembly (eg, due to the presence of excess windows on the die) may likewise not be suitable (or desirable). Can be. Thus, to perform such plating (the steps necessary to transform the free standing wire stem 620 into a composite interconnect element), it is important to mask the surface of the die before plating. This is illustrated in FIG. 6A with a masking material 630 (such as a photoresist) that is selectively applied on the face of the die 602 so as not to cover the face of the carrier substrate 610. Once masked in this manner, it can be easily overcoated with an assembly (ie, an assembly of die 602, carrier substrate 610, and bonding wires 618) material 622. This masking material 630 may be left in place or removed after overcoating.

FIG. 6B illustrates another embodiment 650 of the carrier assembly of FIG. 6. In this embodiment;

(a) Masking material 680 (compare 630) overcoats bond wire (compare 618) and wire stem 670 (compare 620) with 672 (compare 622). Is applied before.

(b) a layer of encapsulant 682 is applied over the masking material 680 to stabilize the derived composite interconnection elements 670/672 (compare 620/622), ie wire stem and carrier 660 ( The joints between the reference numeral 610). Appropriate amounts of encapsulant 682 are applied to cover the composite interconnect (spring) element, leaving a significant portion (including the tip) of the derived composite interconnect (spring) element exposed (FIG. 5B and FIG. Compared to the related technology).

Within the scope of the present invention, one or both of the features (a) and (b) may be adopted.

7A-7F illustrate an alternative technique 700 fabricated employing the spring element carrier of the present invention.

7A shows a leadframe with a plurality of leadframe fingers 702 (only one shown). Each finger 702 has an inner end 702a. Masking material 704, such as photoresist 704, is applied to the outer portions of both sides (top and bottom), leaving the inner portion of leadframe finger 702.

FIG. 7B illustrates the above described core element (wire stem) 706 coupled to the exposed inner portion of leadframe finger 702 and mounting the wire stem to the terminal of the electronic component (compare core 216 of FIG. 2A). It shows taking the spring shape in a manner similar to the technique. Next, the leadframe taking the shape with the core element mounted as shown in FIG. 7C is overcoated with a suitable conductive metal material 708, such as nickel, as described above. In this way, the composite interconnection elements with the desired resistance are formed as free upright spring elements fixed to the inner ends of the leadframe.

Next, as shown in FIG. 7D, the masking material 704 is removed, and a film 712 made of an adhesive material such as a double-sided polyimide coated with an adhesive tape or an adhesive is applied to the lower side of the lead frame 702 (shown in FIG. 7D). Direction). The entire structure may be encapsulated with epoxy or the like and extends upwardly (as shown) towards the base of the spring.

FIG. 7E shows a fully shaped leadframe with two sets of leadframe fingers 700, 700a facing inward to each other with a central opening 720 therebetween.

Within the scope of the present invention, the spring element need not be a composite interconnect element (overcoating core), which is merely illustrative, and instead is essentially a monolithic interconnect element (eg, a single Material having high yield strength).

As shown in FIG. 7E, the carrier is suitably mounted on the front face of the electronic component 730 having a plurality of terminals 732 by an adhesive film 712, each terminal being connected to a leadframe finger by a bonding wire 734. 702 is wire coupled.

Within the scope of the present invention, the outer portion of leadframe finger 702, ie the portion that is masked portion 704 but will not be overcoated, is etched or removed in any suitable manner. However, the adhesive layer 712 preferably covers the entire front face (top in FIG. 7E) of the electronic component onto which the chip scale (chip interconnect) carrier is to be mounted to protect the front face of the electronic component.

Within the scope of the present invention, the chip scale carrier may be mounted to a non-single semiconductor die on a semiconductor wafer before and after the semiconductor die is tested and burned in.

Within the scope of the present invention, the leadframes 702 are initially bound to each other by frames, similar to conventional leadframes, which are removed (eg by stamping removal) after the chip scale carrier is mounted to the semiconductor die. . This provides the advantage that a standard leadframe processing apparatus can be used to handle the chip scale carriers of the present invention. In addition, the component (eg, 730) is taken out, placed on the leadframe, coupled to (734), and encapsulated prior to removal of the leadframe (if present).

Chip scale carrier

8A illustrates one embodiment of a chip scale carrier 800 in accordance with the present invention. Electronic components 802, such as semiconductor devices, have a plurality of terminals 804, 805 (only two shown) in openings 806, 807 of insulating layer 808 on the front side (top in the figure) of component 802. Have

In a manner similar to the spring element carriers of FIGS. 5 and 5A, a carrier substrate 810 is provided, on which a spring element (composite interconnect element, elastic contact structure) is manufactured and from which the electronic component is coupled to the terminal. Wire connection is made. In this embodiment, the substrate 810 has an insulating layer 812, a patterned conductive layer 814 disposed over the insulating layer 812, and another patterned conductive layer 818 disposed over the conductive layer 814. ) Is a multilayer substrate. The insulating layer 816 is generally centrally disposed on the first conductive layer and is sized to expose two end portions of the individual conductive lines of the first conductive layer.

Within the scope of the present invention, alternately continuous insulating and conductive layers may be repeated to form a multilayer substrate having three or more layers.

The conductive layer 814 is formed with a plurality of conductive lines (only one shown in the figure) extending from one side edge of the insulating layer 812 (left in the drawing) to the opposite side of the side edge of the insulating layer 814 (right in the drawing). Take the shape to have. Similarly, conductive layer 818 may include a plurality of conductive lines (only one shown in the drawing) extending from one side edge of insulating layer 816 (left side in the drawing) to the opposite side of side edge of insulating layer 816 (right side in drawing). Take the shape with). As shown, the insulating layer 812 is larger than the insulating layer 816, and the insulating layer 816 is disposed over an intermediate point of the conductive layer 814 so that the ends of the conductive line 814 are exposed.

The core element (wire stem) 820 is coupled to one exposed end (part) of the conductive line 814 in the manner described above to produce a free upright contact structure extending from the conductive line of the substrate, and the core element (wire stem) 822 is coupled to one exposed end (part) of the conductive line 818.

The substrate 810 is disposed over the insulating layer 808 (ie, the surface of the electronic component) of the electronic component. The inner ends (opposite end portions) of the conductive lines 814, 818 are connected to the corresponding ones of the terminals 804, 805 of the electronic component 802 with coupling wires 830, 832, respectively.

As described above, the wire stems 820, 822 are overcoated to impart some elasticity to the composite interconnect element. To this end, a bonding shelf (end portions of conductive lines 814 and 818 that are wire-coupled to terminals of the electronic component) is masked with masking material 824 before mounting the spring carrier to the electronic component as shown in FIG. 8B. The masking material 824 is removed after the wire stems are overcoated (eg, plated) with one or more layers of conductive material 826.

The advantage of this embodiment 800 is that the wiring on each joining shelf directly follows the spring element (elastic contact structure) and does not need to be formed through the multilayer structure 810. This allows very high density connections to the electronic component 802 at reduced cost without the need for fine conductive lines on the substrate. In addition, the chip scale carrier of the present invention simplifies the transition from the peripheral array of terminals on the electronic component to the area array of the spring elements.

As shown in FIG. 8B, the spring element (overcoating wire stem) may occur at any height, but may terminate in the same plane (shown in dashed line in FIG. 8B). In other words, even if the spring elements arise from different heights of the chip scale carrier, they can be easily terminated at the same height above the electronic component 802.

As described above, the substrate 810 may have any number of layers. For example, one layer is used for power and the other one or more layers are used to convey signals to and from the electronic components.

The substrate 810 may be attached to the electronic component in any suitable manner, such as by bonding, and is sized to be positioned over the semiconductor device without suspending the edges of the semiconductor device.

Within the scope of the present invention, the joining shelves are located at places other than the circumferential position on their respective layers. The advantage of having multiple layers is that as long as the selected area on which the springs are mounted is accessible (unless covered by an overlapping layer of the multi-layer carrier), the wiring layer at any height may cause the spring contacts to be in contact with any selected area (i.e. the outer shelf). Smaller carriers occur when mounted in other parts and accessed for connection to terminals of electronic components (eg, semiconductor dies).

Within the scope of the present invention, all of the free ends (tips) of the spring contacts resulting from different heights (layers) of the multi-layer carrier need not be made common (terminated on the same plane). In some applications (e.g., connecting one or more components such that all terminals do not take a common plane), the spring contacts easily facilitate their tip portions to be located at any desired height (z-axis) on the carrier substrate. Are manufactured.

Composite leadframe

The spring carrier of the present invention can be manufactured using substantially conventional leadframes while taking advantage of automated equipment for mounting semiconductor dies to leadframes.

9A shows an embodiment 900 of the present invention (coupled and overcoated in the case of a composite interconnect element) with a spring element 902 mounted to an inner portion of the lid 904 of the leadframe. The outer portion 906 of the leadframe is a frame (ring) 906. The lead 904 of the leadframe extends over the semiconductor die 908 with a plurality of terminals 910 (only one shown) and is mounted thereto using a suitable adhesive 912 disposed opposite the spring element 902. . The adhesive does not need to be elastic or followable. The lead 904 is connected to the terminal 910 on the inside (left side in the drawing) of the spring element 902 by wire bonding or the like.

The lead 904 is preferably cut into the outer circumference of the semiconductor die 908 at an outer position (right in the figure) between the spring element 902 and the frame 906. This is a (goodly supported) stiffness with sufficient force to cut the leads of the leadframe in the gap between the front face (top in the figure) of the semiconductor die 908 and the back face (bottom in the drawing) of the lead 904. Properly obtained by inserting an anvil element 914. In this manner, the plurality of leads 904 may be connected to the plurality of terminals 910 on the semiconductor die 908 with the plurality of spring elements 902 extending from the leads 904. In the final step, the cut leads and the front face of the semiconductor die may be encapsulated with a suitable potting compound (eg, glow top epoxy) in a manner similar to that shown in FIG. 5B. The capsule cover covering the bottoms of the spring element 902 does not impair the function of the spring elements (ie, provide an elastic contact structure for making a pressure connection to the semiconductor die).

Within the scope of the present invention, the lead frame is sized to fit entirely within the outer periphery of the semiconductor die 908.

9B illustrates a modified embodiment 950 of the present invention. In this embodiment, the carrier comprises a plurality of conductive leads (lines) 952 (preferably sans frames) supported by an insulating layer 954 such as a Kapton (tm) film. As in the embodiment 900 described above, the spring elements 956 (compare 902) are mounted to the inner portion of each lead 952 (compare 904), and each lead 952 is of semiconductor die 960 (compare 908). And a corresponding terminal 958 (compare 910). Suitable adhesive 962 (compare 912) is used to mount the spring carrier 950 to the front face of the semiconductor die 960.

In this embodiment, the lid 952 has a patterned size so as not to extend beyond the outer periphery of the semiconductor die 960. However, the insulating film 954 may extend beyond the outer periphery of the semiconductor die 960 for ease of handling of the spring carrier 950 during assembly to the semiconductor die 960. This is generally preferred.

Spring carrier 950 and semiconductor die 960 are preferably encapsulated in a similar manner as in embodiment 900 described above (not shown). In this way, the insulating layer 954 is preferably trimmed so as not to extend over (ie, encapsulate) the capsule. Then, the excess outer portion 964 of the insulating layer 954 must be removed so that the remaining inner portion of the insulating layer 954 (ie, the portion supporting the lid 952) can be encapsulated. As shown in the figure, the dotted line 966 represents the boundary between the inner and outer portions of the insulating layer. The two portions of these insulating layers can be cut from each other in any suitable manner, including applying a hot bar to line 966 and guiding a laser beam concentrated along line 966.

9C shows the semiconductor die 972 with the inner ends of the lead 974 encapsulated, the spring element 976 extending from the leads, and the outer portion 978 of the leadframe shown in dashed lines cut as described above. Is a perspective view illustrating a spring carrier 970 mounted on the spring carrier 970.

Flip chip carrier

Various embodiments of mounting a spring element and a carrier (including leadframe) to a semiconductor die to configure a semiconductor chip assembly have been described.

10 illustrates another embodiment 1000 of a semiconductor chip assembly using solder connections in place of bonding wires to a semiconductor die (chip). In this embodiment, the spring element carrier substrate 1002 has a plurality of (only two) terminals 1004 on the top surface 1002a and a plurality of (only two) terminals 1006 on the bottom surface 1002b. Equipped) A plurality (only two) of spring elements 1008 are mounted to terminal 1004 in a manner similar to the embodiment described above. Terminals 1004 are connected to terminal 1006 through carrier substrate 1002 by a suitable method (not shown).

The semiconductor device (die, chip) has a plurality of terminals 1012 disposed on its front face (upper part of the figure). The terminals 1006 are aligned side by side with the corresponding one of the terminals 1012, and the coefficient of thermal expansion of the carrier substrate 1002 is selected to substantially match the coefficient of thermal expansion of the semiconductor die 1010.

In use, the carrier substrate 1002 is mounted to the semiconductor chip 1010 by soldering. For this purpose, a small amount of solder or solder paste 1014 is applied to at least one of the terminals 1006, 1012. This can be done by screening (eg, solder paste), by inserting a solder preform between the carrier substrate 1002 and the semiconductor die 1010, or other suitable for performing flip chip-like connections (solder bonding) between two electronic components. It can be made by a conventional method.

As the solder mass 1014 reflows, the carrier substrate 1002 tends to self-align itself with the semiconductor chip due to surface tension. Optionally, one or more large piles of solderable features 1016, 1018 may be applied to the bottom surface 1002b of the carrier substrate and the semiconductor die 1010 to increase the moment (ie, force) during the self alignment. It is provided on each front surface. An appropriate amount of solder or solder paste (not shown) is applied to at least one of the features in the manner described above with respect to the solder mass 1014. Within the scope of the present invention, the solder (or solder paste) is applied to the large features 1018 on the semiconductor die instead of applying all of the solder (or solder paste) to either of the two components 1010, 1002. And the terminal 1014 on the carrier substrate, and vice versa.

In the final step (after reflow soldering), the carrier substrate 1002 and the semiconductor die may be encapsulated (not shown) in the manner described above.

Within the scope of the present invention, any spring element, including a single spring element, may extend from the surface of the chip scale carrier (eg, 800). In other words, the present invention is not limited to using a composite spring element comprising a core and overcoating.

Within the scope of the present invention, a plurality of individual chip scale carriers may be shaped to take an arrangement for mounting upright on an electronic component (for example, a semiconductor wafer). For example, a plurality of chip scale carriers may be bound with mating wires that are overcoated to enhance their stiffness. In addition, the plurality of chip scale carriers may be physically integrated with each other in the form of a leadframe arrangement or a TAB tape carrier.

11 shows how the spring carriers 1102, compared to 1002, are mounted in a flip chip manner on a semiconductor wafer 1106. As shown here, the spring carrier 1102 takes a larger span than one die zone 1104 on the semiconductor wafer 1106. In this embodiment, the spring carrier 1102 spans six adjacent die zones 1104. While unifying (dicing) the die zones (eg, while cutting the wafer), the spring carrier 1102 can also be diced. In this embodiment, the free standing spring contacts (compare 1108) extending from the exposed surface of the spring carrier 1102 are omitted for clarity.

While the invention has been described with reference to some exemplary embodiments for purposes of illustration and description, many modifications to the embodiments are possible within the spirit and scope of the invention. Of course, those skilled in the art may also make various modifications to the subject matter described above, which also fall within the scope of the invention. Several of these modifications are described in the parent application.

For example, the technique 600 described with reference to FIGS. 6 and 6A may be applied to a carrier substrate that spans two or more ununited dies on a wafer in the manner described with respect to FIG. 5A.

For example, by mounting the spring carrier substrate of the present invention to an electronic component such as a semiconductor die and sealing the edges of the carrier substrate with an airtight material such as glass (including any gap between the carrier substrate and the face of the semiconductor die) You will get a confidential package. The carrier substrate is preferably made of an airtight material such as ceramic. If it is necessary to ensure airtightness, the capsule material may cover the edge of the carrier substrate and the surface on which the spring elements (including the bottom of the spring element) are to be mounted.

Another variation of the subject matter described above takes a relatively large carrier substrate (with corresponding plurality of spring elements) and transfers the carrier to a plurality of bonded semiconductor dies (eg, a semiconductor die or a large sized carrier substrate). There is a method of connecting (for example by reflow soldering) by forming a solder bump on the bottom surface and cutting (unifying) the semiconductor die (with spring carriers attached). The encapsulant described above can be used before or after singulating the semiconductor die.

Claims (43)

A semiconductor device assembly comprising a semiconductor die having a surface and terminals on a surface of the semiconductor die, the semiconductor device assembly comprising: A carrier substrate mounted on the surface of the semiconductor die, Free standing spring elements extending from the surface of the carrier substrate, And a connection between the spring elements and the terminals. The semiconductor device assembly of claim 1, wherein the connection portion is a bonding wire. The semiconductor device assembly of claim 1, wherein the connection portion is a solder joint. The semiconductor device assembly of claim 1, wherein the carrier substrate is a leadframe and the spring elements are mounted to the leads of the leadframe. The semiconductor device assembly of claim 1, wherein the carrier substrate comprises an insulating layer and conductive lines on the insulating layer, wherein the spring elements are mounted to the conductive lines. The semiconductor device assembly of claim 1, wherein a single carrier substrate is mounted to the surfaces of at least two semiconductor dies. 7. The semiconductor device assembly of claim 6, wherein at least two semiconductor dies are non-unified semiconductor dies on a wafer. The semiconductor device assembly of claim 1, comprising a capsule covering the surface of the semiconductor die and the carrier substrate and the contacts. The semiconductor device assembly of claim 1, wherein the carrier substrate comprises at least two conductive layers separated by at least one insulating layer. The semiconductor device assembly of claim 1, wherein the spring element is a composite interconnect element. A semiconductor die having bonding pads on the surface, A carrier substrate having terminals on a surface and mounted to a surface of the semiconductor die; Coupling wires connecting the coupling pads to the terminals; And spring elements extending from the terminals in a direction away from the surface of the semiconductor die. 12. The semiconductor assembly of claim 11, wherein the spring element is a composite interconnect element. 12. The device of claim 11, wherein a plurality of first terminals and a plurality of second terminals are provided on a surface of the carrier substrate, a spring element extends from the plurality of first terminals, and a coupling wire is connected to the plurality of second terminals, And a plurality of conductive lines located on a surface of the carrier substrate connecting the plurality of first terminals and the plurality of second terminals. 12. The semiconductor assembly of claim 11, wherein the carrier substrate spans at least two adjacent ununited semiconductor dies. The semiconductor assembly of claim 11, wherein the spring element has a core wire stem in contact with the bonding wire. A semiconductor die having bonding pads on the surface, A carrier substrate having terminals on a surface and mounted to a surface of the semiconductor die; Bond wires extending between the bond pads and the terminals and further extended to contact a free upright wire stem from the surface of the carrier substrate in a direction away from the surface of the semiconductor die; A semiconductor assembly comprising at least one layer of conductive material overcoating at least a free upright wire stem. 17. The semiconductor assembly of claim 16, further comprising a capsule disposed over the surface of the semiconductor die and extending to a portion of the overcoated wire stem adjacent the carrier substrate. 17. The semiconductor assembly of claim 16, wherein the carrier substrate spans at least two adjacent ununited semiconductor dies. A leadframe having a plurality of leadframe fingers extending over the surface of the semiconductor die with bonding pads in use; A leadframe comprising spring elements mounted to and extending from the leadframe finger in a free upright manner. 20. The leadframe of claim 19, wherein the spring element is a composite interconnect element. A multilayer substrate comprising an alternating insulating layer and at least two patterned conductive layers and having a top surface, wherein at least one of the insulating layers overlaps over a corresponding at least one conductive layer of the conductive layers; A first selected region of conductive layers having overlapping insulating layers accessible through any overlapping insulating layer or conductive layer from an upper surface, and Spring contacts having spring elements extending from patterned conductive layers over the top surface and extending from conductive layers having overlapping insulating regions extending from the first selection region of the conductive layers, And a second selection region of conductive layers having overlapping insulating layers exposed to make an interconnect to the electronic component. 22. The chip interconnect carrier of claim 21 wherein the interconnect is a bond wire. 22. The device of claim 21, wherein the electronic component is a semiconductor die and further comprises a second plurality of spring elements extending from one end of the conductive line of the first conductive layer and one end of the conductive line of the second conductive layer. Chip interconnect carrier. 22. The chip interconnect carrier of claim 21, wherein the spring contact is a composite interconnect element. A method of mounting elastic contact structures on semiconductor dies, the method comprising: Fabricating a plurality of free standing spring elements on the surface of the carrier substrate; Disposing a carrier substrate on a surface of at least one semiconductor die; Wiring the freestanding spring elements to the terminals of the at least one semiconductor die using a bonding wire. 27. The method of claim 25, wherein the spring element is a composite interconnect element. 27. The method of claim 25, wherein the carrier substrate is an insulated substrate. 26. The method of claim 25, wherein the joining wire contacts the spring element. 27. The method of claim 25, wherein the carrier substrate is a leadframe. 27. The method of claim 25, wherein the carrier substrate is a multilayer substrate. 27. The method of claim 25, wherein the carrier substrate is sized to be positioned over the semiconductor die without spanning over the edge of the semiconductor die. A substrate having a conductive portion extending from first terminals on its first surface to second terminals on a second surface, Spring elements mounted to terminals on one surface, And a semiconductor die mounted to the second surface and electrically connected to the second terminals on opposite sides. 33. The semiconductor chip assembly of claim 32, further comprising a capsule covering the semiconductor die and the carrier substrate. Substrate, A plurality of free standing spring elements extending from one surface of the substrate, And means for connecting said spring elements to an electronic component. 35. The chip interconnect carrier of claim 34, wherein the connecting means are terminals to which coupling wires can be coupled. 35. The chip interconnect carrier of claim 34, wherein the connecting means is a terminal from which solder joints can be made. 35. The chip interconnect carrier of claim 34, wherein the electronic component is at least one semiconductor die. A substrate having a conductive portion extending from first terminals on its first surface to second terminals on a second surface, A spring contact carrier comprising spring elements mounted to terminals on one surface. 39. The spring contact carrier of claim 38 wherein the spring contact is a composite interconnect element. 39. The spring contact carrier of claim 38, wherein the spring contact is a monolithic interconnect element. A method of providing free upright contacts on a surface of a semiconductor device, the method comprising: Mounting free upright contacts on one surface of at least one tile substrate, Coupling and coupling at least one tile wave to the surface of the semiconductor device. 42. The method of claim 41 wherein the semiconductor device remains on a semiconductor wafer. 42. The method of claim 41 wherein the tile is coupled to the semiconductor device by soldering.