KR19990020401A - Method for forming charge storage electrode of semiconductor device - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly to a method for forming a charge storage electrode consisting of a metastable polysilicon layer and a doped polysilicon layer.

2. The technical problem to be solved by the invention

Stabilization of the device by forming a charge storage electrode composed of an MPS layer and a doped polysilicon layer applied to a semiconductor memory device, in which the refilling oxide film is not completely removed and residues remain between grains of the MPS layer during the removal of the refilling oxide film. Problems occur.

3. Summary of the Solution of the Invention

When the refilling oxide is removed, the refilling oxide is etched only until the MPS layer is exposed, followed by etching using a carbon (C) -fluorine (F) -based gas to form a charge storage electrode.

4. Important uses of the invention

Process for forming charge storage electrode of semiconductor device.

Description

Method for forming charge storage electrode of semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a charge storage electrode of a semiconductor device, and more particularly, to a method for forming a charge storage electrode including a metastable polysilicon (MPS) layer and a doped polysilicon layer.

As semiconductor devices are highly integrated, the area occupied by capacitors is gradually decreasing. Nevertheless, minimum capacitance is required to operate the device. In order to increase the capacitance of the charge storage electrode, a method of enlarging the surface area of the charge storage electrode is used. In particular, in the case of a cylinder type charge storage electrode, there is a method of increasing the height of the cylinder to solve this problem. However, this causes a step increase between the cell of the device and the peripheral circuit, which makes it difficult to increase the height since there is difficulty in the metallization process, which is a subsequent process. In order to increase the capacitance of the charge storage electrode, in addition to the cylindrical shape, a study on a new material such as a fin shape and a capacitor material are being conducted.

Currently, charge storage electrodes applied to 256 M (mega) DRAM are formed through the process as shown in FIGS. 1 (a) to 1 (d).

As shown in FIG. 1A, after forming the interlayer insulating film 12 on the semiconductor substrate 11, a contact hole is formed to be connected to the junction 13 of the semiconductor substrate 11. The plug 14 is formed by depositing doped polysilicon in the contact hole. The doped polysilicon plug 14 is formed for the purpose of connecting the upper charge storage electrode and the lower junction 13 in a deep contact structure. An oxide film pattern 15 having a portion of the plug 14 exposed is formed on the interlayer insulating film 12, and the doped polysilicon layer 16 and the MPS layer 17 are disposed on the entire structure including the oxide film pattern 15. To form sequentially. A refilling oxide 18 is formed on the MPS layer 17 to fill the space between the oxide layer patterns 15.

FIG. 1B is a cross-sectional view of the refilled oxide layer 18 etched by dry and wet etching methods to expose the MPS layer 17 on the upper portion of the oxide layer pattern 15. After etching the refilling oxide film 18 by dry and wet etching, the refilling oxide film 18 should remain sufficiently in the space portion between the oxide film patterns 15. However, as shown in the left portion A of FIG. 1B, when the wet etching process is performed such that the refilled oxide layer 18 remains sufficiently between the oxide layer patterns 15, the MPS layer on the upper portion of the oxide layer pattern 15 is formed. The refilling oxide film 18 remains between the grains of (17), and when the exposed portions of the MPS layer 17 and the doped polysilicon layer 16 are etched back in this state, FIG. As shown in the left portion A of 1 (c), a residue 19 of the MPS layer 17 and the doped polysilicon layer 18 occurs. In particular, this phenomenon occurs more severely in the stepped area of the periphery, and this residue 19 is carried out to complete the charge storage electrode, as shown in the left part A of FIG. Although it is removed in the process of removing the refilling oxide film 18 and the oxide film pattern 15, it is highly likely to act as a particle source, causing deterioration of stability and characteristics of the device.

In order to prevent the residue 19 from occurring due to the refilling oxide film 18 remaining between the grains of the MPS layer 17 on the upper portion of the oxide film pattern 15, the right portion B of FIG. As shown, when the refilling oxide layer 18 is etched by increasing the etching target during the wet etching process, the refilling oxide layer 18 is interposed between the grains of the MPS layer 17 above the oxide layer pattern 15. Although not left, the refilling oxide film 18, which should remain sufficiently in the space between the oxide film patterns 15, is excessively etched. Accordingly, as shown in the right portion B of FIG. 1C, the refilling oxide layer (etched) is etched back in the exposed portions of the MPS layer 17 and the doped polysilicon layer 16. 18) the etch back may not function properly as a barrier (barrier), the etching loss of the MPS layer 17 and the doped polysilicon layer 16 is increased. Accordingly, as shown in the right portion B of FIG. 1D, the charge storage electrode is completed by removing the refilling oxide layer 18 and the oxide layer pattern 15. The MPS of the sidewalls and the bottom of the charge storage electrode is completed. The etch loss of the layer 17 reduces the effective surface area of the charge storage electrode so that the capacitance necessary for the operation of the device cannot be obtained.

Accordingly, the present invention effectively removes the residues remaining in the grains of the MPS layer when the refilling oxide film is removed in the process of forming the charge storage electrode of the semiconductor device including the MPS layer and the doped polysilicon layer, thereby reducing the capacity of the charge storage electrode. The purpose is to stabilize the device by solving such problems.

In the method of forming a charge storage electrode of a semiconductor device according to the present invention for achieving the above object, after depositing an interlayer insulating film on a semiconductor substrate, the contact hole is etched so as to be connected to the junction of the semiconductor substrate and dope inside the contact hole. Forming a plug by using poly polysilicon, and forming an oxide layer pattern on the interlayer insulating layer to expose the plug, and forming a doped polysilicon layer and a metastable polysilicon layer on the entire structure including the oxide layer pattern. After sequentially forming, depositing a refilling oxide film on the metastable polysilicon layer, filling the space between the oxide pattern, and etching the refilling oxide film until just before the metastable polysilicon layer is exposed. After that, the remaining portion of the upper portion of the oxide layer pattern is dried by a dry etching method using a carbon (C) -fluorine (F) -based gas. Ring oxide, metastable layer of polysilicon and doped with ring bit refill oxide film comprising the steps of: etching back the poly silicon layer at the same time, remaining between the oxide film pattern, and is characterized in that comprising the step of removing the oxide film pattern.

1 (a) to 1 (d) are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device by a conventional method.

2 (a) to 2 (d) are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.

Explanation of symbols for main parts of the drawings

11 and 21: semiconductor substrate 12 and 22: interlayer insulating film

13 and 23 junction 14 and 24 doped polysilicon plug

15 and 25: oxide film pattern 16 and 26: doped polysilicon layer

17 and 27: MPS layers 18 and 28: refilling oxide film

19: residue

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

2 (a) to 2 (d) are cross-sectional views illustrating a method of forming a charge storage electrode of a semiconductor device according to the present invention.

Referring to FIG. 2A, after the interlayer insulating layer 22 is deposited on the semiconductor substrate 21, a contact hole is formed to be connected to the junction 23 of the semiconductor substrate 21 and doped inside the contact hole. The plug 24 is formed using polysilicon. An oxide pattern 25 having a portion of the plug 24 exposed is formed on the interlayer insulating layer 22, and the doped polysilicon layer 26 and the MPS layer 27 are formed on the entire structure including the oxide layer pattern 25. Are deposited sequentially. A refilling oxide film 28 is deposited on the MPS 27 layer to fill the space portion between the oxide film patterns 25.

At this time, the oxide layer pattern 25 is formed to be as thick as the etch loss thickness to compensate for the etch loss generated during the subsequent etch back process, the doped polysilicon layer 26 is 500 kPa, and the MPS layer 27 is 615 kPa. And the refilling oxide film 28 is deposited to a thickness of 2500 kPa. The refilling oxide film 28, which acts as a barrier during the etch back of the MPS layer 27 and the doped polysilicon layer 26, fills a space portion between the oxide film patterns 25 while maintaining a void of the void. Ozone-PSG with reduced concentration of phosphorus (P) with good step coverage is used to minimize production.

The refilled oxide film 28 deposited as described above is etched by dry etching until the MPS layer 27 is exposed, as shown in FIG. 2 (b).

FIG. 2C is a cross-sectional view of the charge storage electrode separated by removing the MPS layer 27 and the doped polysilicon layer 26 on the upper portion of the oxide layer pattern 25 by an etch back process. At this time, the etch back process is performed using a carbon (C) -fluorine (F) -based gas so that the etching rates of the refilling oxide film 28, the MPS layer 27, and the doped polysilicon layer 26 are similar. In order to prevent residues due to the refilling oxide layer 28 from remaining in the stepped area in the periphery, the etchback process is subjected to overetching of about 200%, thereby compensating for the reduction in device capacity due to the decrease in height. In order to form the thickness of the oxide film pattern 25 to be as thick as the etching loss thickness.

As shown in FIG. 2 (d), the refilling oxide layer 28 and the oxide layer pattern 25 between the oxide layer patterns 25 are removed by a wet etching process using HF to form a charge storage electrode of a semiconductor device.

As described above, according to the present invention, it was solved by performing a process change so that the residue of the peripheral stepped area, which is a problem in the current memory semiconductor device, is removed together with the etch back of the MPS layer and the doped polysilicon layer.

In addition, in the conventional method, wet etching is performed again after dry etching the refilling epitaxial layer, but the wet etching process is not required in the present invention, and thus the process may be simplified.

Claims (5)

Depositing an interlayer insulating film on the semiconductor substrate, forming a contact hole to be connected to a junction of the semiconductor substrate, and forming a plug using the contact hole doped polysilicon; An oxide pattern is formed on the interlayer insulating layer to expose the plug, and a dopant polysilicon layer and a metastable polysilicon layer are sequentially formed on the entire structure including the oxide layer pattern, and then the upper part of the metastable polysilicon layer. Depositing a refilling oxide film to fill a space portion between the oxide pattern; Etching the refilling oxide layer until just before the metastable polysilicon layer is exposed, and simultaneously etching back the refilling oxide layer, the metastable polysilicon layer, and the doped polysilicon layer on the oxide pattern; And removing the refilling oxide film remaining between the oxide film pattern and the oxide film pattern. The method of claim 1, The etchback process is a method of forming a charge storage electrode of a semiconductor device, characterized in that the dry etching method using a carbon (C) -fluorine (F) -based gas. The method of claim 1, And the refilling oxide film is ozone-PSG having a reduced phosphorus (P) concentration. The method of claim 1, The etch back process is a method of forming a charge storage electrode of a semiconductor device, characterized in that to perform a 200% transient etching. The method of claim 1, The refilling oxide layer and the oxide layer pattern is removed by a wet etching process using HF.