KR19990018441A - Communication control circuits and algorithms between the PCI bus and the ISA bus - Google Patents

Abstract

The communication control circuit between the PCI bus and the ISA bus of the present invention includes a server controller, each PCI controller and each ISA controller. The server controller tests and controls the overall communication state between each PCI bus and the ISA bus according to an embedded algorithm. Each PCI controller interfaces between the server controller and each PCI bridge. Each ISA controller interfaces between a server controller and each ISA bus.

Description

Communication control circuits and algorithms between the PCI bus and the ISO bus

The present invention relates to a communication control circuit and algorithm between a PC (hereinafter referred to as PCI) bus and an CS (hereinafter referred to as ISA) bus.

In general, an information processing system includes one or more buses, and devices connected to each bus perform communication such as data transmission through the bus. For example, a typical computer system includes a local bus to which a central processing unit (CPU) is connected, which communicates with other devices connected to the local bus via the local bus. On the other hand, such a system may include one or more peripheral buses, to which peripheral devices such as input / output devices are connected.

By the way, the local bus and the peripheral bus use different protocols in performing data transmission between other devices and devices connected to the buses. Each bus is then manufactured according to this protocol. As such, a device that interfaces buses using different protocols is called a bridge. For example, a bridge that interfaces a local bus and a Peripheral Component Interconnect (PCI) bus is called a PCI bridge, and a bridge that interfaces a local bus and an ISA bus is called an ISA bridge.

The PCI protocol applied to the PCI bus is provided for efficiently connecting peripheral devices that process high-speed data to the server controller. The ISA protocol, which is applied to the ISA bus, is designed for early low speed peripherals and server controllers.

1 illustrates a communication network between a conventional PCI bus and an ISA bus. Referring to the drawings, the communication network between the conventional PCI bus and the ISA bus is composed of each of the PCI bridges 101 and 102 and the ISA bridges 111 and 112, and does not include a separate communication control circuit. Each PCI bridge 101, 102 interfaces between each PCI bus and the local bus. Each ISA bridge 111, 112 interfaces between each ISA bus and the local bus.

As described above, the communication network between the conventional PCI bus and the ISA bus is not provided with a separate communication control circuit and algorithm, so that the state of the entire communication network cannot be efficiently operated and communication errors cannot be detected quickly. Accordingly, there are limitations on the expansion and application of communication networks.

It is an object of the present invention to provide a communication control circuit and algorithm between a PCI bus and an ISA bus that can efficiently operate the state of an entire communication network and detect communication errors quickly.

1 is a block diagram showing a communication network between a conventional PCI bus and an ISA bus.

2 is a block diagram illustrating a communication control circuit between a PCI bus and an ISA bus according to an embodiment of the present invention.

3 is an internal block diagram of the n-th PCI controller of FIG. 2.

4 is an internal block diagram of the n-th ISA controller of FIG. 2.

5 is a flowchart illustrating an initialization algorithm performed by the server controller of FIG. 2.

6 is a flowchart illustrating a communication test algorithm performed by the server controller of FIG. 2.

Explanation of symbols for the main parts of the drawings

101, 102, 201, 202 ... PCI Bridge,

111, 112, 211, 212 ... ISA bridge, 2 ... communication control circuit,

221, 222 ... PCI controller, 2221 ... decoder,

2222 ... PCI subcontroller, 231, 232 ... ISA controller,

2321 ... comparator, 2322 ... ISA subcontroller,

24 ... server control.

The communication control circuit between the PCI bus and the ISA bus of the present invention for achieving the above object includes a server controller, each PCI controller and each ISA controller. The server controller tests and controls the overall communication state between each PCI bus and the ISA bus according to an embedded algorithm. Each PCI controller interfaces between the server controller and each PCI bridge. Each ISA controller interfaces between the server controller and the respective ISA bus.

Advantageously, each said PCI bridge interfaces between said each PCI bus and each ISA bridge. Each ISA bridge interfaces between each PCI bridge and each ISA bus. Each PCI bridge and the ISA bridge are connected by a local bus. Serial data communication is performed between the server controller and each PCI controller. Serial data communication is also performed between the server controller and each ISA controller.

The communication control algorithm between the PCI bus and the ISA bus of the present invention for achieving the above object is applied to the communication control circuit of the present invention. This algorithm comprises: (S1) performing an initialization routine; (S2) transmitting data through each of the PCI controller; (S3) reading the data received from each ISA controller; (S4) comparing the data transmitted in the step S2 and the data read in the step S3, and generating a communication stop signal if not equal to each other; (S5) transmitting data through each ISA controller; (S6) reading the data received from each PCI controller; And (S7) comparing the data transmitted in the step S5 and the data read in the step S6 to generate a communication stop signal if not equal to each other.

Advantageously, said step S1 comprises: (S11) storing initial data related to registers in each of said PCI bridge and ISA bridge; (S12) setting node numbers of the PCI controller and the ISA controller; (S13) enabling configuration registers in each of the PCI bridge and the ISA bridge; (S14) checking the status of diagnostic registers in each of the PCI bridge and the ISA bridge; And (S15) setting a packet size to be used for communication.

As the server controller of the present invention performs the algorithm, the state of the overall communication network can be efficiently operated, and communication errors can be detected quickly.

Hereinafter, preferred embodiments of the present invention will be described in detail.

Referring to Fig. 2, the communication control circuit 2 of the present invention includes a server controller 24, each PCI controller 221, 222 and each ISA controller 231, 232. The server controller 24 tests and controls the overall communication state between each PCI bus and the ISA bus according to an embedded algorithm. Each PCI controller 221, 222 interfaces between the server controller 24 and each PCI bridge 201, 202. Each ISA controller 231, 232 interfaces between the server controller 24 and each ISA bus.

Each PCI Bridge 201, 202 For example, a PCI9050 device interfaces between each PCI bus and each ISA bridge 211, 212. Each ISA bridge 211, 212 interfaces between each PCI bridge 201, 202 and each ISA bus. Each PCI bridge 201, 202 and the ISA bridge 211, 212 are connected by a local bus. Serial data communication is performed between the server controller 24 and each of the PCI controllers 221 and 222. Serial data communication is also performed between the server controller 24 and each of the ISA controllers 231 and 232.

Referring to FIG. 3, each of the PCI controllers 221 and 222 of FIG. 2 includes a decoder 2221 and a PCI sub controller 2222. Decoder 2221 For example, the 74F139 element decodes the chip select signal in the associated local bus and inputs it to the PCI sub controller 2222, eg, COM20020 element. Accordingly, allocated input / output (I / O) data, for example, 8-bit data communication is performed between the associated PCI bridges 201 and 202 and the PCI sub controller 2222. Serial data communication is performed between the PCI sub controller 2222 and the server controller 24.

Referring to FIG. 4, each ISA controller (231, 232 of FIG. 2) includes a comparator 2321 and an ISA sub controller 2232. The comparator 2321 inputs a chip select signal to the ISA sub-controller 2232, for example, a COM20020 element if the input / output (I / O) chip select address in the ISA bus is the same as the set address. The setting address is generated by a dip (Dual In line Package) switch. Since the I / O chip select address in the ISA bus is 16 bits, the configuration address must also be 16 bits. The 16 X 1 comparator 2321 may be replaced with two 8 X 1 comparators, for example two 74F688 elements. The sub controller 2232 generates an input / output (I / O) interrupt signal at one interrupt bit in the ISA bus under the control of the server controller 24 of FIG. 2. Accordingly, allocated input / output (I / O) data, for example, 8-bit data communication is performed between the associated ISA bus and the ISA subcontroller 2232. Serial data communication is performed between the ISA sub controller 2232 and the server controller 24.

An initialization algorithm performed by the server controller 24 of FIG. 2 is shown in FIG. 5, and a communication test algorithm is shown in FIG. 6. Referring to the drawings, the communication control algorithm of the present embodiment includes: performing an initialization routine (steps 51 to 55 of FIG. 5); Transmitting data through each PCI controller 221, 222 of FIG. 2 (steps 61 to 63 of FIG. 6); Reading the data received from the associated ISA controllers 231, 232 (step 64 of FIG. 6); Comparing the data transmitted in steps 61 to 63 and the data read in step 64 to generate a communication stop signal if not equal to each other (step 65); Transmitting data (steps 66 through 68) through each ISA controller (231, 232 of FIG. 2); Reading data received from each PCI controller 221, 222 (step 69); And comparing the data transmitted by the steps 66 to 68 and the data read by the step 69 to generate a communication stop signal if they are not equal to each other (step 70).

Hereinafter, the steps of the algorithm will be described sequentially.

First store initial data associated with registers in each PCI bridge 201, 202 and ISA bridge 211, 212 (step 51). Next, the node numbers of the PCI controllers 221 and 222 and the ISA controllers 231 and 232 are set (step 52). Next, enable configuration registers in each PCI bridge 201, 202 and ISA bridge 211, 212. Accordingly, the PCI bridges 201 and 202 and the ISA bridges 211 and 212 may perform logic control according to the information stored in the configuration registers (step 53). Next, the statuses of the diagnostic registers in the PCI bridges 201 and 202 and the ISA bridges 211 and 212 are checked (step 54). Then, a packet size to be used for transmission is set (step 55).

Next, a start address and a data range for each PCI controller (221, 222 of FIG. 2) are set (step 61). Data to be transmitted next is recorded in the random access memory (RAM) of each of the PCI controllers 221 and 222 (step 62). The data recorded in the RAM is then transferred to the associated ISA bus side. Accordingly, the data recorded in the RAM is transferred to the ISA bus side through the associated local bus and the ISA bridges 211 and 212 (step 63). The data received via the associated ISA controllers 231 and 232 is then read (step 64). Here, the transmitted data and the read data are compared to generate a communication stop signal if they are not equal to each other (step 65).

On the other hand, the start address and data range for each ISA controller (231, 232 of Fig. 2) are set (step 66). The data to be transmitted next is recorded in random access memory (RAM) of each of the ISA controllers 231 and 232 (step 67). The data written to the RAM is then transferred to the associated PCI bus side. Accordingly, the data recorded in the RAM is transferred to the PCI bus side through the associated ISA bridges 211 and 212, the local bus and the PCI bridge (201 and 202 in FIG. 2) (step 68). Next, the data received through the associated PCI controllers 221 and 222 is read (step 69). Here, the transmitted data and the read data are compared to generate a communication stop signal if they are not the same (step 70).

As this algorithm is performed in the server controller 24, the state of the overall communication network can be efficiently operated, and communication errors can be detected quickly. The present invention is not limited to the above embodiments, and modifications and improvements are possible at the level of those skilled in the art. For example, when communication is interrupted by performing step 65 or 70 of FIG. 6, the communication error signal may be transmitted to the associated PCI bus and the ISA bus.

As described above, according to the communication control circuit and algorithm between the PCI bus and the ISA bus according to the present invention, it is possible to efficiently operate the state of the entire communication network and to quickly detect communication errors, thereby contributing to the expansion and application of the communication network. Can be.

Claims (14)

A server controller for testing and controlling the overall communication state between each PCI bus and the ISA bus according to an embedded algorithm; Each PCI controller interfacing between the server controller and each PCI bridge; And And a respective ISA controller for interfacing between the server controller and the respective ISA bus. The method of claim 1, wherein each PCI bridge, And interfacing between each PCI bus and each ISA bridge. The method of claim 2, wherein each ISA bridge, Interfacing between each PCI bridge and each ISA bus. The method of claim 3, wherein between each of the PCI bridge and the ISA bridge, Communication control circuitry between the PCI bus and the ISA bus, characterized in that connected by a local bus. According to claim 1, Between the server controller and each PCI controller, Communication control circuitry between a PCI bus and an ISA bus, wherein serial data communication is performed. The method of claim 1, wherein between the server controller and each ISA controller, Communication control circuitry between a PCI bus and an ISA bus, wherein serial data communication is performed. A server controller for testing and controlling the overall communication state between each PCI bus and the ISA bus according to an embedded algorithm; Each PCI controller interfacing between the server controller and each PCI bridge; And a respective ISA controller for interfacing between the server controller and the respective ISA bus, wherein the communication control algorithm between the PCI bus and the ISA bus is applied to the communication control circuit. (S1) performing an initialization routine; (S2) transmitting data through each of the PCI controller; (S3) reading the data received from each ISA controller; (S4) comparing the data transmitted in the step S2 and the data read in the step S3, and generating a communication stop signal if not equal to each other; (S5) transmitting data through each ISA controller; (S6) reading the data received from each PCI controller; And (S7) comparing the data transmitted in the step S5 and the data read in the step S6, if not equal to each other to generate a communication stop signal; communication control algorithm between the PCI bus and the ISA bus, comprising a. The method of claim 7, wherein each PCI bridge, And a communication control algorithm between the PCI bus and the ISA bus, interfacing between each PCI bus and each ISA bridge. The method of claim 8, wherein each ISA bridge, And a communication control algorithm between the PCI bus and the ISA bus, interfacing between each PCI bridge and the respective ISA bus. The method of claim 9, wherein step S1, (S11) storing initial data related to registers in each of the PCI bridge and the ISA bridge; (S12) setting node numbers of the PCI controller and the ISA controller; (S13) enabling configuration registers in each of the PCI bridge and the ISA bridge; (S14) checking the status of diagnostic registers in each of the PCI bridge and the ISA bridge; And (S15) setting a packet size to be used for communication; communication control algorithm between the PCI bus and the ISA bus comprising a. The method of claim 7, wherein the step S2, (S21) setting a start address and a data range for each PCI controller; (S22) recording the data to be transmitted to the RAM of the PCI controller; And (S23) transmitting the data recorded in the RAM to the ISA bus side; communication control algorithm between the PCI bus and the ISA bus comprising a. The method of claim 7, wherein the step S5, (S51) setting a start address and a data range for each ISA controller; (S52) recording the data to be transmitted to the RAM of the ISA controller; And (S53) transmitting the data recorded in the RAM to the PCI bus side; communication control algorithm between the PCI bus and the ISA bus comprising a. The communication stop signal generated by performing the steps S4 and S7, A communication control algorithm between the PCI bus and the ISA bus comprising a communication error signal. The method of claim 13, wherein the communication stop signal, A communication control algorithm between the PCI bus and the ISA bus, characterized in that it is transmitted over the PCI bus and the ISA bus.