KR19990018193A - Serial Interface Unit for OTP - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface apparatus, and more particularly, to an OTP serial interface apparatus for programming a One-Time-Programmable EPROM (OTP), and is input to a clock terminal 100. The voltage level of the signal OSID input to the address / data terminal 110 is converted from the first voltage level to the second voltage level while the clock signal OSIC maintains a constant voltage level. Operation), and the program (or read operation) is terminated by converting from the second voltage level to the first voltage level. The serial interface device 10 converts serially input data in parallel during a program operation and provides the same to the OTP 20. During read operation, the serial interface device 10 receives parallel data from the OTP 20 and converts the serial data into serial data and outputs the serial data to the outside. . In this case, a predetermined integer multiple of the input clock signal OSIC is a dummy clock, and when the dummy clock is input, the address / data terminal 110 is set as an input port, and in the interval of the dummy clock. A plurality of control signals for controlling the program and the read operation are generated.

Description

Serial Interface Unit for OTP

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial interface apparatus, and more particularly to a serial interface apparatus for OTP for programming of a One-Time-Programmable EPROM (OTP).

Currently, a microcontroller may be provided with a random access memory (RAM) and a read only memory (ROM). In particular, ROM has built-in OTP. OTP can be used to store one programmable memory or microcontroller application program.

On the other hand, in the case of a microcontroller with a built-in OTP in order to program the built-in OTP was usually used a parallel port (parallel port) provided in the microcontroller. Since the conventional OTP program method requires the use of a parallel port of a microcontroller, a plurality of pins constituting the parallel port have to be used. In the case of a serial port provided in the microcontroller, an interface for the OTP program was not provided, and thus a program using the same was not possible.

Accordingly, an object of the present invention is to provide a serial interface device for OTP for programming OTP as proposed to solve the above-mentioned problems.

Another object of the present invention is to provide a microcontroller capable of programming OTP in a serial manner.

1 is a block diagram schematically showing a connection relationship between an OTP and a serial interface device of the present invention;

2 is a circuit diagram of a serial interface device according to a preferred embodiment of the present invention;

3 is a view showing a format of a data transmission protocol between a serial interface device and an OTP according to a preferred embodiment of the present invention;

4 is a waveform diagram of a main part according to a program operation of the serial interface device shown in FIG. 2;

5 is a waveform diagram of a main part according to a read operation of the serial interface device shown in FIG. 2;

Explanation of symbols for main parts of the drawings

10: serial interface device 20: OTP

100: clock terminal 110: data / address terminal

120: status signal generator 130: counter

140: control signal generator 150: address / data buffer

According to one aspect of the present invention for achieving the object of the present invention as described above, the OTP serial interface device: receives a clock signal and a address / data signal having a predetermined period of the program / read operation of the OTP A state signal generator for outputting a state signal for informing a start state and an end state; A counter unit receiving the clock signal and the state signal and outputting signals according to a counting result of the clock signal; A control signal generator which receives the status signal and the output of the counter and outputs predetermined control signals for controlling the program / read operation of the OTP; And receiving a synchronization signal and a control signal provided from the counter unit and the control signal generator, receiving the address / data signal, outputting an address signal for addressing the OTP, and performing serial-to-parallel data conversion. Address / data buffer to be executed and output.

In this embodiment, the counter unit comprises: a clock counter for counting the number of clocks of the clock signal; It receives the output of the clock counter, and includes a frame counter for distinguishing the address information and data information.

In this embodiment, the control signal generator comprises: a write / read control signal generator for outputting a control signal according to a program and a read operation of the OTP; And a mode control signal generator for outputting an OTP mode control signal.

In this embodiment, the address / data buffer receives a synchronization signal from the counter, and receives and stores address data input as the address / data signal in synchronization with the counter, and provides the same from the counter unit and the control signal generator. An address buffer which increases address data based on the control signal to be output to the OTP; In programming, the serial data inputted as the address / data signal is received from the counter in synchronization with the synchronous signal and stored therein, and the parallel data stored in the OTP based on the control signal provided from the counter unit and the control signal generator is parallel data. Converts and outputs, and receives and stores parallel data from the OTP in synchronization with a synchronous signal from the counter during a read operation, and converts the parallel data stored on the basis of control signals provided from the counter and the control signal generator. Data buffer to be output.

According to another feature of the invention, a microcontroller comprises: a programmable OTP; A clock terminal configured to receive a clock signal according to a program operation and a read operation of the OTP; An address / data terminal for receiving an address signal and a data signal according to the program operation and the read operation of the OTP; And a serial interface device for an OTP that performs the program and read operation of the OTP based on each signal input to the clock terminal, the address, and / or data terminal.

In this embodiment, the serial interface device generates a state signal for receiving a clock signal having a predetermined period and an address / data signal and outputting a state signal for notifying the start state and end state of the program / read operation of the OTP. Wealth; A counter unit receiving the clock signal and the state signal and outputting signals according to a counting result of the clock signal; A control signal generator which receives the status signal and the output of the counter and outputs predetermined control signals for controlling the program / read operation of the OTP; And receiving a synchronization signal and a control signal provided from the counter unit and the control signal generator, receiving the address / data signal, outputting an address signal for addressing the OTP, and performing serial-to-parallel data conversion. Address / data buffer to be executed and output.

In this embodiment, the counter unit comprises: a clock counter for counting the number of clocks of the clock signal; It receives the output of the clock counter, and includes a frame counter for distinguishing the address information and data information.

In this embodiment, the control signal generator comprises: a write / read control signal generator for outputting a control signal according to a program and a read operation of the OTP; And a mode control signal generator for outputting an OTP mode control signal.

In this embodiment, the address / data buffer receives a synchronization signal from the counter unit, and receives and stores address data input as the address / data signal in synchronization with the counter unit and the control signal generator. An address buffer which increases address data based on the control signal provided and outputs the address data to the OTP; During programming, serial data inputted as the address / data signal is received and stored in synchronization with the synchronization signal from the counter unit, and the serial data stored in the OTP is paralleled based on a control signal provided from the counter unit and the control signal generator. Converts and outputs the data, receives parallel data from the OTP in synchronization with the synchronization signal from the counter during read operation, and stores the parallel data stored based on the control signal provided from the counter and the control signal generator. Contains a data buffer for conversion and output.

According to still another aspect of the present invention, a programmable OTP, a clock terminal for receiving a clock signal according to a program and a read operation of the OTP, an address for receiving an address signal and a data signal according to a program and a read operation of the OTP OTP program and read control method of the microcontroller including a serial interface device for performing the OTP program and the read operation based on the / data terminal, the signal input to the clock terminal and the address / data terminal When the clock signal inputted to the clock terminal maintains a constant voltage level, when the signal inputted to the address / data terminal is converted from a first voltage level having a different voltage level to a second voltage level, the program of the OTP or Any one of the read operations is started; When the signal input to the address / data terminal is converted from the second voltage level to the first voltage level in the period in which the clock signal maintains a constant voltage level, any one of the program or read operation of the OTP is terminated; A dummy clock is defined in the clock signal, and a program or a read operation of the OTP is performed in synchronization with the dummy clock.

In this embodiment, during the read operation, the address / data terminal is set as an input port in the section where the dummy clock is input.

In this embodiment, in the program operation, a plurality of dummy data is transmitted following the last program data at the end of the program to secure the program time of the final program data.

According to the present invention as described above, the voltage level of the signal input to the address / data terminal is converted from the first voltage level to the second voltage level in a period in which the clock signal input to the clock terminal maintains a predetermined voltage level. The program (or read operation) is started, and the program (or read operation) is terminated by converting from the second voltage level to the first voltage level. The serial interface device converts the serially input data into parallel during the program operation and provides it to the OTP. During the read operation, the serial interface device receives parallel data from the OTP and converts the serial data into serial data for output. In this case, a predetermined integer multiple of the clock signal to be input is a dummy clock, the address / data terminal is set as an input port when the dummy clock is input, and a plurality of clocks for controlling a program and a read operation in the dummy clock section. Generate a control signal.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a connection relationship between an OTP and a serial interface device of the present invention, and FIG. 2 is a circuit diagram of a serial interface device according to a preferred embodiment of the present invention.

As shown in Fig. 1, the novel serial interface device 10 for OTP of the present invention is embedded in a microcontroller in which the OTP 20 is incorporated. The serial interface device 10 receives a clock signal (OSIC; OTP Serial Interface Clock) through the clock terminal 100 provided in the microcontroller, and through the address / data terminal 110, the address / data signal ( OSID; OTP Serial Interface Data) is provided. In addition, the serial interface device 10 provides a predetermined control signal and an address signal to the OTP 20 in response to each input signal, and performs a data write and read operation. .

Specifically, a predetermined program device (not shown) for programming the OTP 20 is connected to the clock terminal 100 and the address / data terminal 110. At this time, an OSIC signal and an OSID signal are provided to the serial interface device 10 through each terminal. Subsequently, the serial interface device 10 provides various control signals and address / data signals to the OTP 20 based on each input signal so that the OTP 20 is programmed. When the program is completed, the program device reads the programmed data from the OTP 20 to determine whether the OTP 20 is normally programmed. The serial interface device 10 provides the read data to the program device through the address / data terminal 110.

When performing the above operation, the serial interface device 10 converts the serial data inputted to the address / data terminal 110 into parallel data and provides the parallel data to the OTP 20, from (20). The read parallel data is converted into serial data and output to the address / data terminal 110.

More specifically, with reference to the accompanying drawings Figures 2 to 5 will be described in detail a serial interface device according to a preferred embodiment of the present invention.

As shown in FIG. 2, the serial interlacing apparatus according to the embodiment of the present invention has a large state signal generator 120, a counter 130, a control signal generator 140, and an address / data buffer ( 150).

In the serial interface device having the above configuration, the format as shown in Fig. 3 operates according to the data transmission protocol.

3 is a diagram illustrating a format of a data transmission protocol between a serial interface device and an OTP according to a preferred embodiment of the present invention.

As shown in FIG. 3, the format of the data transmission protocol between the serial interface apparatus and the OTP according to the preferred embodiment of the present invention is address information 31 and data information 35 in a frame 30 transmitted. ).

The address information 31 is composed of three bytes (A23 to A0) of Address1, Address2, and Address3. 3 bits A23 to A21 of the Address1 32 are mode setting bits. 4 bits A20 to A17 are bits for address expansion, and A16 bits are bits for setting write / read. The mode setting includes, for example, a read mode, a program mode, a dummy row read program mode, and the like. Address 2 and 3 (A15 to A8 and A7 to A0) 33 are areas for addresses.

The data information 35 includes N data (Data1 to DataN) 36 and 1 byte of dummy data 37 for terminating the program of the OTP. The dummy data 37 is set to FFh in this embodiment. The dummy data 37 is used to secure the time for the Nth data to be programmed in the OTP.

Operation of each part of the serial interface device using the above protocol is as follows.

First, the state signal generator 120 receives a corresponding signal (OSIC, OSID) from the clock terminal 100 and the address / data terminal 110, respectively, and starts the program / read operation with an OTP. Outputs an EMODE signal to indicate an end condition.

The counter 130 includes a clock counter 132 consisting of a 4 bit counter for counting the number of clocks of the OSIC, and a frame composed of a 2 bit counter for distinguishing the address information 31 and the data information 35. A frame counter 134.

The counter unit 130 provides a counting result to the control signal generator 140 and the address / data buffer 150.

The control signal generator 140 includes a write / read control signal generator 142 and a mode control signal generator 144, and control signals PGM # and OE # according to the program and read operation of the OTP. And OTP mode control signals (OTPROW, OTPCOL, GANG).

The address / data buffer 150 includes an address buffer 152 and a data buffer 154. The address buffer 152 is input through the address / data terminal 110 in response to a clock signal provided from the counter 130 and a control signal provided from the counter 130 and the control signal generator 140. The serial address data is converted into parallel address data and output to OTP. The data buffer 154 converts the serial data input through the address / data terminal 110 into parallel data and provides the data to the OTP. Conversely, the parallel data provided from the OTP is converted into serial data and converted into the serial data. Output through the data terminal 110.

It takes nine OSIC clocks to transfer one byte during program or read operation. At this time, the ninth clock is a dummy clock and generates various signals related to the program or read operation of the OTP in synchronization with the ninth clock. That is, in the serial interface device according to the embodiment of the present invention, the address / data terminal 110 becomes an input port at the ninth clock after data is transmitted one byte. For example, at the end of the read operation in the read mode, the high level section of the ninth clock is made longer than the high level section of the normal clock and the read level operation is terminated because the logical level of the OSID is converted in the state where the high level section is extended. .

Again, the program operation and the read operation will be described in detail with reference to FIGS. 4 and 5.

4 is a waveform diagram of a main part according to a program operation of the serial interface device shown in FIG. 2, and FIG. 5 is a waveform diagram of a main part according to a read operation of the serial interface device shown in FIG.

First, the program operation is as follows.

Referring to FIG. 4A, at the beginning of program, as shown by reference numeral 410, the state signal generator 120 may generate a high level section in which the OSIC signal is at a voltage level of logic '1'. When the OSID signal is transitioned from a low level, which is a voltage level of logic '0', to a high level, the output of the EMODE signal is converted from a low level to a high level. Therefore, the program starts to OTP.

Referring to FIG. 4B, at the end of program, as shown by reference numeral 420, in the section in which the ninth OSIC signal is high level in the section in which the dummy data 37 is input, the OSID is low in the high level. When the signal is converted to the level, the state signal generator 120 converts the output of the EMODE signal from the high level to the low level. Therefore, the program of OTP is terminated.

4A and 4B, the serial interface device first receives 3 bytes of address information and data sequentially in synchronization with the OCIC clock. At this time, the transmitted address information is stored in the address buffer 152. The address stored in the address buffer 152 is the address where the program starts. This start address is automatically increased in the section where the program control signal PGM # is high level and in the rising edge of the dummy clock. After the program starts, the program starts at the falling edge of each dummy clock, and then the program ends at the falling edge of the eighth OSIC clock. Therefore, N pieces of data (DO to DN) inputted as OSIDs are programmed in the OTP. However, when programming the Nth data, dummy data FF is added to the N + 1th to secure the time for the Nth data to be programmed in the OTP.

Next, the read operation will be described.

5A and 5B, the serial interface device receives 3 bytes of address information in synchronization with the OSIC clock, and is stored in the address buffer 152. The control signal OE # for OTP reading is output to the OTP in synchronization with each dummy clock from the third input dummy clock. During each dummy clock, the corresponding data is read from the OTP, which is stored in the data buffer 154. The stored data is converted into serial data and output to the outside through the address / data terminal 110. The start address stored in the address buffer 152 is increased at the rising edge of the eighth clock following the dummy clock. According to such an operation, a data reading operation of the OTP is performed.

According to the present invention as described above, since the OTP serial interface device is built in the OTP-embedded microcontroller, the external program device uses a simple serial method to overcome the conventional complicated parallel method, so that the OTP program and read operation are easy. It becomes In particular, by using the serial interface method has an effect that can reduce the external terminal provided in the microcontroller.

Claims (12)

A status signal generator for receiving a clock signal OSIC having a predetermined period and an address / data signal OSID and outputting a status signal EMODE for notifying the start and end states of the program / read operation of the OTP; 120); A counter unit (130) receiving the clock signal (OSIC) and the state signal (EMODE) and outputting signals according to a counting result of the clock signal (OSIC); A control signal generator 140 receiving the output of the status signal EMODE and the counter 130 and outputting predetermined control signals for controlling the program / read operation of the OTP; And receiving an synchronization signal and a control signal provided from the counter unit 130 and the control signal generator 140, and receiving the address / data signal OSID to receive an address signal for specifying the address of the OTP. And an address / data buffer (150) for outputting by performing serial-to-parallel data conversion. 2. The apparatus of claim 1, wherein the counter comprises: a clock counter (132) for counting the number of clocks of the clock signal (OSIC); And a frame counter (134) for receiving the output of the clock counter (132) and distinguishing address information (31) and data information (35). 2. The apparatus of claim 1, wherein the control signal generator 140 includes: a write / read control signal generator 142 for outputting control signals PGM # and OE # according to program and read operation of the OTP; A serial interface device for an OTP comprising a mode control signal generator 144 for outputting an OTP mode control signal (OTPROW, OTPCOL, GANG). The method of claim 1, wherein the address / data buffer 150 receives a synchronization signal from the counter unit 130, receives and stores address data input as the address / data signal OSID in synchronization with the counter signal 130, An address buffer 152 that increases address data based on the control signals provided from the counter 130 and the control signal generator 140 and outputs the OTP to the OTP; During programming, the serial data inputted as the address / data signal (OSID) is received from the counter unit 130 in synchronization with a synchronous signal and stored therein, and are provided from the counter unit 130 and the control signal generator 140. Based on the control signal, the serial data stored in the OTP is converted into parallel data and outputted, and during the read operation, the parallel data is received and stored from the OTP in synchronization with the synchronization signal from the counter unit 130, and the counter unit 130 And a data buffer (154) for converting and outputting serial data stored in parallel based on a control signal provided from the control signal generator (140). In a microcontroller; A programmable OTP 20; A clock terminal 100 receiving a clock signal according to a program operation and a read operation of the OTP 20; An address / data terminal 110 for receiving an address signal and a data signal according to a program operation and a read operation of the OTP 20; And a serial interface device (10) for OTP performing the program and read operation of the OTP based on the signals input to the clock terminal (100) and the address / data terminal (110). . The apparatus of claim 5, wherein the serial interface device 10 receives a clock signal OSIC having a predetermined period and an address / data signal 9 OSID to inform the start state and end state of the program / read operation of the OTP. A status signal generator 120 for outputting a status signal EMODE for the controller; A counter unit (130) receiving the clock signal (OSIC) and the state signal (EMODE) and outputting signals according to a counting result of the clock signal (OSIC); A control signal generator 140 receiving the output of the status signal EMODE and the counter 130 and outputting predetermined control signals for controlling the program / read operation of the OTP; And receiving an synchronization signal and a control signal provided from the counter unit 130 and the control signal generator 140, and receiving the address / data signal OSID to receive an address signal for specifying the address of the OTP. And an address / data buffer (150) for outputting by performing serial-to-parallel data conversion. The apparatus of claim 6, wherein the counter unit comprises: a clock counter (132) for counting the number of clocks of the clock signal (OSIC); And a frame counter (134) for receiving the output of the clock counter (132) and distinguishing address information (31) and data information (35). The method of claim 6, wherein the control signal generator 140 includes: a write / read control signal generator 142 for outputting control signals PGM # and OE # according to the program and read operation of the OTP; A serial interface device for an OTP comprising a mode control signal generator 144 for outputting an OTP mode control signal (OTPROW, OTPCOL, GANG). According to claim 6, The address / data buffer 150 receives the synchronization signal from the counter unit 130, and in synchronization with this receives the address data input to the address / data signal (OSID), and stores it, An address buffer 152 that increases address data based on the control signals provided from the counter 130 and the control signal generator 140 and outputs the OTP to the OTP; During programming, the serial data inputted as the address / data signal (OSID) is received from the counter unit 130 in synchronization with a synchronous signal and stored therein, and are provided from the counter unit 130 and the control signal generator 140. Based on the control signal, the serial data stored in the OTP is converted into parallel data and outputted, and during the read operation, the parallel data is received and stored from the OTP in synchronization with the synchronization signal from the counter unit 130, and the counter unit 130 And a data buffer (154) for converting and outputting serial data stored in parallel based on a control signal provided from the control signal generator (140). A programmable OTP 20, a clock terminal 100 for receiving a clock signal according to a program and a read operation of the OTP 20, and an address signal and a data signal according to the program and read operation of the OTP 200 are input. OTP serial interface device 10 for performing program and read operation of the OTP based on the received address / data terminal 110 and the signals input to the clock terminal 100 and the address / data terminal 110. The OTP program and read control method of the microcontroller, including: a signal input to the address / data terminal 110 in a section in which a clock signal OSIC input to the clock terminal 100 maintains a constant voltage level When the OSID is converted from the first voltage level having the different voltage level to the second voltage level, any one of the program or read operation of the OTP 20 is started; When the signal OSID input to the address / data terminal 110 is converted from the second voltage level to the first voltage level in the period of maintaining the voltage level, any one of the program or read operation of the OTP 20 is performed. Define a dummy clock in the clock signal OSIC, and perform any one of a program or a read operation of the OTP 20 in synchronization with the dummy clock. Control method. The OTP program and read control method of claim 10, wherein the address / data terminal 110 is set as an input port in a section in which the dummy clock is input during a read operation. The program and read control method of the microcontroller according to claim 10, wherein in the program operation, at the end of the program, a plurality of dummy data are transmitted following the final program data to secure the program time of the final program data.