KR19990012987A - Transverse electric field liquid crystal display device - Google Patents
Transverse electric field liquid crystal display device Download PDFInfo
- Publication number
- KR19990012987A KR19990012987A KR1019970036569A KR19970036569A KR19990012987A KR 19990012987 A KR19990012987 A KR 19990012987A KR 1019970036569 A KR1019970036569 A KR 1019970036569A KR 19970036569 A KR19970036569 A KR 19970036569A KR 19990012987 A KR19990012987 A KR 19990012987A
- Authority
- KR
- South Korea
- Prior art keywords
- electrode
- liquid crystal
- electric field
- crystal display
- transverse electric
- Prior art date
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims abstract description 99
- 230000005684 electric field Effects 0.000 title claims abstract description 71
- 239000010409 thin film Substances 0.000 claims abstract description 41
- 238000002161 passivation Methods 0.000 claims abstract description 22
- 239000004065 semiconductor Substances 0.000 claims abstract 7
- 239000000758 substrate Substances 0.000 claims description 59
- 239000010408 film Substances 0.000 claims description 51
- 239000002184 metal Substances 0.000 claims description 39
- 239000000463 material Substances 0.000 claims description 31
- 238000000034 method Methods 0.000 claims description 15
- 230000001681 protective effect Effects 0.000 claims description 12
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- -1 polysiloxane Polymers 0.000 claims description 8
- 229920001296 polysiloxane Polymers 0.000 claims description 8
- 230000000903 blocking effect Effects 0.000 abstract description 15
- 239000010410 layer Substances 0.000 description 75
- 230000001678 irradiating effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 241000270730 Alligator mississippiensis Species 0.000 description 1
- 229910019923 CrOx Inorganic materials 0.000 description 1
- 239000004988 Nematic liquid crystal Substances 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 101150037603 cst-1 gene Proteins 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
- G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1337—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers
- G02F1/133711—Surface-induced orientation of the liquid crystal molecules, e.g. by alignment layers by organic films, e.g. polymeric films
- G02F1/133723—Polyimide, polyamide-imide
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Geometry (AREA)
Abstract
본 발명의 횡전계방식 액정표시장치는 공통전극이 형성되는 보호막 위의 게이트전극 영역에 차광전극이 형성되어 백게이트전극 역할을 함과 동시에 백라이트나 외부로부터 반도체층에 빛이 입사되어 박막트랜지스터에 누설전류가 발생하는 것을 방지한다. 공통전극은 게이트배선과 데이터배선의 일부분과 오버랩되어 게이트배선과 데이터배선에 의한 전계를 차단하여 화상에 전경이 발생하는 것을 방지한다.In the transverse electric field liquid crystal display device of the present invention, a light blocking electrode is formed in a gate electrode area on a passivation layer on which a common electrode is formed to serve as a back gate electrode, and light is incident on a semiconductor layer from a backlight or the outside to leak into a thin film transistor. Prevents current from occurring The common electrode overlaps a portion of the gate wiring and the data wiring to block an electric field by the gate wiring and the data wiring, thereby preventing the foreground from occurring in the image.
Description
본 발명은 액정표시장치에 관한 것으로, 고휘도이고 고정세이며 제조비용이 절감된 횡전계방식 액정표시장치에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and to a transverse electric field type liquid crystal display device having high brightness, high definition, and low manufacturing cost.
최근, 휴대용 텔레비젼이나 노트북 컴퓨터에 많이 사용되는 박막트랜지스터 액정표시장치(TFT LCD)에서 대면적화가 강력하게 요구되고 있지만, 상기한 TFT LCD에는 시야각에 따라 콘트라스트비(contrast ratio)가 변하는 문제가 있었다. 이러한 문제를 해결하기 위해, 광보상판이 장착된 트위스트네마틱(twisted nematic) 액정표시장치, 멀티도메인(multi-domain) 액정표시장치 등과 같은 여러가지 액정표시장치가 제안되고 있지만, 이러한 여러가지 액정표시장치로는 시야각에 따라 콘트라스트비가 저하되고 색상이 변하는 문제를 해결하기 힘든 실정이다.Recently, a large area has been strongly demanded in thin film transistor liquid crystal displays (TFT LCDs), which are widely used in portable televisions and notebook computers. However, the above-described TFT LCDs have a problem in that contrast ratio is changed depending on the viewing angle. In order to solve this problem, various liquid crystal display devices such as a twisted nematic liquid crystal display device equipped with an optical compensation plate and a multi-domain liquid crystal display device have been proposed. It is difficult to solve the problem that the contrast ratio decreases and the color changes depending on the viewing angle.
광시야각을 실현하기 위해 제안되는 다른 방식의 액정표시장치인 횡전계방식(in plane switching mode)의 액정표시장치가 JAPAN DISPLAY 92 P547, 일본특허 특개평 7-36058, 일본특허 특개평 7-225538, ASIA DISPALY 95 P107 등에 제안되고 있다.Another type of liquid crystal display device that is proposed to realize a wide viewing angle is a liquid crystal display device of the in plane switching mode (JAPAN DISPLAY 92 P547, Japanese Patent Laid-Open No. 7-36058, Japanese Patent Laid-Open No. 7-225538, It is proposed to ASIA DISPALY 95 P107.
도 1은 종래의 횡전계방식 액정표시장치를 나타내는 도면이다. 상기한 종래의 횡전계방식 액정표시장치는 도 1(a)에 나타낸 바와 같이, 제1기판(10) 위에 배열되어 화소영역을 정의하는 게이트배선(1) 및 데이터배선(2)과, 상기한 게이트배선(1)과 평행하게 화소 내에 배열된 공통배선(3)과, 상기한 게이트배선(1)과 데이터배선(2)의 교차점에 배치된 박막트랜지스터와, 상기한 화소 내에 데이터배선(2)과 대략 평행하게 배열된 데이터전극(8) 및 공통전극(9)으로 구성된다. 도 1(b)에 나타낸 바와 같이, 박막트랜지스터는 제1기판(10) 위에 형성되어 게이트배선(1)과 접속되는 게이트전극(5)과, 상기한 게이트전극(5) 위에 적층된 게이트절연막(12)과, 상기한 게이트절연막(12) 위에 형성된 활성층(15)과, 상기한 활성층(15) 위에 형성된 n+층(16)과, 상기한 n+층(16) 위에 형성되어 데이터배선(2)과 데이터전극(8)에 각각 접속되는 소스전극(6) 및 드레인전극(7)으로 구성된다. 화소 내의 공통전극(9)은 제1기판(10) 위에 형성되어 공통배선(3)에 접속되며 데이터전극(8)은 게이트절연막(12) 위에 형성되어 박막트랜지스터의 드레인전극(7)에 접속된다. 박막트랜지스터, 데이터전극(8) 및 게이트절연막(12) 위에는 보호막(20)이 적층되어 있으며, 그 위에 제1배향막(23a)이 도포되고 배향방향이 결정된다.1 is a view showing a conventional transverse electric field type liquid crystal display device. In the conventional transverse electric field type liquid crystal display device, as shown in FIG. 1A, the gate line 1 and the data line 2 are arranged on the first substrate 10 to define a pixel area. The common wiring 3 arranged in the pixel in parallel with the gate wiring 1, the thin film transistor arranged at the intersection of the gate wiring 1 and the data wiring 2, and the data wiring 2 in the pixel. And a data electrode 8 and a common electrode 9 arranged in substantially parallel with each other. As shown in FIG. 1B, the TFT may include a gate electrode 5 formed on the first substrate 10 and connected to the gate wiring 1, and a gate insulating layer stacked on the gate electrode 5. 12), it is formed on the active layer 15 and the n + layer 16 and the one n + layer 16 is formed on the above-described active layer 15 formed on the gate insulating film 12, data wire (2 ) And a source electrode 6 and a drain electrode 7 respectively connected to the data electrode 8. The common electrode 9 in the pixel is formed on the first substrate 10 and connected to the common wiring 3, and the data electrode 8 is formed on the gate insulating film 12 and connected to the drain electrode 7 of the thin film transistor. . A protective film 20 is stacked on the thin film transistor, the data electrode 8 and the gate insulating film 12, and the first alignment film 23a is coated thereon, and the orientation direction is determined.
제2기판(11)에는 박막트랜지스터, 게이트배선(1), 데이터배선(2), 공통배선(3) 근처로 빛이 새는 것을 방지하는 차광층(28)이 형성되어 있으며, 그 위에 컬러필터층(29) 및 제2배향막(23b)이 형성되어 있다. 또한, 상기한 제1기판(10) 및 제2기판(11) 사이에는 액정층(30)이 형성되어 있다.The second substrate 11 is formed with a light blocking layer 28 that prevents light leakage near the thin film transistor, the gate wiring 1, the data wiring 2, and the common wiring 3. 29) and the second alignment film 23b are formed. In addition, a liquid crystal layer 30 is formed between the first substrate 10 and the second substrate 11.
상기한 바와 같이 구성된 횡전계방식 액정표시장치에 있어서, 외부구동회로로부터 전압이 인가되면, 데이터전극(8)과 공통전극(9) 사이에 기판(10, 11)과 평행한 횡전계가 발생한다. 따라서, 액정층(30) 내에 배향된 액정분자가 상기한 횡전계를 따라 회전하게 되며, 그 결과 액정층(30)을 통과하는 빛의 양을 제어하게 된다.In the transverse electric field type liquid crystal display device configured as described above, when a voltage is applied from an external driving circuit, a transverse electric field parallel to the substrates 10 and 11 is generated between the data electrode 8 and the common electrode 9. . Accordingly, the liquid crystal molecules oriented in the liquid crystal layer 30 rotate along the above-described transverse electric field, thereby controlling the amount of light passing through the liquid crystal layer 30.
그러나, 상기한 바와 같은 종래의 횡전계방식 액정표시장치에는 다음과 같은 문제가 있다. 첫째, 게이트배선(1), 데이터배선(2), 박막트랜지스터 근처로 빛이 새는 것을 방지하기 위해 차광층(28)을 형성하기 때문에, 제조비용이 증가한다. 또한, 상기한 차광층(28)을 형성하기 위해서는 Cr이나 CrOx와 같은 금속을 적층한 후 에칭하거나 검은색 수지 등을 도포한 후 에칭해야만 하기 때문에 수율이 저하되는 문제도 있다. 둘째, 데이터전극(8) 위에 보호막(20)이 적층되어 있고 공통전극(9) 위에 게이트절연막(12)과 보호막(20)이 형성되어 있기 때문에, 액정층(30) 내에 인가되는 횡전계가 상기한 게이트절연막(12)과 보호막(20)에 흡수되어 액정층(30) 내에 인가되는 횡전계의 세기가 작아진다. 따라서, 액정분자의 구동속도가 저하되어 동영상의 구현시 화면이 끊어지는 현상이 발생하게 된다. 셋째, 제1기판(10)과 제2기판(11)의 합착시 정확한 합착이 이루어지지 않으면, 블랙마스크(28)가 화소영역을 침범하게 되어 개구율이 저하되는데, 상기한 기판의 정확한 합착은 대단히 어려운 실정이다. 넷째, 게이트배선(1)과 데이터배선(2)에 의해 발생하는 전계에 기인하는 크로스토크(crosstalk)를 방지하기 위해 게이트배선(1) 및 데이터배선(2)과 실제의 화상이 구현되는 화소영역이 일정 거리 이상 떨어져 있어야 하기 때문에, 개구율이 더욱 저하된다.However, the above-described conventional transverse electric field type liquid crystal display has the following problems. First, since the light shielding layer 28 is formed to prevent light leakage near the gate wiring 1, the data wiring 2, and the thin film transistor, the manufacturing cost increases. In addition, in order to form the light-shielding layer 28 described above, since a metal such as Cr or CrOx must be laminated and etched or coated with a black resin or the like, there is also a problem that the yield decreases. Second, since the passivation layer 20 is stacked on the data electrode 8 and the gate insulating layer 12 and the passivation layer 20 are formed on the common electrode 9, the transverse electric field applied to the liquid crystal layer 30 is the above-mentioned. The strength of the transverse electric field absorbed by the gate insulating film 12 and the protective film 20 and applied to the liquid crystal layer 30 is reduced. Therefore, the driving speed of the liquid crystal molecules is lowered, which causes the screen to break when the video is implemented. Third, when the first substrate 10 and the second substrate 11 are not bonded correctly, the black mask 28 may invade the pixel region and the aperture ratio is lowered. It is difficult. Fourth, a pixel region in which an actual image is realized with the gate wiring 1 and the data wiring 2 in order to prevent crosstalk due to the electric field generated by the gate wiring 1 and the data wiring 2. Since the distance must be at least a certain distance, the aperture ratio is further lowered.
본 발명은 상기한 점을 감안하여 이루어진 것으로, 게이트전극과 게이트배선의 일부분 위에 차광전극을 형성하고, 상기한 차광전극을 게이트배선에 접속하여 고휘도이고 제조비용이 절감된 횡전계방식 액정표시장치를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has a transverse electric field type liquid crystal display device in which a light shielding electrode is formed on a portion of a gate electrode and a gate wiring, and the light shielding electrode is connected to the gate wiring to achieve high brightness and reduced manufacturing cost. It aims to provide.
본 발명의 다른 목적은 공통전극을 게이트배선과 데이터배선의 일부분과 오버랩시켜 상기한 게이트배선과 데이터배선에 의한 전계를 차단함으로써 전경을 방지함과 동시에 개구율이 향상된 횡전계방식 액정표시장치를 제공하는 것이다.Another object of the present invention is to provide a transverse electric field type liquid crystal display device having a common electrode overlapping a portion of a gate wiring and a data wiring to block the electric field by the gate wiring and the data wiring, thereby preventing the foreground and improving the aperture ratio. will be.
상기한 목적을 달성하기 위해, 본 발명에 따른 횡전계방식 액정표시장치는 제1기판 및 제2기판과, 상기한 제1기판 위에 종횡으로 교차하여 화소영역을 정의하는 게이트배선 및 데이터배선과, 상기한 게이트배선과 데이터배선의 교차부분에 배치된 박막트랜지스터와, 화소영역 내에 상기한 게이트배선과 평행하게 배열된 공통배선과, 상기한 화소영역에 데이터배선과 평행하게 배열된 데이터전극과, 상기한 데이터전극과 평행하게 배열된 공통전극과, 상기한 박막트랜지스터와 게이트배선의 일부분 위에 게이트배선과 접속되도록 형성되어 백게이트전극 역할을 함과 동시에 박막트랜지스터로 빛이 입사되는 것을 방지하는 차광전극과, 상기한 제1기판 전체에 걸쳐서 도포된 제1배향막과, 상기한 제2기판 위에 형성된 컬러필터층과, 상기한 컬러필터층 위에 도포된 제2배향막과, 상기한 제1기판과 제2기판 사이에 형성된 액정층으로 구성된다.In order to achieve the above object, a transverse electric field liquid crystal display device according to the present invention comprises a gate wiring and a data wiring for defining a pixel region by crossing the first substrate and the second substrate, and vertically and horizontally on the first substrate; A thin film transistor disposed at an intersection of the gate wiring and the data wiring, a common wiring arranged in parallel with the gate wiring in a pixel region, a data electrode arranged in parallel with the data wiring in the pixel region, and A common electrode arranged in parallel with one data electrode, a light blocking electrode formed on the thin film transistor and a portion of the gate wiring so as to be connected to the gate wiring, and serving as a back gate electrode, and preventing light from being incident on the thin film transistor; And a first alignment layer applied over the entire first substrate, a color filter layer formed on the second substrate, and the color filter layer. The first consists of a liquid crystal layer formed between the second alignment layer and, above the first substrate and the second substrate applied to.
박막트랜지스터는 게이트배선과 접속된 게이트전극과, 상기한 게이트전극 위에 제1기판 전체에 걸쳐서 적층된 게이트절연막과, 상기한 게이트절연막 위에 형성된 활성층과, 상기한 활성층 위에 형성된 n+층과, 상기한 n+층 위에 형성된 소스전극 및 드레인전극으로 구성된다.The thin film transistor includes a gate electrode connected to a gate wiring, a gate insulating film stacked over the first substrate on the gate electrode, an active layer formed on the gate insulating film, an n + layer formed on the active layer, and a source electrode and a drain electrode formed on the n + layer.
데이터전극은 게이트절연막 위에 형성되어 드레인전극과 접속되며, 공통전극은 보호막 위에 형성되어 홀을 통해 공통배선에 접속된다. 상기한 데이터전극과 공통전극은 그 사이에 부가용량을 형성함으로써, 액정표시장치 전체에 2중의 부가용량을 인가한다. 또한, 차광전극은 상기한 공통전극과 동일한 층에 동시에 형성되어 보호막의 홀을 통해 게이트배선에 접속된다.The data electrode is formed on the gate insulating film and connected to the drain electrode, and the common electrode is formed on the passivation film and connected to the common wiring through the hole. The data electrode and the common electrode form an additional capacitance therebetween, thereby applying a double additional capacitance to the entire liquid crystal display device. In addition, the light blocking electrode is simultaneously formed on the same layer as the common electrode and connected to the gate wiring through the hole of the protective film.
본 발명의 다른 관점에 의한 횡전계방식 액정표시장치는 제1기판 및 제2기판과, 상기한 제1기판 위에 종횡으로 교차하여 화소영역을 정의하는 게이트배선 및 데이터배선과, 상기한 게이트배선과 데이터배선의 교차부분에 배치된 박막트랜지스터와, 상기한 화소영역에 게이트배선과 평행하게 배열된 공통배선과, 상기한 화소영역에 데이터배선과 평행하게 배열된 데이터전극과, 상기한 데이터전극과 평행하게 배열되며 게이트배선과 데이터배선의 일부분과 오버랩되어 상기한 게이트배선과 데이터배선으로부터의 전계를 차단하는 공통전극과, 상기한 박막트랜지스터의 게이트전극과 게이트배선의 일부분 위에 형성되고 보호막의 홀을 통해 게이트배선에 접속되어 백게이트전극의 역할을 함과 동시에 박막트랜지스터의 활성층으로 빛이 조사되는 것을 방지하는 차광전극과, 상기한 제1기판 전체에 걸쳐서 도포된 제1배향막과, 상기한 제2기판 위에 형성된 컬러필터층과, 상기한 컬러필터층 위에 도포된 제2배향막과, 상기한 제1기판과 제2기판 사이에 형성된 액정층으로 구성된다.According to another aspect of the present invention, there is provided a transverse electric field type liquid crystal display device comprising: a gate wiring and a data wiring defining a pixel region by crossing the first substrate and the second substrate vertically and horizontally on the first substrate; A thin film transistor arranged at an intersection of the data lines, a common line arranged in parallel with the gate line in the pixel area, a data electrode arranged in parallel with the data line in the pixel area, and parallel to the data electrode And a common electrode which overlaps a portion of the gate line and the data line to block an electric field from the gate line and the data line, and is formed on a portion of the gate electrode and the gate line of the thin film transistor and formed through a hole in the protective layer. Light is irradiated to the active layer of the thin film transistor while being connected to the gate wiring and serving as a back gate electrode. A light shielding electrode for preventing, a first alignment film applied over the first substrate, a color filter layer formed on the second substrate, a second alignment film applied on the color filter layer, and the first substrate; It consists of a liquid crystal layer formed between 2nd board | substrates.
도 1은, 종래의 횡전계방식 액정표시장치를 나타내는 도면.1 is a view showing a conventional transverse electric field type liquid crystal display device.
도 2는, 본 발명의 제1실시예 따른 횡전계방식 액정표시장치의 평면도.2 is a plan view of a transverse electric field type liquid crystal display device according to a first embodiment of the present invention.
도 3(a)는, 도 2의 B-B'선 단면도.FIG. 3A is a cross-sectional view taken along the line BB ′ of FIG. 2.
도 3(b)는, 도 2의 C-C'선 단면도.FIG. 3B is a cross-sectional view taken along the line CC 'of FIG. 2.
도 3(c)는, 도 2의 D-D'선 단면도.(C) is sectional drawing in the DD 'line | wire of FIG.
도 4는, 본 발명의 제1실시예에 따른 횡전계방식 액정표시장치에서의 광학축방향을 나타내는 도면.Fig. 4 is a diagram showing the optical axis direction in the transverse electric field type liquid crystal display device according to the first embodiment of the present invention.
도 5는, 본 발명에 따른 횡전계방식 액정표시장치에서 액정분자의 구동을 나타내는 개략도.5 is a schematic diagram showing driving of liquid crystal molecules in a transverse electric field type liquid crystal display device according to the present invention;
도 6은, 본 발명에 따른 액정패널의 구성도.6 is a block diagram of a liquid crystal panel according to the present invention.
도 7은, 본 발명이 적용된 횡전계방식 액정표시장치의 구성도.7 is a configuration diagram of a transverse electric field type liquid crystal display device to which the present invention is applied.
도 8은, 본 발명의 제2실시예에 따른 횡전계방식 액정표시장치의 평면도.8 is a plan view of a transverse electric field type liquid crystal display device according to a second embodiment of the present invention.
- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-
101, 201 : 게이트배선 102, 202 : 데이터배선101, 201: gate wiring 102, 202: data wiring
103, 203 : 공통배선 105, 205 : 게이트전극103, 203: common wiring 105, 205: gate electrode
106, 206 : 소스전극 107, 207 : 드레인전극106, 206: source electrode 107, 207: drain electrode
108, 208 : 데이터전극 109, 209 : 공통전극108, 208: data electrode 109, 209: common electrode
110 : 제1기판 111 : 제2기판110: first substrate 111: second substrate
112 : 게이트절연막 115 : 활성층112: gate insulating film 115: active layer
116 : n+층 123 : 배향막116: n + layer 123: alignment layer
125, 225, 325 : 홀 130 : 액정층125, 225, 325: hole 130: liquid crystal layer
132, 133 : 액정분자 135 : 편광판132, 133: liquid crystal molecules 135: polarizing plate
136 : 검광판 139 : 액정패널136: detection plate 139: liquid crystal panel
140 : 표시부 145 : 프레임140: display unit 145: frame
147 : 백라이트하우징 148 : 백라이트147: backlight housing 148: backlight
149 : 도광판 150 : 게이트구동회로149: light guide plate 150: gate driving circuit
151 : 게이트패드 154 : 데이터구동회로151: gate pad 154: data driving circuit
155 : 데이터패드 157 : 공통패드155: data pad 157: common pad
160 : 차광전극 161 : 홀160: light blocking electrode 161: hole
165 : 외부접지회로 167 : 정전기방지회로165: external ground circuit 167: antistatic circuit
이하, 첨부한 도면을 참조하여 본 발명에 따른 횡전계방식 액정표시장치를 상세히 설명한다.Hereinafter, a transverse electric field type liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 제1실시예를 나타내는 도면이다. 도면에 나타낸 바와 같이, 기판 위에는 복수의 게이트배선(101) 및 데이터배선(102)이 배열되어 화소영역을 정의한다. 실제의 액정표시장치에서는 n개의 게이트배선(101)과 m개의 데이터배선(102)에 의해 n×m개의 화소가 존재하지만, 도면에서는 설명의 편의를 위해 한 화소만을 나타내었다. 화소 내에는 상기한 게이트배선(101)과 평행하게 공통배선(103)이 배열되어 있으며, 게이트배선(101)과 데이터배선(102)의 교차점에는 박막트랜지스터가 배치되어 있다. 화소 내에 배열된 데이터전극(108)과 공통전극(109)은 데이터배선(102)과 평행하게 배열되어 있다. 이때, 데이터전극(108)과 공통전극(109)은 각각 공통배선(103) 위에도 형성된다. 상기한 공통전극(109)은 보호막의 홀(125)을 통해 공통배선(103)에 접속된다. 또한, 도면에 나타낸 바와 같이, 박막트랜지스터의 게이트전극(105)과 게이트배선(101)의 일부분 위에는 차광전극(160)이 형성되어 홀(161)을 통해 상기한 게이트배선(101)에 접속된다.2 is a diagram showing a first embodiment of the present invention. As shown in the figure, a plurality of gate wirings 101 and data wirings 102 are arranged on a substrate to define a pixel region. In the actual liquid crystal display device, n x m pixels exist by the n gate wirings 101 and the m data wirings 102, but only one pixel is shown in the drawing for convenience of description. The common wiring 103 is arranged in parallel with the gate wiring 101 in the pixel, and a thin film transistor is disposed at the intersection of the gate wiring 101 and the data wiring 102. The data electrode 108 and the common electrode 109 arranged in the pixel are arranged in parallel with the data wiring 102. In this case, the data electrode 108 and the common electrode 109 are also formed on the common wiring 103, respectively. The common electrode 109 is connected to the common wiring 103 through the hole 125 of the passivation layer. In addition, as shown in the drawing, a light blocking electrode 160 is formed on a portion of the gate electrode 105 and the gate wiring 101 of the thin film transistor and is connected to the gate wiring 101 through the hole 161.
도 3(a)는 도 2의 B-B'선 단면도이다. 도면에 나타낸 바와 같이, 박막트랜지스터는 제1기판(110) 위에 형성된 게이트전극(105)과, 상기한 게이트전극(105) 위에 적층된 게이트절연막(112)과, 상기한 게이트절연막(112) 위에 형성된 활성층(115)과 상기한 활성층(115) 위에 형성된 n+층(116)과, 상기한 n+층(116) 위에 형성된 소스전극(106) 및 드레인전극(107)으로 구성된다. 게이트전극(105)은 게이트배선(101) 및 공통배선(103)과 동시에 형성되는 것으로, 스퍼터링방법에 의해 적층된 2000Å 두께의 Al박막과 1000Å 두께의 Mo박막 등으로 이루어진 2중막을 에칭하여 형성하며, 게이트절연막(112)은 제1기판(110) 전체에 걸쳐서 SiNx 등과 같은 무기물을 CVD(chemical vapor deposition)방법으로 4000Å 두께로 적층하여 형성한다. 활성층(115) 및 n+층(116)은 CVD방법에 의해 적층된 1700Å 두께의 비정질실리콘(a-Si)과 300Å 두께의 n+a-Si를 에칭하여 형성한다. 데이터배선(102), 소스전극(106), 드레인전극(107), 데이터전극(108)은 스퍼터링방법으로 적층된 1500Å 두께의 Cr박막을 에칭하여 형성한다. 도 2에 나타낸 바와 같이, 박막트랜지스터의 게이트전극(105)은 게이트배선(101)에 연결되고 소스전극(106)은 데이터배선(102)에 연결되며, 드레인전극(107)은 데이터전극(108)에 연결된다.(A) is sectional drawing in the BB 'line | wire of FIG. As shown in the drawing, the thin film transistor is formed on the gate electrode 105 formed on the first substrate 110, the gate insulating film 112 stacked on the gate electrode 105, and on the gate insulating film 112. The active layer 115 and the n + layer 116 formed on the active layer 115 and the source electrode 106 and the drain electrode 107 formed on the n + layer 116 described above. The gate electrode 105 is formed at the same time as the gate wiring 101 and the common wiring 103. The gate electrode 105 is formed by etching a double film made of an Al thin film having a thickness of 2000 GPa and a Mo thin film having a thickness of 1000 GPa by a sputtering method. The gate insulating film 112 is formed by stacking an inorganic material, such as SiNx, on the entire first substrate 110 to a thickness of 4000 kPa by a chemical vapor deposition (CVD) method. The active layer 115 and the n + layer 116 are formed by etching 1700 Å thick amorphous silicon (a-Si) and 300 Å thick n + a-Si deposited by the CVD method. The data wiring 102, the source electrode 106, the drain electrode 107, and the data electrode 108 are formed by etching a 1500 Å thick Cr thin film deposited by a sputtering method. As shown in FIG. 2, the gate electrode 105 of the thin film transistor is connected to the gate wiring 101, the source electrode 106 is connected to the data wiring 102, and the drain electrode 107 is connected to the data electrode 108. Is connected to.
박막트랜지스터, 게이터배선(108), 게이트절연막(112) 위에는 2000Å 두께의 SiNx 등으로 이루어진 보호막(120)이 적층되어 있으며, 그 위에 공통전극(109)이 형성되어 있다. 공통전극(109)은 스퍼터링방법에 의해 적층된 약 1000Å의 Mo박막 또는 ITO/MO박막을 에칭하여 형성한다.On the thin film transistor, the gator wiring 108 and the gate insulating film 112, a protective film 120 made of SiNx having a thickness of 2000 Å is stacked, and a common electrode 109 is formed thereon. The common electrode 109 is formed by etching a Mo thin film or an ITO / MO thin film of about 1000 mW stacked by a sputtering method.
보호막(120) 위의 게이트전극(105)과 게이트배선(101) 영역에는 차광전극(160)이 형성된다. 차광전극(160)은 공통전극(109)과 동일한 공정에 의해 형성된 약 1000Å의 Mo 금속층으로, 도 3(b)에 나타낸 바와 같이, 게이트절연막(112)과 보호막(120)에 형성된 홀(161)을 통해 게이트배선(101)에 전기적으로 접속된다. 따라서, 외부구동회로로부터 게이트전극(105)에 전압이 인가되는 경우 상기한 차광전극(160) 역시 상기한 게이트전극(105)과 동전위를 형성한다.The light blocking electrode 160 is formed in the gate electrode 105 and the gate wiring 101 region on the passivation layer 120. The light blocking electrode 160 is a Mo metal layer having a thickness of about 1000 mV formed by the same process as the common electrode 109. As shown in FIG. 3 (b), the hole 161 formed in the gate insulating film 112 and the protective film 120 is formed. It is electrically connected to the gate wiring 101 through. Therefore, when voltage is applied to the gate electrode 105 from the external driving circuit, the light blocking electrode 160 also forms a coin phase with the gate electrode 105.
차광전극(160)은 보호막(120)을 사이에 두고 게이트전극(105) 위에 직접 형성되어 있기 때문에, 백라이트나 외부로부터의 빛이 박막트랜지스터의 활성층(115)으로 입사되는 것을 방지한다. 따라서, 박막트랜지스터의 오프(off)상태시 빛의 입사에 의해 활성층(115)이 여기되어 누설전류(leakage current)가 발생하는 것을 방지하기 때문에, 화질이 더욱 향상된다. 또한, 차광전극(160)이 게이트전극(105) 바로 위에 형성되기 때문에, 고강도의 백라이트를 사용하는 것이 가능하게 되어 휘도가 향상된다. 더욱이, 상기한 차광전극(160)이 홀(161)을 통해 게이트배선(101)에 접속되어 게이트전극(105)과 동전위를 이루고 있기 때문에, 상기한 차광전극(160)이 백게이트전극(back gate electrode)의 역할을 하게 되어 박막트랜지스터의 온전류가 증가한다. 이러한 온전류의 증가는 박막트랜지스터의 스위칭속도를 향상시키는 요인이 되는데, 종래의 액정표시장치에서와 같은 특정한 스위칭속도가 필요한 경우에는 박막트랜지스터를 작게 형성할 수 있기 때문에 박막트랜지스터의 고정세가 가능하게 된다.Since the light blocking electrode 160 is formed directly on the gate electrode 105 with the passivation layer 120 interposed therebetween, light from the backlight or the outside is prevented from entering the active layer 115 of the thin film transistor. Therefore, since the active layer 115 is excited by the incident light in the off state of the thin film transistor and prevents leakage current, the image quality is further improved. In addition, since the light shielding electrode 160 is formed directly on the gate electrode 105, it becomes possible to use a high intensity backlight and the luminance is improved. Furthermore, since the light blocking electrode 160 is connected to the gate wiring 101 through the hole 161 to form a coincidence with the gate electrode 105, the light blocking electrode 160 is a back gate electrode (back). It acts as a gate electrode, increasing the on-current of the thin film transistor. The increase in the on-current is a factor to improve the switching speed of the thin film transistor. When the specific switching speed is required as in the conventional liquid crystal display device, the thin film transistor can be made small, so that the thin film transistor can be fixed. .
그리고, 종래와는 달리 제2기판(111)에 블랙마스크가 형성되지 않기 때문에 제조비용이 증가함과 동시에 합착의 정밀도에 의한 개구율 저하가 발생하지 않게 된다.Unlike the related art, since the black mask is not formed on the second substrate 111, the manufacturing cost increases and the opening ratio decrease due to the precision of the bonding does not occur.
제1배향막(123a)은 공통전극(109)과 보호막(120) 위에 도포되어 있다. 폴리이미드로 이루어진 배향막(123a)은 기계적인 러빙(rubbing)에 의해 배향방향이 결정되지만, PVCN(polyvinylcinnemate)계 물질이나 폴리실록산계 물질과 같은 광반응성 물질로 이루어진 배향막(123a)은 자외선과 같은 광의 조사에 의해 배향방향이 결정된다. 상기한 광배향처리에서는 조사되는 광의 편광여부, 편광방향, 조사횟수에 따라 배향방향이 결정된다. 일반적으로, 상기한 폴리실록산계 물질이나 PVCN계 물질을 배향막으로 사용하는 경우에는, 자외선을 1회 조사하거나 2회 조사하여 배향방향을 결정한다. 광을 1회 조사하는 방법에는 배향막에 대해서 비편광된 광을 경사조사하는 방법, 편광된(특히, 선편광된) 광을 경사조사하는 방법, 부분 편광된 광을 경사조사하는 방법 등이 있으며, 광을 2회 조사하는 방법에서는 배향막에 대하여 편광된 광을 1회 경사 혹은 수직조사하여 2개의 축퇴(degeneracy)된 배향방향을 결정한 후 다시 편광된 광을 조사하여 2개의 배향방향중 원하는 방향을 선택한다.The first alignment layer 123a is coated on the common electrode 109 and the passivation layer 120. Although the alignment direction 123a made of polyimide is determined by mechanical rubbing, the alignment film 123a made of photoreactive material such as polyvinylcinnemate (PVCN) -based material or polysiloxane-based material is irradiated with light such as ultraviolet rays. The orientation direction is determined by. In the optical alignment process described above, the alignment direction is determined according to whether the irradiated light is polarized, the polarization direction, and the number of irradiation times. In general, in the case where the above-described polysiloxane-based material or PVCN-based material is used as the alignment film, the alignment direction is determined by irradiating the ultraviolet light once or twice. The method of irradiating light once includes a method of obliquely irradiating unpolarized light with respect to the alignment layer, a method of obliquely irradiating polarized (particularly linearly polarized) light, a method of obliquely irradiating partially polarized light, and the like. In the method of irradiating twice, the two degeneracy alignment directions are determined by inclining or vertically irradiating the polarized light with respect to the alignment layer once, and then irradiating the polarized light again to select a desired direction among the two alignment directions. .
도 2에 나타낸 바와 같이, 보호막(120)에는 홀(125)이 형성되어 공통전극(109)이 상기한 홀을 통해 공통배선(103)에 접속된다. 도 3(c)는 상기한 접속을 나타내는 도 2의 D-D'선 단면도이다. 도면에 나타낸 바와 같이, 데이터전극(108)과 공통전극(109)은 각각 게이트절연막(112)과 보호막(120) 위에 형성된 금속배선들에 연결된다. 물론, 이 금속배선들은 각각 데이터전극(108) 및 공통전극(109)과 동일한 금속으로 동시에 형성된다. 따라서, 데이터전극(108)이 접속된 금속배선과 공통배선(103) 사이, 공통전극(109)이 접속된 금속배선과 데이터전극(108)이 접속되는 금속배선 사이에는 각각 게이트절연막(112)과 보호막(120)이 적층되어 있기 때문에, 도면에 나타낸 바와 같이, 부가용량(storage capacity;Cst)이 데이터전극(108)과 공통전극(109) 사이의 부가용량(Cst1)과 공통배선(103)과 데이터전극(108) 사이의 부가용량(Cst2)의 합이 되어 종래의 부가용량(Cst2) 보다 커진다. 따라서, 액정층(130)에 인가되는 전압을 더욱 안정화 시킬 뿐만 아니라, 종래와 비슷한 부가용량을 부여하는 경우에는 부가용량 면적을 감소시킴으로써 개구율을 더욱 향상시킬 수 있게 된다. 또한, 공통전극(109)이 보호막(120) 위에 형성되어 있기 때문에, 절연막에 의한 전계의 흡수가 발생하지 않게 되어 강한 세기의 전계가 액정층(130)에 인가된다. 그러므로, 구동전압을 낮출 수 있게 된다.As shown in FIG. 2, a hole 125 is formed in the passivation layer 120 so that the common electrode 109 is connected to the common wiring 103 through the hole. (C) is sectional drawing in the DD 'line | wire of FIG. 2 which shows said connection. As shown in the figure, the data electrode 108 and the common electrode 109 are connected to metal wirings formed on the gate insulating film 112 and the passivation layer 120, respectively. Of course, these metal wires are simultaneously formed of the same metal as the data electrode 108 and the common electrode 109, respectively. Therefore, the gate insulating film 112 and the metal wiring to which the data electrode 108 is connected and the common wiring 103 are connected between the metal wiring to which the common electrode 109 is connected and the metal wiring to which the data electrode 108 is connected, respectively. Since the passivation layer 120 is stacked, as shown in the drawing, the storage capacity Cst is equal to the additional capacitance Cst1 and the common wiring 103 between the data electrode 108 and the common electrode 109. The sum of the additional capacitances Cst2 between the data electrodes 108 is greater than the conventional additional capacitance Cst2. Therefore, not only the voltage applied to the liquid crystal layer 130 is further stabilized, but also when the additional capacitance similar to the conventional one is provided, the opening ratio can be further improved by reducing the additional capacitance area. In addition, since the common electrode 109 is formed on the passivation layer 120, absorption of an electric field by the insulating layer does not occur, and an electric field of strong intensity is applied to the liquid crystal layer 130. Therefore, the driving voltage can be lowered.
제2기판(111)에는 컬러필터층(129)이 형성되어 있다. 컬러필터층(129)에는 R, G, B층이 화소마다 반복 형성되어 있다. 컬러필터층(129) 위에는 폴리이미드나 광반응성물질로 이루어진 제2배향막(123b)이 도포된 후 러빙이나 광의 조사에 의해 배향방향이 결정된다. 또한, 제1기판(110)과 제2기판(111) 사이에는 진공상태에서 액정이 주입되어 액정층(130)이 형성된다.The color filter layer 129 is formed on the second substrate 111. In the color filter layer 129, R, G, and B layers are repeatedly formed for each pixel. After the second alignment layer 123b made of polyimide or a photoreactive material is coated on the color filter layer 129, the orientation direction is determined by rubbing or irradiation of light. In addition, a liquid crystal is injected in a vacuum state between the first substrate 110 and the second substrate 111 to form the liquid crystal layer 130.
도 4는 본 발명의 제1실시예에 따른 액정표시장치의 광학축방향을 나타내는 도면이고, 도 5는 액정분자의 구동을 나타내는 도면이다. 도면에서, θEL, θR, θE는 각각 데이터전극(108)과 공통전극(109)의 연장방향, 배향막의 배향방향, 전극(108, 109) 사이의 횡전계방향을 나타낸다. 도면에 나타낸 바와 같이, 데이터전극(108)과 공통전극(109)은 데이터배선(102)의 연장방향과 평행하게 배열된다(θEL= 90°). 배향막에 결정된 배향방향(θR)은 0°<θR<90°로서, 액정분자가 도 5에 나타낸 바와 같이 상기한 배향방향(θR)을 따라 배향된다. 전극에 전압이 인가되어 전극(108, 109) 사이에 θE=0°의 횡전계가 발생하면, 액정분자(132)가 시계방향으로 회전하여 상기한 전계방향(θE)을 따라 배향된다. 도면에서, 점선의 액정분자(132)는 전압미인가시의 액정분자이고 실선의 액정분자(133)는 전압인가시의 액정분자이다.4 is a view showing the optical axis direction of the liquid crystal display device according to the first embodiment of the present invention, Figure 5 is a view showing the driving of the liquid crystal molecules. In the figure, θ EL , θ R , θ E represent the extension direction of the data electrode 108 and the common electrode 109, the alignment direction of the alignment film, and the transverse electric field direction between the electrodes 108, 109, respectively. As shown in the figure, the data electrode 108 and the common electrode 109 are arranged in parallel with the extending direction of the data wiring 102 (θ EL = 90 °). The orientation direction θ R determined in the alignment film is 0 ° <θ R <90 °, and the liquid crystal molecules are aligned along the above-described orientation direction θ R as shown in FIG. 5. When a voltage is applied to the electrode to generate a transverse electric field of θ E = 0 ° between the electrodes 108 and 109, the liquid crystal molecules 132 are rotated clockwise to be oriented along the electric field direction θ E. In the figure, the dashed liquid crystal molecules 132 are liquid crystal molecules when no voltage is applied, and the solid liquid crystal molecules 133 are liquid crystal molecules when voltage is applied.
도 6은 본 발명이 적용된 박막트랜지스터 어레이(array)기판을 나타내는 도면이다. 도면에 나타낸 바와 같이, 종횡으로 배열되어 화소를 정의하는 게이트배선(101)과 데이터배선(102)은 각각 게이트패드(151)와 데이터패드(155)를 통해 외부구동회로에 접속된다. 상기한 게이트배선(101)과 데이터배선(102)은 박막트랜지스터로 구성된 정전기방지회로(167)를 통해 외주접지배선(165)에 접속된다. 또한, 게이트배선(101)과 데이터배선(102) 사이에도 정전기방지회로(167)가 형성되어 있다. 정전기방지회로(167)의 소스전극과 드레인전극은 데이터배선(102)에 접속된다. 또한, 공통배선(103) 역시 공통패드(157)를 통해 외부로 접지된다. 도면에는 나타내지 않았지만, 상기한 패드(151, 155, 157)는 복수의 금속층으로 구성된다. 제1금속층으로는 주로 Mo/Al층을 사용하며 제2금속층으로는 Cr층을 사용한다. 또한, 보호막(120) 위의 공통전극(109)으로 ITO/Mo막을 사용하는 경우에는 ITO를 상기한 패드(151, 155, 157) 위에 적층함으로써, 패드의 금속층이 산화되어 접촉저항이 증가하는 것을 방지할 수 있게 된다.6 illustrates a thin film transistor array substrate to which the present invention is applied. As shown in the figure, the gate wiring 101 and the data wiring 102 arranged vertically and horizontally are connected to the external driving circuit through the gate pad 151 and the data pad 155, respectively. The gate wiring 101 and the data wiring 102 are connected to the outer circumferential ground wiring 165 through an antistatic circuit 167 composed of a thin film transistor. In addition, an antistatic circuit 167 is formed between the gate wiring 101 and the data wiring 102. The source electrode and the drain electrode of the antistatic circuit 167 are connected to the data wiring 102. In addition, the common wiring 103 is also grounded to the outside through the common pad 157. Although not shown in the figure, the pads 151, 155, and 157 are composed of a plurality of metal layers. Mo / Al layer is mainly used as the first metal layer and Cr layer is used as the second metal layer. In addition, when the ITO / Mo film is used as the common electrode 109 on the passivation layer 120, the ITO is laminated on the pads 151, 155, and 157, whereby the metal layer of the pad is oxidized to increase the contact resistance. It can be prevented.
도 7은 본 발명에 따른 횡전계방식 액정표시장치의 구성을 나타내는 도면으로, 도 7(a)는 평면도이고 도 7(b)는 도 7(a)의 E-E'선 단면도이다. 도 7(a)에 나타낸 바와 같이, 표시부(140) 외부의 프레임(145) 내부에는 게이트구동회로(150)와 데이터구동회로(154)가 배치되어 게이트패드(151)와 데이터패드(155)를 통해 표시부(140)의 게이트배선(101)과 데이터배선(102)에 접속된다.7 is a view showing the configuration of a transverse electric field type liquid crystal display device according to the present invention. FIG. 7 (a) is a plan view and FIG. 7 (b) is a cross-sectional view taken along the line E-E 'of FIG. 7 (a). As shown in FIG. 7A, the gate driver circuit 150 and the data driver circuit 154 are disposed in the frame 145 outside the display unit 140 to provide the gate pad 151 and the data pad 155. The gate line 101 and the data line 102 of the display unit 140 are connected to each other.
프레임(145) 상부의 백라이트 하우징(back light housing)(147) 내에는 도 7(b)에 나타낸 바와 같이, 백라이트(148)가 장착되어 도광판(149)을 통해 액정패널(139)에 빛을 투사한다. 도광판(149)과 액정패널(139) 사이에는 투사되는 빛을 선편광시키는 편광판(135)이 부착되어 있으며, 액정패널(139)의 바깥쪽에는 검광판(136)이 부착되어 있다.As shown in FIG. 7B, a backlight 148 is mounted in the back light housing 147 on the frame 145 to project light onto the liquid crystal panel 139 through the light guide plate 149. do. A polarizing plate 135 for linearly polarizing the projected light is attached between the light guide plate 149 and the liquid crystal panel 139, and an analyzer 136 is attached to the outside of the liquid crystal panel 139.
도 8은 본 발명의 제2실시예를 나타내는 도면이다. 상기한 제2실시예는 도면에 나타낸 바와 같이, 공통전극(209)의 모양을 제외한 다른 모든 부분은 제1실시예와 동일하다. 즉, 게이트배선(201)과 데이터배선(202)의 교차점에는 박막트랜지스터가 형성되어 있으며, 화소영역 내의 데이터전극(208)은 상기한 박막트랜지스터의 소스전극(206) 및 드레인전극(207)과 동일층에 형성되어 있다. 보호막(209) 위에 배열된 공통전극(209)은 게이트배선(201) 및 데이터배선(202)의 일부분과 오버랩되며, 홀(225)을 통해 공통배선(203)에 전기적으로 접속된다. 상기한 오버랩에 의해, 공통전극(209)이 게이트배선(201)과 데이터배선(202)으로부터 발생하는 전계를 차단하여, 화면에 전경(disclination)이 발생하는 것을 방지한다. 또한, 오버랩된 부분이 블랙마스크로 작용하여 상기한 게이트배선(201)과 데이터배선(202) 근처로 빛이 새는 것을 방지하게 된다. 따라서, 제조비용을 절감할 수 있을 뿐만 아니라 제1기판(110)과 제2기판(111)의 합착불량에 의한 개구율저하가 방지된다. 제2실시에서도 차광전극(260)이 게이트전극(205)과 게이트배선(201)의 일부분 위에 형성되어 백게이트전극의 역할을 하는 동시에 백라이트 및 외부로부터 빛이 활성층(215)에 입사되는 것을 방지한다. 상기한 바와 같이, 공통전극(209)을 게이트배선(201) 및 데이터배선(202)과 오버랩시키는 경우에는 게이트배선(201)과 데이터배선(202)의 기생용량이 커져 신호지연이 발생하는 경우가 있다. 이러한 경우에는 상기한 게이트배선(201)과 데이터배선(202)을 저저항재료로 이루어진 Mo박막, Mo/Al/Mo박막, Cr/Al/Cr박을 사용하면 상기한 신호지연의 문제를 해결할 수 있게 된다.8 is a diagram showing a second embodiment of the present invention. As shown in the drawing, the second embodiment is the same as the first embodiment except for the shape of the common electrode 209. That is, a thin film transistor is formed at the intersection of the gate wiring 201 and the data wiring 202, and the data electrode 208 in the pixel region is the same as the source electrode 206 and the drain electrode 207 of the thin film transistor. Formed in layers. The common electrode 209 arranged on the passivation layer 209 overlaps the gate wiring 201 and a portion of the data wiring 202 and is electrically connected to the common wiring 203 through the hole 225. As a result of the overlap, the common electrode 209 blocks the electric field generated from the gate wiring 201 and the data wiring 202 to prevent the occurrence of foreground on the screen. In addition, the overlapped portion serves as a black mask to prevent light from leaking near the gate wiring 201 and the data wiring 202. Therefore, not only the manufacturing cost can be reduced, but also the opening ratio decrease due to the poor bonding of the first substrate 110 and the second substrate 111 can be prevented. Also in the second embodiment, the light blocking electrode 260 is formed on a portion of the gate electrode 205 and the gate wiring 201 to serve as a back gate electrode and to prevent light from being incident on the active layer 215 from the backlight and the outside. . As described above, when the common electrode 209 overlaps the gate wiring 201 and the data wiring 202, parasitic capacitances of the gate wiring 201 and the data wiring 202 may increase, resulting in signal delay. have. In this case, if the gate wiring 201 and the data wiring 202 are used as the Mo thin film, the Mo / Al / Mo thin film, and the Cr / Al / Cr foil made of a low resistance material, the above problem of signal delay can be solved. Will be.
본 발명은 상기한 바와 같이, 차광층이 박막트랜지스터로 빛이 입사되는 것을 방지하는 종래의 액정표시장치와는 달리, 게이트전극 및 게이트배선의 일부분 위에 차광전극이 형성되어 백게이트전극의 역할을 함과 동시에 박막트랜지스터의 활성층으로 빛이 입사되어 누설전류가 발생하는 것을 방지하기 때문에, 화질이 향상되고 고정세의 횡전계방식 액정표시장치의 제조가 가능하며, 제조비용도 대폭 절감된다. 또한, 공통전극이 게이트배선과 데이터배선의 일부분과 오버랩되어 있기 때문에, 종래의 횡전계방식 액정표시장치에서 상기한 게이트배선과 데이터배선에 의한 크로스토크의 발생을 방지하기 위해 실제로 화소영역이 구현되는 화소영역을 상기한 게이트배선과 데이터배선을 일정 거리 이상 떨어지게 형성하는 것에 비해 개구율이 대폭 향상된다.As described above, unlike the conventional liquid crystal display device in which the light blocking layer prevents light from entering the thin film transistor, the light blocking electrode is formed on a portion of the gate electrode and the gate wiring to serve as a back gate electrode. At the same time, since light is prevented from being incident on the active layer of the thin film transistor to prevent leakage current, the image quality can be improved, and a high-definition transverse electric field type liquid crystal display device can be manufactured, and manufacturing cost can be greatly reduced. In addition, since the common electrode overlaps a part of the gate wiring and the data wiring, the pixel region is actually implemented in order to prevent crosstalk caused by the gate wiring and the data wiring in the conventional transverse type liquid crystal display device. The aperture ratio is significantly improved compared with forming the pixel region such that the gate wiring and the data wiring are separated by a predetermined distance or more.
Claims (42)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970036569A KR100251655B1 (en) | 1997-07-31 | 1997-07-31 | Transverse electric field liquid crystal display device |
US09/116,707 US6335770B1 (en) | 1997-07-22 | 1998-07-17 | In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode |
US09/116,707 US20010055074A1 (en) | 1997-07-22 | 1998-07-17 | In-plane switching mode lcd with specific arrangement of common bus line, data electrode, and common electrode |
US09/613,730 US6400436B1 (en) | 1997-07-22 | 2000-07-11 | In-plane switching mode liquid crystal display device with specific arrangement of common bus line, data electrode and common electrode |
US10/015,765 US6803982B2 (en) | 1997-07-22 | 2001-12-17 | In-plane switching mode liquid crystal display device including common electrode on passivation layer which is formed over TFT and data electrode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970036569A KR100251655B1 (en) | 1997-07-31 | 1997-07-31 | Transverse electric field liquid crystal display device |
Publications (2)
Publication Number | Publication Date |
---|---|
KR19990012987A true KR19990012987A (en) | 1999-02-25 |
KR100251655B1 KR100251655B1 (en) | 2000-04-15 |
Family
ID=19516516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970036569A KR100251655B1 (en) | 1997-07-22 | 1997-07-31 | Transverse electric field liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR100251655B1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100504531B1 (en) * | 1999-12-15 | 2005-08-03 | 엘지.필립스 엘시디 주식회사 | An in-plane switching mode liquid crystal display device |
US7441420B2 (en) | 2000-12-01 | 2008-10-28 | Lg Electronics Inc. | Device for fastening tub to move drum type washing machine |
KR101110005B1 (en) * | 2005-03-10 | 2012-01-31 | 엘지디스플레이 주식회사 | Liquid crystal display device prevented light leakage in the pixel portion |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3774858B2 (en) * | 2001-04-07 | 2006-05-17 | 大林精工株式会社 | Liquid crystal display device and driving method thereof |
KR101080356B1 (en) * | 2003-10-13 | 2011-11-04 | 삼성전자주식회사 | Thin film transistor, thin film transistor array panel, and display device |
CN105425482A (en) * | 2016-01-18 | 2016-03-23 | 京东方科技集团股份有限公司 | Liquid crystal display panel and display device |
-
1997
- 1997-07-31 KR KR1019970036569A patent/KR100251655B1/en active IP Right Grant
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100504531B1 (en) * | 1999-12-15 | 2005-08-03 | 엘지.필립스 엘시디 주식회사 | An in-plane switching mode liquid crystal display device |
US7441420B2 (en) | 2000-12-01 | 2008-10-28 | Lg Electronics Inc. | Device for fastening tub to move drum type washing machine |
KR101110005B1 (en) * | 2005-03-10 | 2012-01-31 | 엘지디스플레이 주식회사 | Liquid crystal display device prevented light leakage in the pixel portion |
Also Published As
Publication number | Publication date |
---|---|
KR100251655B1 (en) | 2000-04-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR100251512B1 (en) | Transverse electric field liquid crystal display device | |
US6335770B1 (en) | In-plane switching mode LCD with specific arrangement of common bus line, data electrode, and common electrode | |
KR100257370B1 (en) | In plane switching mode liquid crystal display device | |
US6710835B2 (en) | Liquid crystal display device with stacked insulating film of different layers | |
KR100293436B1 (en) | In plane switching mode liquid crystal display device | |
WO2001018597A1 (en) | Liquid crystal display device | |
JP3792670B2 (en) | Horizontal electric field type active matrix liquid crystal display device and method for manufacturing the same | |
KR100257976B1 (en) | An in-plane switching mode liquid crystal display device | |
KR100218697B1 (en) | LCD | |
KR100269351B1 (en) | Ips typed lcd device | |
JP3199221B2 (en) | Liquid crystal display device and manufacturing method thereof | |
KR100251655B1 (en) | Transverse electric field liquid crystal display device | |
KR100244730B1 (en) | A method for fabricating liquid crystal display device | |
KR19990012990A (en) | Transverse electric field liquid crystal display device and manufacturing method thereof | |
KR100411974B1 (en) | Liquid crystal display device | |
JP4121357B2 (en) | Liquid crystal display | |
KR100269354B1 (en) | In-plain switching type lcd | |
JPH09171175A (en) | Liquid crystal display element | |
JP2007057752A (en) | Liquid crystal device | |
KR100282330B1 (en) | In plane switching mode liquid crystal display device having electrode structre applying inclined electric field | |
JPH08146425A (en) | Liquid crystal display element | |
KR19990012988A (en) | Transverse electric field liquid crystal display device | |
JPH09171181A (en) | Liquid crystal display element | |
KR20030055930A (en) | Liquid crystal display device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19970731 |
|
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19970731 Comment text: Request for Examination of Application |
|
PG1501 | Laying open of application | ||
N231 | Notification of change of applicant | ||
PN2301 | Change of applicant |
Patent event date: 19990903 Comment text: Notification of Change of Applicant Patent event code: PN23011R01D |
|
E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19991016 |
|
GRNT | Written decision to grant | ||
PR0701 | Registration of establishment |
Comment text: Registration of Establishment Patent event date: 20000113 Patent event code: PR07011E01D |
|
PR1002 | Payment of registration fee |
Payment date: 20000114 End annual number: 3 Start annual number: 1 |
|
PG1601 | Publication of registration | ||
PR1001 | Payment of annual fee |
Payment date: 20021231 Start annual number: 4 End annual number: 4 |
|
PR1001 | Payment of annual fee |
Payment date: 20031229 Start annual number: 5 End annual number: 5 |
|
PR1001 | Payment of annual fee |
Payment date: 20041229 Start annual number: 6 End annual number: 6 |
|
PR1001 | Payment of annual fee |
Payment date: 20051229 Start annual number: 7 End annual number: 7 |
|
PR1001 | Payment of annual fee |
Payment date: 20061229 Start annual number: 8 End annual number: 8 |
|
PR1001 | Payment of annual fee |
Payment date: 20071231 Start annual number: 9 End annual number: 9 |
|
PR1001 | Payment of annual fee |
Payment date: 20090102 Start annual number: 10 End annual number: 10 |
|
PR1001 | Payment of annual fee |
Payment date: 20091218 Start annual number: 11 End annual number: 11 |
|
PR1001 | Payment of annual fee |
Payment date: 20101228 Start annual number: 12 End annual number: 12 |
|
PR1001 | Payment of annual fee |
Payment date: 20111221 Start annual number: 13 End annual number: 13 |
|
FPAY | Annual fee payment |
Payment date: 20121228 Year of fee payment: 14 |
|
PR1001 | Payment of annual fee |
Payment date: 20121228 Start annual number: 14 End annual number: 14 |
|
FPAY | Annual fee payment |
Payment date: 20131227 Year of fee payment: 15 |
|
PR1001 | Payment of annual fee |
Payment date: 20131227 Start annual number: 15 End annual number: 15 |
|
FPAY | Annual fee payment |
Payment date: 20141230 Year of fee payment: 16 |
|
PR1001 | Payment of annual fee |
Payment date: 20141230 Start annual number: 16 End annual number: 16 |
|
FPAY | Annual fee payment |
Payment date: 20151228 Year of fee payment: 17 |
|
PR1001 | Payment of annual fee |
Payment date: 20151228 Start annual number: 17 End annual number: 17 |
|
FPAY | Annual fee payment |
Payment date: 20161214 Year of fee payment: 18 |
|
PR1001 | Payment of annual fee |
Payment date: 20161214 Start annual number: 18 End annual number: 18 |
|
PC1801 | Expiration of term |