KR19990010739A - Morse transistor for power and manufacturing method thereof - Google Patents

Abstract

MOS transistor for power and a manufacturing method thereof. The MOS transistor according to the present invention reduces the area of the gate conductive layer by forming a thick oxide film instead of the gate oxide film and the gate conductive film on a part of the surface of the semiconductor substrate where no channel is formed. Therefore, the parasitic capacitance existing in the gate oxide film between the gate conductive layer and the semiconductor substrate can be reduced.

Description

Morse transistor for power and manufacturing method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS transistor for power and a method of manufacturing the same, and more particularly, to a MOS transistor for power capable of reducing power loss generated during switching and a method of manufacturing the MOS transistor.

In general, a MOS transistor for power has a first high input impedance as compared with a bipolar transistor. Therefore, the gyro driving circuit is very simple. Second, since it is a unipolar device, accumulation by minor carriers during the turn- And there is no time delay caused by recombination. Accordingly, the use of a switching mode power supply, a lamp ballast, and a motor driving circuit is gradually spreading.

When such a MOS transistor for power is used as a switching element, it is known that power loss occurs due to two causes. One is power loss due to switching time delay and the other is due to on resistance Power loss. Among them, the power loss caused by the switching time delay is mainly caused by the parasitic capacitors existing in the MOS transistor.

FIG. 1 is a cross-sectional view illustrating parasitic capacitance components existing in a conventional MOS transistor for power, in which reference numeral 10 denotes an n-type semiconductor substrate, 12 denotes a gate oxide film, and 14 denotes a gate polysilicon layer , Numeral 16 denotes a p-type well, numeral 18 denotes an n-type source, numeral 20 denotes an insulating layer for insulating the gate polysilicon layer, numeral 22 denotes a metal layer connected to the source, Represents the parasitic capacitance present.

1, the parasitic capacitance existing in the MOS transistor is determined by the first, second, and third capacitances C1, C2, and C3 present in the gate oxide film 12, the fourth capacitance C4 present on the surface of the p-type well 16 and the fifth capacitance C5 existing in the depletion region of the surface of the n-type substrate 10 below the gate oxide film 12 , And a sixth capacitance (C6) present in the depletion region adjacent to the well (16). The capacitances may also be divided into an input capacitance (Ciss) component, an output capacitance (Coss) component, and a reverse capacitance (Crss) component. (C3 * C5) / (C3 + C5) / (C3 + C5) and the output capacitance (Coss) C5) + C6 and the reverse capacitance (Crss) can be expressed by (C3 * C5) / (C3 + C5), respectively.

The parasitic capacitances classified as described above cause a switching time delay due to the RC time delay when switching the MOS transistor for power, resulting in power loss of the MOS transistor. Accordingly, it is desirable to reduce the parasitic capacitances as described above to prevent switching time delay and power loss.

SUMMARY OF THE INVENTION The present invention provides a MOS transistor for power capable of preventing a power loss due to a switching time delay of a MOS transistor for power.

Another aspect of the present invention is to provide a manufacturing method suitable for fabricating the MOS transistor for power.

1 is a cross-sectional view illustrating parasitic capacitance components existing in a conventional MOS transistor for power.

2 is a schematic plan view of a MOS transistor for power according to an embodiment of the present invention.

3 is a schematic vertical cross-sectional view of a MOS transistor for power according to an embodiment of the present invention.

4 to 7 are cross-sectional views illustrating a method of fabricating a MOS transistor for power according to an embodiment of the present invention.

According to an aspect of the present invention, there is provided a MOS transistor for power comprising a semiconductor substrate of a first conductivity type, a well of a second conductivity type formed in the semiconductor substrate, a source of a first conductivity type formed in the well, A gate oxide layer formed on the surface of the well, a gate conductive layer formed on the gate oxide layer, and a gate oxide layer and a gate conductive layer formed on the surface of the semiconductor substrate except for the source and the well, And an oxide film formed so as to surround it.

The MOS transistor for power may further include an interlayer insulating layer covering the gate conductive layer and the upper portion of the oxide film, and wiring layers formed on the interlayer insulating layer and electrically connected to the source and gate conductive layers.

According to another aspect of the present invention, there is provided a method of fabricating a MOS transistor for power, comprising: forming a selectively thick oxide film on a surface of a first conductive semiconductor substrate; forming a gate oxide film on the surface of the semiconductor substrate, A conductive layer is selectively formed to surround the oxide film. Next, the oxide film and the gate conductive layer are used as a mask, impurities of the second conductivity type are injected into the semiconductor substrate to form wells, and impurities of the first conductivity type are injected into the wells to form a source.

Here, an epitaxial layer of the same conductivity type as that of the semiconductor substrate can be further formed on the semiconductor substrate before forming the oxide film.

The well may also be formed by implanting impurities of a low concentration second conductivity type using the oxide film and the gate conductive layer as masks, forming a mask pattern on the resultant, and then using the mask pattern to form a high concentration second conductivity type After impurities are selectively implanted, they can be formed by drive-in.

As described above, the MOS transistor for power according to the present invention reduces the area of the gate conductive layer by forming a thick oxide film instead of the gate oxide film and the gate conductive layer on a part of the surface of the semiconductor substrate where no channel is formed. Therefore, the parasitic capacitance existing in the MOS transistor, in particular, the parasitic capacitance existing in the gate oxide film between the gate conductive layer and the semiconductor substrate can be effectively reduced.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It will be apparent to those skilled in the art that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know. When any film is referred to as being present on another film or substrate in the embodiments described below, it may be directly on another film or substrate, or a layered film may be present. In the drawings, the same reference numerals denote the same members.

FIG. 2 is a schematic plan view of a MOS transistor for power according to an embodiment of the present invention, and FIG. 3 is a vertical sectional view.

2 and 3, the MOS transistor for power according to the present invention includes a semiconductor substrate 50 of a first conductivity type, a well 60 of a second conductivity type formed in the semiconductor substrate 50, A gate conductive layer 56 formed on the gate oxide layer 54 and a gate insulating layer 56 formed on the gate oxide layer 54. The first conductive type source 70 is formed in the well, An oxide film 52 formed by being surrounded by the gate conductive layer 56, an interlayer insulating layer 80 covering the upper portion of the gate conductive layer 56 and the oxide film 52, And a metal layer 85 electrically connected to the source 70.

Here, the first conductivity type may be n-type, and the second conductivity type may be p-type.

The oxide layer 52 according to the present invention is formed to be thickly surrounded by the gate conductive layer 56 so that the area of the gate conductive layer 56 is reduced by the area where the oxide layer 52 is formed. At this time, the oxide layer 52 formed instead of the gate conductive layer 56 is preferably formed on the surface of the substrate 50.

As the area of the gate conductive layer 56 is reduced, the parasitic capacitance also decreases as shown in the following equation.

C = .

Here,? Represents the dielectric constant, A represents the plate area, and d represents the thickness of the dielectric film.

That is, the parasitic capacitance existing in the gate oxide film 54 is affected by the area of the gate conductive layer 56 and the thickness of the gate oxide film 54, and the parasitic capacitance existing in the area of the gate conductive layer 56 The parasitic capacitance existing in the MOS transistor can be reduced.

According to the present invention, parasitic capacitance (C3 in FIG. 1) present in the gate oxide film 54 between the gate conductive layer 56 and the semiconductor substrate 50 can be effectively reduced.

4 to 7 are cross-sectional views illustrating a method of fabricating a MOS transistor for power according to an embodiment of the present invention, wherein like reference numerals refer to like elements throughout the drawings, In addition to the steps, various steps can be added to improve the characteristics of the MOS transistor.

Referring to FIG. 4, first, a thick oxide film 52 is selectively formed on one surface of the first conductive semiconductor substrate 50.

The oxide film 52 may be formed by a conventionally known method such as a thermal oxidation process, a chemical vapor deposition (CVD) process, or the like. According to a preferred embodiment of the present invention, an epitaxial layer of the same conductivity type as that of the semiconductor substrate 50 may be formed on the semiconductor substrate 50.

5, a gate oxide layer 54 and a gate conductive layer 56 are selectively formed on the surface of the semiconductor substrate 50 on which the oxide film 52 is formed.

At this time, the gate oxide film 54 and the gate conductive layer 56 are formed to surround the oxide film 52. According to a preferred embodiment of the present invention, the gate oxide layer 54 is formed by a thermal oxidation process, a conductive material such as polysilicon is deposited thereon, and then patterned to form the gate conductive layer 56.

Referring to FIG. 6, the oxide film 52 and the gate conductive layer 56 are used as a mask, and impurities of a second conductivity type are implanted into the semiconductor substrate 50 to form a well 60. A mask for forming a source is formed on the resultant structure in which the well 60 is formed, and the source 70 is formed by implanting impurities of the first conductivity type into the well 60 using the mask.

At this time, in order to improve the breakdown voltage characteristic, the well 60 is formed by first implanting a low concentration second conductivity type impurity, selectively implanting a high concentration second conductivity type impurity using a mask process, As shown in Fig.

7, an insulation layer 80 is formed by applying an insulating material such as PSG to the entire surface of the resultant structure where the well 60 and the source 70 are formed, and the insulating layer 80 is patterned to form the source contact holes h And a gate contact hole (not shown). Subsequently, a conductive material, such as metal, is deposited on the entire surface of the resultant product in which the source and gate contact holes are formed, and then patterned to form a wiring layer, for example, a source wiring layer 85 electrically connected to the source 70.

As described above, the MOS transistor for power according to the present invention reduces the area of the gate conductive layer by forming a thick oxide film instead of the gate oxide film and the gate conductive layer on a part of the surface of the semiconductor substrate where no channel is formed. Therefore, the parasitic capacitance existing in the MOS transistor for power can be effectively reduced, in particular, the parasitic capacitance existing in the gate oxide film between the gate conductive layer and the semiconductor substrate.

Claims (7)

A semiconductor substrate of a first conductivity type; A well of a second conductivity type formed in the semiconductor substrate; A source of a first conductivity type formed in the well; A gate oxide film formed on the upper surface of the well; A gate conductive layer formed on the gate oxide film; And an oxide film formed thicker than a gate oxide film and a gate conductive layer on a part of the surface of the semiconductor substrate excluding the source and the well and formed to be surrounded by the gate conductive layer. The power MOS transistor according to claim 1, further comprising: an interlayer insulating layer covering the gate conductive layer and the upper portion of the oxide film; Further comprising wiring layers formed on the interlayer insulating layer and electrically connected to the source and gate conductive layers. The MOS transistor for power according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type. Forming a selectively thick oxide film on one surface of the semiconductor substrate of the first conductivity type; Selectively forming a gate oxide layer and a gate conductive layer on the surface of the semiconductor substrate on which the oxide layer is formed, surrounding the oxide layer; Implanting impurities of a second conductivity type into the semiconductor substrate using the oxide film and the gate conductive layer as masks to form wells; And implanting impurities of a first conductivity type into the well to form a source. 5. The method according to claim 4, further comprising forming an epitaxial layer of the same conductivity type as the semiconductor substrate (50) on the semiconductor substrate (50) before the step of forming an oxide film Method of manufacturing MOS transistor. 5. The method of claim 4, wherein the forming of the well comprises: implanting impurities of a second conductivity type of low concentration using the oxide film and the gate conductive layer as a mask; Forming a mask pattern on the resultant; And selectively implanting a high-concentration second-conductivity-type impurity using the mask pattern, followed by driving-in the impurity. 5. The method of claim 4, further comprising: forming an insulating layer by coating an insulating material on the entire surface of the resultant formed with the well and the source, after the step of forming the source; Patterning the insulating layer to form a source contact hole and a gate contact hole; And forming wiring layers by depositing a conductive material on the entire surface of the resultant structure having the source and gate contact holes and then patterning the conductive material.